Introduction to Xilinx System Generator Part II. Evan Everett and Michael Wu ELEC Spring 2013

Transcription

1 Introduction to Xilinx System Generator Part II Evan Everett and Michael Wu ELEC Spring 2013

2 Outline Introduction to FPGAs and Xilinx System Generator System Generator basics Fixed point data representation Sample times Tips for building models

3 Fixed Point Binary Numbers MATLAB generally uses high precision values 64-bit floating point - huge dynamic range Impractical in hardware System Generator uses fixed point numbers instead Limited, but flexible, range & precision Pro: smaller hardware Con: requires attention to overflow & quantization

4 Fixed-Point Representation total bits fractional bits unsigned UFix8_ = total bits 8-5 = 3 integer bits 5 fractional bits

5 Fixed-Point Representation total bits fractional bits signed Fix8_ = total bits 8-4 = 4 integer bits 4 fractional bits

6 Range vs. Precision Unsigned UFix4_ Signed Fix4_

7 Range vs. Precision Unsigned UFix4_ Signed Fix4_

8 Range vs. Precision Unsigned UFix4_ Signed Fix4_

9 Fixed Point Arithmetic Addition & multiplication are provided Adders use general logic Multipliers use dedicated blocks Division expensive to implement and rarely used Multi-cycle operation Try to replace with shifts

10 Fixed Point Arithmetic More bits needed with each operation for full precision N bit M bit + max(n,m)+1 bit (integer growth) N bit M bit N+M bit (integer and fractional growth) May not always want to expand bitwidth, but must understand risk of overflow and/or quantization N bit N bit + N bit (overflow risk) N bit N bit N bit (integer overflow; fractional quantization)

11 Fixed Point Quantization Occurs when available fractional bits are insufficient Truncate (default): just drop bits past LSB; more efficient Round: choose nearest representable value Full Precision (UFix_11_8) Truncated (UFix_8_5) Rounded (UFix_8_5) (Δ= ) (Δ= )

12 Fixed Point Overflow Occurs when available integer bits are insufficient Required bits increase with every operation This can add up very fast Think of a long FIR filter Most blocks Error on Overflow option Great for debugging in simulation Sim stops with error when overflow occurs Overflow in hardware is very hard to isolate: simulate to check first

13 Fixed Point Overflow Overflow Options UFix_4_2 + UFix_4_ UFix_5_ Full Precision - No overflow Notice the bit growth

14 Fixed Point Overflow Overflow Options 2.50 UFix_4_ UFix_4_ UFix_4_ Wrap Happens by default in hardware if you don t give enough bits Not always bad; sometimes this is intentional Often the source of nonsensical results

15 Fixed Point Overflow Overflow Options 2.50 UFix_4_ UFix_4_ UFix_4_ Saturate Stops at max/min to prevent overflow Sign of answer will be correct More expensive in hardware (requires comparator & mux for every operation)

16 System Generator Clocking Both simulation and hardware are discrete time Model has a master system sample period Related to FPGA clock in System Generator token An x sec system period = 1 FPGA clock period System Generator

17 Multiple Clock Domains All clock domains are multiples of master System Period Every other clock period is derived from master FPGA clock period System sample period must be the smallest period in the model System Generator

18 System Generator Clocking Sample periods propagate with signals Some blocks can override the propagation Feedback loops often require explicit sample periods Most blocks are single rate (eq. logic & arithmetic) Many blocks are multi-rate: upsample & downsample, interpolate & decimate, serial-parallel conversion

19 Multiple Clock Domains Example Upsample, filter, and downsample a 25 MHz (40 ns) signal FPGA Clock period = 40 ns System Generator System period = 1 Sample period = MHz 50 MHz Error: sample rates not multiple of sample period

20 Multiple Clock Domains Example Upsample, filter, and downsample a 25 MHz (40 ns) signal System Generator FPGA Clock period = 20 ns System period = 1 Sample period = 2 25 MHz 50 MHz

21 Sample Times Example Upsample Blocks Downsample Blocks Use sample time colors!

22 Resource Estimation Any model of any size can be simulated Device resource limitations affect HW implementation Sysgen provides Resource Estimator block Adds up resource requirements before synthesis Good estimate - but not always right! Only post-place & route report is guaranteed Slice count usually matters most

23 System Generator Tips Show port data types and sample times Use variables instead of constants, initialize in a script Avoid explicit sample periods (except for feedback loops) Use keyboard shortcuts ctrl-click to wire blocks ctrl-drag to duplicate selected blocks ctrl-d to update/error check model Use subsystems and give them meaningful names Too much precision is okay at first, use Error on Overflow to optimize later Avoid saturation and rounding options

24 System Generator Example Gateway In: Gate way Out: UFix10_0 Accumulator: 10 bit output Add Wrap ROMs: Output: Fix16_15 Depth: 1024 Initial Values: cos(2π[0:1023]/1024) sin(2π[0:1023]/1024)

25 System Generator Example ROMs: Depth: 1024 Initial Values: cos(2π[0:1023]/1024) sin(2π[0:1023]/1024)