Intel Q3GM ES Layout and DFM Feature Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor and electronics technology, please call Sales at Chipworks. 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: 613.829.0414 Fax: 613.829.0515 www.chipworks.com
Layout and DFM Feature Analysis Table of Contents 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device and Report Overview 1.6 Device Summary 1.7 Brief Comparison to Intel 45 nm Process Technology 2 Device Overview 2.1 Package and Die 2.2 CPU (8PWSCA Die Markings) Die Features and Die Utilization 3 Estimated Design Rules 3. and Summary Tables 4 Layer-by-Layer Design Rule and DFM Analysis 4. 4.2 Metal 8, Metal 9, and Via 8s 4.3 Metal 7 through Metal 4 and Via 7s through Via 4s 4.4 Metal 3 Through Metal 1 and Via 3s Through Via 1s 4.5 Via 0s, Metal 0, Contacts, and Transistor Gates 4.6 Isolation and Substrate 5 Selected Layout Feature Analysis 5. 5.2 Logic Region Features 5.3 L3 Cache SRAM 6 ICWorks Surveyor Circuit Layout Analysis 6. 6.2 Bevel Sample Layout Files 6.3 Targeted Region Files (L1/L2/L3 Cache, Standard Logic, and I/Os) 7 References 8 Statement of Measurement Uncertainty and Scope Variation About Chipworks
Overview 1-1 1.1 List of Figures 1.4.1 ICWorks Surveyor Folders 1.4.2 Example ICWorks Surveyor Window Bevel Sample 1.4.3 Example ICWorks Surveyor Window Interactive Regions 2 Device Overview 2.1.1 Package Top 2.1.2 Package and Lid 2.1.3 CPU Die Photograph (8PWSCA Die Markings) 2.1.4 8PWSCA Die Markings 2.1.5 8PWSCA Die Markings (RDL Removed) 2.1.6 8PWSCA Die Photograph (RDL Removed) 2.1.7 Metal 1 CPU Die Photograph 2.2.1 CPU Die Corner A 2.2.2 CPU Die Corner B 2.2.3 CPU Die Corner C 2.2.4 CPU Die Corner D 2.2.5 High Density Bump Via Windows (on CPU) 2.2.6 CPU Die Utilization Analysis 2.2.7 CPU Standard Logic Cell Size 3 Estimated Design Rules 3.1.1 Interconnect Measurement Reference 3.1.2 Interconnect Scaling Minimum Feature Size/Pitch 4 Layer-by-Layer Design Rule and DFM Analysis 4.2.1 General Metal 9 Patterning 4.2.2 Metal 9 Minimum Feature Size 4.2.3 Via 8 Distribution 4.2.4 Via 8 Pitch 4.2.5 General Metal 8 Patterning (A) 4.2.6 General Metal 8 Patterning (B) 4.2.7 Metal 8 Minimum Feature Size 4.2.8 Metal 8 Orthogonal Routing 4.2.9 Metal 8 Minimum Gap 4.3.1 Via 7 Overview 4.3.2 Via 7 Distribution 4.3.3 Via 7 Pitch 4.3.4 Metal 7 Minimum Feature Size 4.3.5 Metal 7 Orthogonal Routing 4.3.6 Via 6 Pitch 4.3.7 General Metal 6 Patterning 4.3.8 Metal 6 Minimum Feature Size 4.3.9 Metal 6 Orthogonal Routing
Overview 1-2 4.3.10 Via 5 Distribution 4.3.11 Via 5 Pitch 4.3.12 Metal 5 Minimum Feature Size, Orthogonal Routing 4.3.13 Metal 5 Minimum Line End-to-End Gap 4.3.14 Planar TEM of Metal 5 (A) 4.3.15 Planar TEM of Metal 5 (B) 4.3.16 Via 4 Pitch 4.3.17 Planar TEM of Via 4 and Metal 4 4.3.18 Metal 4 Minimum Feature Size 4.3.19 Metal 4 Orthogonal Routing 4.4.1 Via 3 Distribution 4.4.2 Via 3 Pitch 4.4.3 Metal 3 Minimum Feature Size 4.4.4 Metal 3 Orthogonal Routing 4.4.5 Via 2 Pitch 4.4.6 Via 2 Distribution 4.4.7 Metal 2 Minimum Feature Size 4.4.8 Metal 2 Minimum Line End-to-End Gap 4.4.9 Via 1 Distribution 4.4.10 Via 1 Pitch 4.4.11 Metal (Standard Logic Region) 4.4.12 Metal 1 Pitch 4.4.13 Metal 1 Line End Uniformity (A) 4.4.14 Metal 1 Line End Uniformity (B) 4.4.15 Metal 4.4.16 Metal 1 Line End-to-End Gap 4.5.1 Via 0 Pitch 4.5.2 Metal 0 Minimum Feature Size 4.5.3 Metal 0 Distribution 4.5.4 Contacted Gate Pitch 4.5.5 General Gate and Local Interconnect Layout 4.5.6 Gate End Uniformity 4.5.7 Planar TEM of PMOS Gate Fingers 4.5.8 Planar TEM of Dummy Gate Structure (PMOS Gate Metal) 4.5.9 Planar TEM of NMOS Gate Fingers 4.5.10 Planar TEM of Dummy NMOS Gate 4.5.11 Multiple Width Gate Metal 4.5.12 TEM Micrograph Cross Section of Wide NMOS Gate 4.6.1 Diffusion Level Layout (A) 4.6.2 Diffusion Level Layout (B)
Overview 1-3 5 Selected Layout Feature Analysis 5.2.1 Standard Logic Dummy Pattern at Metal 1 5.2.2 Standard Logic Dummy Pattern at Gate Level 5.2.3 Standard Logic Dummy Pattern at Diffusion 5.2.4 Alignment Feature at Metal 1 5.2.5 Alignment Feature at Gate Level 5.2.6 Alignment Feature at Diffusion 5.3.1 Edge of L3 Cache Array Metal 1 5.3.2 Edge of L3 Cache Array Gate Level 5.3.3 Edge of L3 Cache Array Diffusion 5.3.4 L3 Cache SRAM at Metal 3 5.3.5 L3 Cache SRAM at Metal 2 5.3.6 L3 Cache SRAM at Metal 1 5.3.7 L3 Cache SRAM at Gate Level 5.3.8 L3 Cache SRAM at Diffusion Level 5.3.9 Planar TEM of L3 Cache at Metal 0 5.3.10 Planar TEM of L3 Cache at Gate/Metal Level 5.3.11 Planar TEM of L3 Cache at Gate/W Contact Level 5.3.12 Planar TEM of L3 Cache at Active Silicon Level 6 ICWorks Surveyor Circuit Layout Analysis 6.2.1 Bevel Sample Location 6.2.2 Bevel Sample Analysis Sites 6.3.1 Interactive Layer Analysis Imaging Sites 6.3.2 Example ICWorks Surveyor Screen Shot All Levels 1.2 List of Tables 1.5.1 Available Companion Reports on Intel 32 nm 1.5.2 Device Identification 1.6.1 8PWSCA Die Summary 1.7.1 Comparison of Intel 45 nm Process to 32 nm Process 2 Device Overview 2.2.1 CPU Die Utilization 2.2.2 CPU Package, Die, and Standard Logic Cell Size 3 Estimated Design Rules 3.1.1 Estimated Interconnect Design Rules 3.1.2 Estimated Via and Contact Design Rules 3.1.3 Estimated Transistor and Isolation Design Rules 4 Layer-by-Layer Design Rule and DFM Analysis 4.5.1 Observed Gate Finger Widths 6 ICWorks Surveyor Circuit Layout Analysis 6.2.1 Bevel Site and Software Folder Sample Reference 6.3.1 Targeted Region Interactive Files
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