High Performance Packaging what does the future hold? Grace O'Malley inemi

High Performance Packaging what does the future hold? Grace O'Malley inemi

What is High Performance Packaging? 1

What is High Performance Packaging? Meets Performance Electrical Thermal Mechanical Environmental Protection Highly Reliable Life time Operating conditions At an acceptable Cost 2

Objectives Overview of what's happening in the electronics manufacturing industry Highlights from the inemi Packaging Roadmap Packaging trends in general High performance packaging technologies Challenges 3

inemi Overview & Roadmap

About inemi Mission: Forecast and Accelerate improvements in the Electronics Manufacturing Industry for a Sustainable Future. 5 Key Deliverables: Technology Roadmaps Collaborative Deployment Projects Research Priorities Documents Proactive Forums Position Papers International Electronics Manufacturing Initiative (inemi) is an industry-led consortium of over 100 global manufacturers, suppliers, industry associations, government agencies and universities. Working on advancing manufacturing technology since 1994. Visit us at www.inemi.org. 5 5

2013 Roadmap > 650 participants > 350 companies/organizations 18 countries from 4 continents 20 Technology Working Groups (TWGs) 6 Product Emulator Groups (PEGs) > 8 Man Years of Development Time > 1900 pages of information Roadmaps the needs for 2013-2023 7

inemi Roadmap Biannual Process 21 Technology Working Groups (TWGs) Modeling, Simulation, and Design Connectors RF Components & Subsystems Test, Inspection & Measurement Solid State Illumination Large Area, Flexible Electronics Semiconductor Technology Photovoltaics MEMS/ Sensors Packaging & Component Substrates Passive Components Optoelectronics Thermal Management Mass Storage (Magnetic & Optical) Ceramic Substrates Energy Storage & Conversion Systems Organic PCB Board Assembly Final Assembly Customer Information Management Systems Environmentally Conscious Electronics Red=Business Green=Engineering Purple=Manufacturing Blue=Component & Subsystem 9

Portable / Consumer Office Systems Defense and Aerospace Medical Products Automotive High-End Systems Roadmap Development Product Sector Needs Vs. Technology Evolution TWGs (20) Product Emulator Groups Semiconductor Technology Business Processes Prod Lifecycle Information Mgmt. Design Technologies Modeling, Thermal, etc. Manufacturing Technologies Board Assy, Test, etc. Comp./Subsyst. Technologies Packaging, Substrates, Displays, etc. 10

Selected Parameters for Automotive Electronics Year of Production 2015 2017 2019 2021 2023 2025 Battery performancefor HEV (Power oriented development) Power density per weight (W/kg) 4000 4300 4450 4550 4650 4750 Energy density per weight (Wh/kg) 105 115 125 133 138 142 Battery performancefor BEV (Energy oriented development) Power density per weight (W/kg) 1350 1430 1480 1530 1580 1600 Energy density per weight (Wh/kg) 220 235 245 255 265 270 Capacitor pack (F) 227 240 254 260 260 260 Power devices Inverter power density (W/cm3) 13 20 25 35 45 55 Specific on-resistance at breakdown voltage of 1.2kV [mohm*cm2@1.2kv] 5 4 3 2 2 2 Max junction temperature (degree C) 220 240 260 270 280 290 Rthja required for inverter power density (W/cm3) with regard to Ta of 125deg C (deg C/W/cm3) 7.3 5.8 5.4 4.1 3.4 3.0 Max mold temperature (deg C) 200 200 200 200 200 200 package termical resistance (m Ohm) 0.16 0.16 0.16 0.16 0.16 0.16 Logic devices Temperature attached to engine (degree C) 155 175 175 175 175 175 Max junction temperature (degree C) 160 175 180 185 190 195 11

Thirteen Contributing Industry Organizations Semiconductors inemi / ITRS / MIG/PSMA Packaging TWG inemi / MIG / ITRS MEMS TWG inemi / IPC / EIPC / TPCA Organic PWB TWG Organic Printed Circuit Boards Interconnect Substrates Ceramic inemi Board Assembly TWG inemi Roadmap inemi Information Management TWG Supply Chain Management inemi Optoelectronics TWG inemi Mass Data Storage TWG Magnetic and Optical Storage Optoelectronics and Optical Storage 12

Key Industry Trends & Drivers

Integration driving Growth User Interface + Smaller Form Factor + Lower Prices + New Services Source: Morgan Stanley Estimates 14

Overall Key Trends Convergence - pace of product enhancements is growing rapidly Medical-Consumer Automotive-Entertainment Communication-Entertainment Infrastructure (Business Model) changes: Fabless Semiconductor Fabrication Redundant Elements EMS and ODM roles grow; R&D Challenges Quality, reliability, cost still paramount Form factor - Miniaturization and Thinner still important Product Personalization Counterfeit Products a growing issue Rare Earth and Conflict Materials are new concerns 15

Strategic Concerns Restructuring from vertically integrated OEMs to multi-firm supply chains Resulted in a disparity in R&D Needs vs. available resources Critical needs for R&D Middle part of the Supply Chain is least capable of providing resources Industry collaboration Variety of paths : University R&D centers, Industry consortia, ad-hoc cross-company R&D teams The mechanisms for cooperation throughout the supply chain must be strengthened. Cooperation and risk sharing among OEMs, ODMs, EMS firms and component suppliers is needed to focus on the right technology and to find a way to deploy it in a timely manner. 16

Packaging Roadmap

Primary Contributors CONTRIBUTORS W. R. Bottoms, 3MTS, Chair William Chen, ASE, Co-Chair Keith Newman, Sun Microsystems Bernd Appelt, ASE Henry Utsunomiya, Interconnection Technologies, Inc. Chuck Richardson, inemi Bob Pfahl, inemi Jie Xue, Cisco Rolf Aschenbrenner, Fraunhofer Institute IZM 18

State of the semiconductor packaging market Market for semiconductors has rebounded driven mainly by mobile computing. Increased focus on shrinking form factor and low power High level of integration (SoC, SiP) Use of 3D packaging and embedded components Majority of devices are packaged by assembly contractors Very competitive markets with low gross margin. Constrained ability to invest in the new technology required to meet emerging market requirements. Key Drivers in terms of markets Replacement of transportation with communication Internet of things Sensors and data everywhere Improvement of energy efficiency through use of electronics Hybrid and electric cars Environmental controls including smart thermostats, automatic lighting control, etc. Load shedding power controls for electronic systems based on real time use conditions. Improved energy efficiency for electric motors, appliances, consumer products Improved lighting efficiency through the use of LEDs Innovation in packaging will be one enabling factor in bringing these new technologies to market providing cost and performance advantages. 19

Paradigm Shifts Need for continuous introduction of complex multifunctional products to address converging markets favors modular components or SiP (2-D & 3-D): Increases flexibility - Shortens design cycle Cloud connected digital devices have the potential to enable major disruptions across the industry Rapid evolution and new challenges in energy consuming products such as SSL, Automotive and more Sensors everywhere MEMS and wireless traffic! More Moore (scaling of pitch) has reached its forecast limit and must transition to heterogeneous integration - More Than Moore. 20

Packaged Devices are getting more complex Scaling (More Moore) [Geometrical & Equivalent scaling] Moore s Law & More Functional More Diversification than Moore: Diversification (More than Moore) Analog/RF HV HVPower Passives Passives Power Sensors Actuators Biochips More Moore: Miniaturization Baseline CMOS: CPU, Memory, Logic 130nm 90nm 65nm 45nm 32nm 22nm.. V Information Processing Digital content System-on-chip (SoC) Interacting with people and environment Non-digital content System-in-package (SiP) Combining SoC and SiP: Higher Value Systems Beyond CMOS 21

0214.1/105bp Product/Package Type Volume (Bn Units) SiP/MCP FORECAST 2013 2018 Forecast Leading Suppliers/Players Stacked Die In Package and ASE, SPIL, Amkor, STATS ChipPAC, Samsung, 8 11 Memory Card Micron, SKHynix, Toshiba, SanDisk Stacked Package on Package Amkor, STATS ChipPAC, ASE, SPIL, Samsung, 0.8 1.3 Bottom Package Only Apple, Qualcomm, Sony, Panasonic PA Centric RF Module 4.3 6.3 RFMD, Skyworks, Anadigics, Renesas, TriQuint, Avago Connectivity Module (Bluetooth/WLAN) 0.4 0.5 Murata, Taiyo Yuden, ACSIP, ALPS Graphics/CPU or ASIC MCP 0.2 0.2 Intel, IBM, Fujitsu, Xlinx, Altera Leadframe Module NXP, STMicro, TI, Freescale, Toshiba, 3 5 (Power/Other) Infineon, Renesas, IR, ON Semi MEMS and Controller 5 8 ST, Analog, Bosch, Freescale, Knowles, SKHynix, InvenSense Denso TOTAL 21.7 32.3 Prismark Partners LLC 22 22

High Performance Packaging Technologies and Challenges

Potential Solution: 2.5D/3D Photonic Co-integrated SiP TSV memory stack, direct bonding interconnect, Large on-package memory cache Multiple voltage regulators to match power delivery to each component to the work in process Electronics, Photonics and Plasmonics on an SOI Substrate Photonic engine DRAM Flash memory DRAM Flash memory DRAM Flash memory DRAM Flash memory Memory controller DRAM CMOS logic DRAM Memory controller Silicon Substrate with TSV interconnects and Si Waveguides Power Controller Photonic/electronic Circuit Board PCB with electronic and photonic signals with embedded components 24

SiP Physical density Difficult Challenges by Package Type Thermal management Cross talk Noise isolation Power delivery Heterogeneous integration (compound semiconductors, photonics to the package, MEMS, etc.) Wafer level packaging 3D Heterogeneous integration Embedded components Alignment accuracy Large area packages and interposers Stress due to CTE mismatch Warpage 3D Integration Cost Power integrity (lower operating voltage) Thermal management Thin wafer and die handling Bandwidth 25

System in Package (SiP) Poses Many Difficult Challenges 26

Technologies Enabling 3D Integration Through Silicon Via active wafer & interposers Two side wafer level Processes RDL and MicroBumping Embedded Components (active & passive) Wafer thinning & Handling Wafer to Wafer Bonding Die to Wafer Bonding Micro bump assembly Design Tools Micro fluidics Cooling Assembly of TSV die Test of TSV Die Source: Phil Garrou, 2009

Difficult Challenges: Materials Materials Incorporation of ballistic conductors Improved thermal conductivity (die attach, underfill, encapsulant, interlayer dielectric, other) Pb free solder materials Low temp bonding (adhesives and other materials) Low cost, high density component substrates with low CTE Flexible component substrates compatible with wearable electronics 28

New Materials Will Be Required Many are in use today Cu interconnect Ultra Low k dielectrics High k dielectrics Organic semiconductors Green Materials Pb free Halogen free Many are in development Nanotubes Nano Wires Macromolecules Nano Particles Composite materials But improvements are needed 29

Carbon Conductors Look Better Than Cu Many questions still to be answered before graphene or CNT can be considered as practical interconnect materials. The results so far are very promising. 30

Major Gaps and Showstoppers Power requirements (Particularly package related) Thermal management for high thermal density Cost (lowest system cost may not be lowest package cost) Heterogeneous integration (Both device & material) Physical density of Bandwidth Latency There are many details associated with each of these issues and solutions will require new materials, new package architectures and new packaging processes. 31

Reducing power, ensuring reliability and power integrity at the point of use are major challenges. What are the potential solutions? 32

How Can We Reduce Power? Continue Moore s Law Scaling Reduce leakage currents (new transistor designs) Transistors are less than 10% of IC power today and going down Reduce on-chip Interconnect power by: Improved conductor conductivity Decrease capacitance Reduce interconnect length Reduce operating frequency Reduce operating voltage Voltage regulator per core Reduce high speed electrical signal length Move photons closer to the transistors (new material) (new material) (3D integration) (increased parallelism) (increased parallelism) (On-package photonics) 33

Thermal management is critical due to higher circuit density and lower operating temperature requirement. What are the potential solutions? 34

Potential Thermal Management Solutions Don t make heat in the first place Improved thermal conductivity through new materials Incorporation of microfluidics, heat pipes Segregation of high temperature components T. Brunschwiler et al., 3D-IC 2009 (IBM) 35

Thermal Management Materials Requirements Examples Thermal Interface Mat. Mold Compound Conductors Adhesives Underfill Adhesion Functional Properties Moisture Resistance Modulus Fracture Toughness CTE Highly coupled Material Properties Novel materials to achieve optimal performance for each parameter 36

Thermal Management Challenges for Packaging Finding solutions is not going to be easy High thermal dissipation density Hot spots Differential thermal expansion Heterogeneous integration Both circuit type and material The result is thermal limitations for: Bandwidth Power density Cost Reliability 37

Package Cost has not scaled with device cost and now poses a significant Gap that will become a showstopper without major innovation 38

Gaps with no Known Solution The most common reason for no known solution is cost not meeting market need Potential Solutions include: Increase parallelism in manufacturing Reduce the number of process steps 39

WLP, FOWLP and Panel Processing Increase Parallelism and Reduce Cost FOWLP Cost/die $0.5 $0.30 200mm WLP, Yield, test and productivity of FOWLP lines will rapidly increase FOWLP Production volume will increase dramatically with time Depreciation of the infrastructure with time New infrastructure will emerge for Panel manufacturing using 0ld LCD 300mm FOWLP display Processing $0.20 $0.10 Cost reduction! FOWLP already in production Panel Processing in development Panel Processing 470mmx370mm 2008 2010 2012 2014 2016 Source: Yole

Reduce Processing Steps to reduce Cost Remove package underfill New materials and lower processing temperature to reduce stress Reduce CTE differential Lower modulus materials with improved fracture toughness Improved interfacial adhesion Ziptronix DIB Cu nano-solder Ultra-conducting CU New ULK dielectrics Alchimer metal Reduce stress concentration by design Simulation 41

Summary

Packaging Gaps / Technology needs < 5 years Need lower cost multilayer interposers and integrated passives Address package warpage at elevated temperatures Develop high thermal conductive materials for high thermal density devices Handling of thinned wafer and die Develop equipment for wafer level packaging, fan out, 3D etc. Address equipment requirements to support assembly of complex SiPs with MEMS, 43 43

Packaging Gaps/ Technology needs > 5 years Improved design systems enable electrical, mechanical and thermal co-design and simulation tools that can be used to predict the reliability of packages/systems with high level of confidence Further packaging technologies will incorporate a wide range of materials and equipment that are not available today. 44 44

Invitation to get involved Participate through email and webex meetings over the next 3 months to update and review the 2015 roadmap chapter. 45 45

www.inemi.org Email contacts: Grace O Malley gomalley@inemi.org Steve Payne- Europe Steve.payne@inemi.org Haley Fu - Asia haley.fu@inemi.org