INSTITUTE OF AERONAUTICAL ENGINEERING Dundigal, Hyderabad - 500 043

INSTITUTE OF AERONAUTICAL ENGINEERING Dundigal, Hyderabad - 500 043 ELECTRONICS AND COMMUNICATION ENGINEERING Course Title VLSI DESIGN Course Code 57035 Regulation R09 COURSE DESCRIPTION Course Structure Lectures Tutorials Practicals Credits Course Coordinator Team of Instructors 4 1-4 Mr. V. R. Sheshagiri Rao, Professor Mr. B. Kiran Kumar, Assistant Professor I. COURSE OVERVIEW: VLSI design course gives the knowledge about the fabrication of NMOS, PMOS, CMOS and their application in the present electronics world. The present course gives knowledge about different processes used for fabrication of an IC. The electrical properties of MOS transistor and analysis of CMOS, BiCMOS inverters is carried out. This course gives detail study on design rules, stick diagrams, logic gates, types of delays, fan-in, fan-out which effects the action of a MOS. It also gives information on data path subsystem and array subsystems, and several PLD s like PLA, PAL, CPLD and FPGA s. We also came to know about the CMOS testing principles both at system level and chip level. II. PREREQUISITES: Level Credits Periods / Week Prerequisites UG 4 4 Electronic Devices and circuits,switching Theory and Logic Design III. COURSE ASSESSMENT METHODS: Sessional Marks There shall be 2 midterm examinations. Each midterm examination consists of subjective test and objective test. The subjective test is for 10 marks, with duration of 1 hour. Subjective test of each subject shall contain 4 questions; the student has to answer any 2 questions, each carrying 5 marks. The objective test is for 10 marks, with duration of 20 min. University End Exam Marks Total Marks 75 100 First midterm examination shall be conducted for the first four units of syllabus and second midterm examination shall be conducted for the remaining portion. Five marks are marked for assignments. There shall be two assignments in every theory course. First assignment marks will be allotted to 1 st mid for first four units and second assignment marks will be allotted to 2 nd mid for next four units. So each mid exam is conducted for 25 marks 1 P a g e

IV. EVALUATION SCHEME: S. No Component Duration Marks 1 I Mid Examination 60 minutes 20 2 I Assignment - 05 3 II Mid Examination 60 minutes 20 4 II Assignment - 05 5 External Examination 180 minutes 75 V. COURSE OBJECTIVES: I. Give exposure to different steps involved in fabrication of ICs using MOS/BiCMOS/CMOS transistors. II. Explain electrical properties of MOS and BiCMOS devices to analyse the behaviour of inverters designed with various load. III. Give exposure to the design rules to be followed to draw the layout of any logic circuits. IV. Provide concept to different logic gates using CMOS inverter and analyse their characteristics. V. Provide design concepts to design building blocks of data path of any system using gates. VI. Understand basic PLDs and testing of CMOS circuits. VI. COURSE OUTCOMES: 1. Discuss about the fabrication process of ICs by different Metal Oxide Semiconductor (MOS) technologies. 2. Explain the various electricalproperties of MOS transistors 3. Choose an appropriate inverter depending on specifications required for a circuit. 4. Design the stick diagrams and layout of any logic circuits 5. Illustrate the different design rules 6. Explain different switch logic and alternate gate circuits 7. Design of various subsystems like shifters, adders, comparators, multipliers detectors and counters 8. Design simple array of memories using MOS transistors and can understand design of large memories 9. Design simple semiconductor integrated circuits like PLA, PAL, FPGA and CPLD and to construct various logic circuits using them 10. Explain different types of faults that can occur in a system and learn the concepts of testing and adding extra hardware to improve testability of system VII. HOW PROGRAM OUTCOMES ARE ASSESSED: 2 P a g e Program Outcomes Level Proficiency assessed by 1 An ability to apply knowledge of basic sciences, mathematical S Assignments skills, engineering and technology to solve complex electronics and communication engineering problems 2 An ability to identify, formulate and analyze engineering S -- problems using knowledge of Basic Mathematics and Engineering Sciences 3 An ability to provide solution and to design Electronics and H Practice

4 5 6 7 8 9 10 11 12 Communication Systems as per social needs An ability to investigate the problems in Electronics and Communication field and develop suitable solutions (Engineering Problem solving skills) An ability to use latest hardware and software tools to solve complex engineering problems (Practical engineering analysis skills) An ability to apply knowledge of contemporary issues like health, Safety and legal which influences engineering design (social awareness) An ability to have awareness on society and environment for sustainable solutions to Electronics and Communication Engineering problems (Creative Skills) An ability to demonstrate understanding of professional and ethical responsibilities (Professional Integrity) An ability to work efficiently as an individual and in multidisciplinary teams (Team work) An ability to communicate effectively and efficiently both in verbal and written form (Communication Skills) An ability to develop confidence to pursue higher education and H for life-long learning (continuing education awareness) An ability to design, implement and manage the electronic H projects for real world applications with optimum financial resources (Software & Hardware Interface) N = None S = Supportive H = Highly Related S Sessions Design Exercises H Design Exercises Seminars, Paper Presentations N -- N -- N -- H S Projects Document Preparation and Presentation Seminars Discussions Development of Prototype, Mini Projects VIII. HOW PROGRAM OUTCOMES ARE ASSESSED: PROGRAM SPECIFIC OUTCOMES LEVEL PROFICIENCY ASSESSED BY PSO 1 Professional Skills: An ability to understand the basic concepts in Electronics & Communication H Lectures and Assignments Engineering and to apply them to various areas, like Electronics, Communications, Signal processing, VLSI, Embedded systems etc., in the design and implementation of complex systems. PSO 2 Problem-solving skills: An ability to solve complex S Tutorials Electronics and communication Engineering problems, using latest hardware and software tools, along with analytical skills to arrive cost effective PSO 3 and appropriate solutions. Successful career and Entrepreneurship: An understanding of social-awareness & environmentalwisdom along with ethical responsibility to have a successful career and to sustain passion and zeal for real-world applications using optimal resources as an Entrepreneur. S Seminars and Projects 3 P a g e

IX. SYLLABUS: UNIT I INTRODUCTION Introduction to IC technology-mos, PMOS, NMOS, CMOS and BiCMOS Technologies: Oxidation, Lithography, Diffusion, Ion implantation, Metallization, Encapsulation, Probe testing, Integrated Resistors and Capacitors. UNIT II BASIC ELECTRICAL PROPERTIES Basic electrical properties of MOS and BiCMOS circuits: I ds-v ds relationships, MOS transistor threshold voltage, g m, g ds, figure of merit w o, pass transistor, NMOS inverter, Various pull-ups, CMOS inverter analysis and design, BiCMOS inverters. UNIT III VLSI CIRCUIT DESIGN PROCESSES VLSI design flow, MOS layers, Stick diagrams, Design Rules and Layout, 2 um CMOS design rules for wires, Contacts and Transistors, Layout diagrams for NMOS and CMOS inverters and gates, Scaling of MOS circuits UNIT IV GATE LEVEL DESIGN Logic gates and other complex gates, Switch logic, Alternate gate circuits, Time delays, Driving large capacitive loads, Wiring capacitances, Fan-in and fan-out, Choice of layers. UNIT V DATA PATH SUB SYSTEMS Sub system design, Shifters, Adders, ALUs, Multipliers, Parity generators, Comparators, Zero/One detectors, Counters. UNIT VI ARRAY SUBSYSTEMS SRAM, DRAM, ROM, Serial Access Memories, Content Addressable Memory UNIT VII SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN PLAs, FPGAs, CPLDs, Standard cells, Programmable Array Logic, Design Approach, Parameters influencing low power design. UNIT VIII CMOS TESTING CMOS Testing, Need for testing, Test principles, Design strategies for test, Chip level test techniques, System-level test techniques, Layout design for improved testability. Text Books: 1. Essentials of VLSI circuits and systems Kamran Eshraghian, Eshraghian Dougles and A. Pucknell, PHI, 2005 Edition. 2. VLSI DESIGN - K. Lal Kishore, V.S.V Prabhakar, I.K International, 2009. 3. CMOS VLSI Design- Neil H.E Weste, David Harris, Ayan Banerjee, Pearson Education, 1999. References: 1. CMOS logic circuit design- John P. Uyemura, Springer, 2007. 2. Modern VLSI Design Wayne Wolf, Pearson Education, 3 rd Edition, 1997. 3. Introduction to VLSI-Mead and convey, BS publications, 2010 4. Application Specific Integrated Circuits-smith 4 P a g e

X. COURSE PLAN: At the end of the course, the students are able to achieve the following course learning outcomes (CLO): Lecture UNI Course learning outcomes Topics to be covered Book No. T 1 I Discuss and memorize the IC Introduction to IC generations, importance of VLSI To know fabrication of PMOS Technology MOS, PMOS 2-3 Describe fabrication of NMOS NMOS technology 4-5 Describe fabrication of CMOS CMOS technologies 6-7 Describe fabrication of Bi CMOS Bi CMOS technologies 8 Outline ion implantation, diffusion, Diffusion, Ion implantation, oxidation, lithography Metallization 9 Describe encapsulation, probe testing, Encapsulation, Probe Integrated Resistors, capacitors testing, Integrated Resistors 10-11 II Identifythe threshold voltage concept Basic Electrical Properties and Basic Electrical Properties of MOS and Bi-CMOS Circuits 12-13 Depending on V GS I ds-v ds relations I ds-v ds relationships, MOS are derived transistor threshold Voltage 14 Illustrateabout the pass transistor,w o gm, gds, figure of merit w o, Pass transistor 15 Illustratevarious pull up Various pull-ups, 16-17 Identifywhy we are preferring CMOS technology CMOS Inverter analysis and design, Bi-CMOS Inverters 18 III Describe the design flow Design Flow, MOS Layers 19-20 Discussstickdiagram representation and illustrate the concept of stick diagram representation. Stick Diagrams, Design Rules and Layout 21-22 Examine the concept of layout and study required rules. 23-24 Discuss the construction of study layout rules for different processes and to learn how to draw layouts. 25 Discuss and memorize the scaling and effects of scaling. Identify the limitations of scaling 26-27 IV Analyse gate design by CMOS and nmos logic. 28-30 Illustrate gate design and distinguish between CMOS and nmos logic. 31-32 Discuss driving large Capacitive Loads, Wiring Capacitances 33 Describe about Fan-in and fan-out, Choice of layers 2 um CMOS Design rules for wires, Contacts and Transistors Layout Diagrams for NMOS and CMOS Inverters and Gates Scaling of MOS circuits Logic Gates and Other complex gates, Switch logic Alternate gate circuits, Time Delays Driving large Capacitive Loads, Wiring Capacitances Fan-in and fan-out, Choice of layers 34-36 V Design Shifters, Adders Subsystem Design, Shifters, T3 Adders 37-38 Design ALUs, Multipliers, Parity ALUs, Multipliers, Parity T3 generators generators 39-41 Design Comparators, Zero/One Comparators, Zero/One T3 Detectors, Counters Detectors, Counters 42-44 VI Design memories SRAM, DRAM, SRAM, DRAM, ROM T3 ROM 45-48 Design of serial access memories, Serial access memories, T3 content addressable memory content addressable memory 49-52 VII Design of PLAs, FPGAs, CPLDs PLAs, FPGAs, CPLDs R4 5 P a g e

53 Mention advantages of Programmable Array Logic Standard Cells, Programmable Array Logic 54-55 VIII Illustrate parameters influencing low Design Approach, power design parameters influencing low power design 56-57 Demonstrate the need for testing. CMOS Testing, Need for testing, Test Principles 58-60 To illustrate the different test Design Strategies for test, techniques To acquaint with the chip Chip level Test Techniques level testing techniques. 61-63 To Discuss with the system level testing techniques. System-level Test Techniques, Layout Design for improved Testability R4 R4 T3 T3 T3 XI. MAPPING COURSE OBJECTIVES LEADING TO THE ACHIEVEMENT OF PROGRAM OUTCOMES: Course Objectives Program Outcomes Program Specific Outcomes PSO1 PSO2 PSO3 1 2 3 4 5 6 7 8 9 10 11 12 1 S H H S S H 2 H S H S 3 S H S H S S S S 4 H S H S 5 S S S S H S S 6 S H S S XII. S= Supportive H = Highly Related MAPPING COURSE OUTCOMES LEADING TO ACHIEVEMENT OF PROGRAM OUTCOMES: Course Outcomes Program Outcomes 1 2 3 3 5 6 7 8 9 10 11 12 13 1 H S S H S H 2 S S H H 3 H S S H S 4 S S H S S 5 S S H S H Program Specific Outcomes PS PS O1 O2 6 S S H H 7 H S S S S 8 S H H S 9 S S 10 H S H S S S= Supportive H = Highly Related Prepared by: Mr. B. Kiran Kumar, Assistant Professor HOD, ECE PS O3 6 P a g e