AMD/ATI 215-0754009-00 RV840 Juniper GPU (from Radeon TM HD 5750 Graphics Card) Circuit Analysis of GDDR5 I/O Drivers, Receivers, DLL, and PLL Table of Contents 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel: 613.829.0414 Fax: 613.829.0515 www.chipworks.com
Overview Introduction Brief Design Overview Component Descriptions Device Summary Figures To view, please click on the appropriate bookmark in the panel on the left. 0.1.1 Package Markings 0.1.2 Package X-Ray 0.1.3 Die Markings 0.2.1 Die Photograph 0.2.2 Die Architecture 0.2.3 Die Architecture (High Magnification) Schematics 1.0.0 Top Level Diagram 2.0.0 TX Output Drivers 2.1.0 Output Buffer with Impedance Control 2.1.1 Unused 1 2.1.1.1 PULLDN_X4 2.1.2 TX Data Delay Latches 2.1.2.1 DELAY_D6_3 2.1.3 Latched Data Buffers 2.1.4 Buffer 2.1.5 Buffer 2.1.6 Clock Generator 2.1.6.2 INV22F_2 2.1.6.3 Clock Generator 2.1.6.3.1 TRIGATE 2.1.6.3.2 Clock Controller 2.1.6.3.3 Decoder 2.1.7 TX Data Buffers 2.1.8 Logic Controller 2.1.8.1 DELAY_D10 2.1.9 Output Buffers with Impedance Control 2.1.9.1 Counter
2.1.9.2 Counter 2.1.9.3 Impedance Controller 2.1.9.3.1 OR52F_1 2.1.9.3.2 BUF2F_1 2.1.9.3.3 UNUSED 2.1.9.3.4 Level Shifters 2.1.9.3.4.1 DIFBUF_2 2.1.9.4 Flip-Flop 2.1.9.5 Latch 2.1.9.6 Output Buffer Circuit 2.1.9.6.1 Output Buffer Cell 2.1.9.6.1.1 RT_2 2.1.9.6.1.1.1 NAND2F_X16 2.1.9.6.1.1.2 NAND2F_X8 2.1.9.6.1.1.3 NAND2F_X4 2.1.9.6.1.1.4 NAND2F_X2 2.1.9.6.1.1.5 NAND2F_X1 2.1.9.6.1.1.6 AND2B1F_X16 2.1.9.6.1.1.7 AND2B1F_X8 2.1.9.6.1.1.8 AND2B1F_X4 2.1.9.6.1.1.9 AND2B1F_X2 2.1.9.6.1.1.10 AND2B1F_X1 2.1.9.6.1.2 High Side Pre-Buffer 2.1.9.6.1.3 Low Side Pre-Buffer 2.1.9.6.1.4 Delay Circuit 2.1.9.6.2 PULLDN_X5 2.1.9.6.3 PULLUP_X5 2.1.9.6.4 Output Buffer Cell 2.1.9.6.4.1 Programmable Output Buffer 2.1.9.7 Parallel-Serial Converter 2.1.9.7.1 XOR 2.1.9.7.2 MUX 2.1.9.8 ESD 2.1.9.9 Impedance Clock Controller 2.1.10 TX Data Path 2.1.10.1 BUF_1 2.1.10.2 8 Bit Latched Data 2.1.10.2.1 DELAY_D8_1 2.1.10.2.2 DELAY_D8_4 2.1.10.3 8 Bit Latched Data
2.1.10.3.1 DELAY_D8_2 2.1.10.3.2 DELAY_D6_2 2.1.10.4 8 Bit Latched Data 2.1.10.4.1 DELAY_D8 2.1.10.4.2 DELAY_D8_3 2.1.10.5 Latched Data 2.1.10.5.1 DELAY_D6 2.1.10.5.2 DELAY_D6_1 2.1.10.6 8 Bit Data Selector Logic 2.1.10.6.1 AOI22_2 2.1.10.6.2 AO22_1 2.1.10.7 8 Bit Data Selector Logic 2.1.10.7.1 AOI22_1 2.1.10.7.2 AO22_2 2.1.11 TX Latch Clock Control 2.1.11.1 Buffers 2.1.11.2 DELAY_D11 2.1.12 Test Circuitry 2.1.12.1 Test Circuitry 2.1.12.1.1 DIFINV_1 2.2.0 Output Buffer with Impedance Control 2.2.2 Latched Data Buffers 2.2.3 TX Data Delay Latches 2.2.3.1 Delay Latches (x8) 2.2.3.2 Delay Latches (x8) 2.2.3.3 Delay Latches (x7) 2.2.3.4 Delay Latches (x6) 2.2.3.5 Delay Latches (x8) 2.2.3.6 Delay Latches (x4) 2.2.3.7 Delay Latches 2.2.4 Logic Controller 2.2.5 TX Data Buffers 2.2.6 TX Data Path 2.2.6.1 Data Selector Logic 2.2.6.2 Data Selector Logic 2.2.6.3 Bit Data Selector 2.2.6.3.1 AOI22_3 2.2.6.3.2 AOI22_4 2.2.6.3.3 AOI22_5 2.2.6.4 Bit Data Selector
2.2.6.4.1 AOI22_2S1 2.2.6.4.2 AOI22_6 2.2.6.5 Bit Latched Data 2.2.7 Output Buffer with Impedance Control 2.2.7.1 Impedance Clock Controller 2.2.8 OR Gates 2.2.8.1 OR2F_1 2.2.8.2 OR2F_1S1 2.2.8.3 OR2F_1S2 2.2.9 TX Delay Latch Clock Control 2.3.0 TX Output Logic Controller 2.4.0 Clock Buffer 2.5.0 Buffers Circuit 3.0.0 Receiver 3.1.0 Bias Generator 1 3.1.1 Folded Cascode Amplifier 3.1.2 Folded Cascode Amplifier Bias Generator 3.1.3 Current Mirror 3.2.0 Bias Generator 1S1 3.2.1 DIFBUF_1 3.3.0 Reference Selector 3.3.1 Level Shifter x8 3.3.2 Programmable Current Control 2 3.3.3 Bias Generator 3.3.3.1 Differential Amplifier 3.3.3.2 Series Transistors 3.3.4 Programmable Current Mirror 3.3.4.1 Programmable Current Mirror Leg 3.3.4.1.1 TRIGATE_3 3.3.4.2 Programmable Current Mirror Leg 2 3.3.4.2.1 NCASC_X2 3.3.4.3 Programmable Current Mirror Leg 3 3.3.5 TRIGATE_13 3.3.6 Programmable Current Mirror 2 3.3.6.1 CASC_SWITCH_3 3.3.7 Programmable Current Control 1 3.3.7.1 Level Shifter x6 3.4.0 8 Bit Buffer 3.5.0 Input Data Interface
3.5.1 Data Test Circuitry 3.5.1.1 Test Interface 3.5.1.1.1 RS 3.5.1.1.2 NAND2D2 3.5.1.2 Test Signal Generator 1-to-4 3.5.1.3 Test Signal Generator 1-to-4 3.5.1.4 Clock Selector 3.5.1.4.1 4 Bit Counter 3.5.1.4.1.1 MX21 3.5.1.4.1.2 MX21B1_1 3.5.1.4.1.3 MX21_1 3.5.1.4.2 Frequency Selector 3.5.1.4.3 1 Bit Counter 3.5.1.5 Scan Chain Interface 3.5.1.5.1 4 Bit Decoder 3.5.1.5.1.1 1-to-4 Decoder 3.5.1.5.2 Clock Selector 3.5.1.5.3 Scan Chain x16 3.5.1.5.3.1 Scan Chain Cell 3.5.1.5.4 Inverter x16 3.5.1.6 MUX 2-to-1 3.5.2 Input Data Buffer 3.5.2.1 Comparator 2 3.5.2.1.1 BUF_2 3.5.2.2 Comparator 3 3.5.2.2.1 TRIGATE_6 3.5.2.2.2 INV_1 3.5.2.3 Comparator 4 3.5.2.4 Amplifier 10 3.5.2.4.1 TRIGATE_7 3.5.2.4.2 TRIGATE_8 3.5.2.4.3 TRIGATE_9 3.5.2.4.4 TRIGATE_10 3.5.2.4.5 TRIGATE_11 3.5.2.5 Amplifier 11 3.5.2.6 Data Path Switch 3.5.2.6.1 TRIGATE_5 3.5.2.7 Comparator 5 3.5.2.7.1 TRIGATE_12 3.5.2.7.2 INV_2
3.5.2.7.3 BUF2_3 3.5.2.8 Level Shifter 3.5.2.9 Clock Generator 2 3.5.2.10 Level_Shifter_1 3.5.2.11 Latch 1 3.5.2.12 FF1 3.5.2.13 Edge Trigger FF 3.5.2.14 Latch 3 3.5.2.15 Latch 4 3.5.2.16 Latch 5 3.5.2.17 Delay 3.5.3 Test Code Detector 3.5.3.1 AOI222 3.5.3.2 Data Detector 3.5.3.2.1 OA21 3.5.3.2.2 Data Buffer 1 3.5.3.2.3 Data Buffer 2 3.5.3.2.4 AO22 3.5.3.2.5 AO22_3 3.5.3.2.6 AO22_4 3.5.3.2.7 AO22_5 3.5.3.2.8 COUNT_1B 3.5.3.2.8.1 OR2 3.5.3.2.9 XNOR2 3.5.4 3 Bit Decoder 1 3.5.5 Control 11 3.5.6 3 Bit Decoder 2 3.5.7 30-to-8 Bit Data Encoder 3.5.7.1 MUX 8 3.5.7.2 MUX 8S1 3.5.7.3 MUX 8S2 3.5.7.4 MUX 8S4 3.5.7.5 MUX 8S5 3.5.7.6 MUX 8S6 3.5.7.7 MUX 8S7 3.5.7.8 MUX 8S8
4.0.0 DLL 4.1.0 DLL Decoder 4.1.1 Pull-Up_x6 4.2.0 Clock Latch 4.3.0 Phase Detector 4.3.1 LANF 4.4.0 Charge Pump 4.4.1 Amplifier 4.4.1.1 BUF2_1 4.4.2 Bias Circuit 4.4.2.1 TRIGATE_2 4.4.2.2 BUF2 4.4.3 Charge Circuit 4.4.3.1 Charge Cell 4.4.3.1.1 TRIGATE_1 4.5.0 Programmable Delay 1 4.5.1 Cap 4.5.1.1 TRIGATEF 4.5.1.2 TRIGATEF_1 4.5.1.3 TRIGATEF_2 4.5.2 Delay Cell 2 4.5.2.1 Current 3 4.5.2.2 Current 4 4.5.3 Delay Cell 1 4.5.3.1 Current 2 4.5.3.2 Current 1 4.5.4 Buffer 3 4.5.5 Buffer 2 4.5.6 Buffer 1 4.6.0 Clock Select 4.6.1 Decoder 4.7.0 NOR2B1 4.8.0 Pull-Down X60 4.9.0 Pull-Up X60 4.10.0 Data Buffers 4.10.1 BUF2F 4.10.1.1 INVX8 4.10.1.2 INVX6 4.10.2 BUF2F_2 4.10.2.1 INVX5
4.10.3 BUF2F_3 4.10.4 BUF2_2 4.12.0 Delay Circuit 4.12.1 Programmable Delay 2 5.0.0 PLL 5.1.0 Clock Output 5.1.1 Frequency Divedor 5.1.2 Decoder 5.1.3 Frequency Selection 5.1.3.1 INVX2 5.1.4 DFS_LAT 5.2.0 PLL Core 5.2.1 Clock Buffer 1 5.2.2 Clock Buffer 2 5.2.3 Amplifier 5 5.2.4 Voltage Generator 5.2.5 Voltage Generator S1 5.2.6 Voltage Detector 5.2.7 Frequency CK Feed MUX 5.2.8 Power-Down Control 5.2.9 Clock Multiplexer 1 5.2.9.1 Divide-by-M Counter 5.2.9.1.1 DFSF 5.2.9.1.2 DFSF_1 5.2.10 Phase Frequency Detector 5.2.10.1 TRINOT14 5.2.10.2 NAND2F 5.2.10.3 Comparator 7 5.2.10.4 Comparator 7S1 5.2.11 Divide-by-N Counter 5.2.11.1 Pull-Down x6 5.2.11.2 LAN 5.2.12 Voltage Generator 1 5.2.12.1 TRIGATE_4 5.2.12.2 Amplifier 7 5.2.12.2.1 FCAP_x3 5.2.12.2.2 DIFINV_2 5.2.13 Charge Pump 2 5.2.13.1 Charge Switch x8
5.2.13.1.1 Charge Switch x2 5.2.13.1.2 CHARGE_SWITCH3 5.2.13.2 Amplifier 8 5.2.13.3 Amplifier 9 5.2.13.4 Control 1 5.2.13.5 Bias Generator 2 5.2.13.6 BUF2_4 5.2.13.7 Charge Switch x28 5.2.13.7.1 Charge Switch x14 5.2.13.7.1.1 Charge Switch x1 5.2.13.7.2 Control 5.2.13.7.2.1 OR2_1 5.2.14 VCO 5.2.14.1 VCO_UNUSED 5.2.14.2 Adjust Delay Cell 5.2.14.2.1 VS_INV_1 5.2.14.2.2 VS_INV_2 5.2.14.2.3 VS_TRINOT23_X2 5.2.14.2.3.1 VS_TRINOT23_1 5.4.0 Power-Up 5.4.1 Power-Up 1 5.4.2 Power-Up 2 5.5.0 PLL Control 5.5.1 PLL Control 1 5.5.1.1 10 Bit Counter 5.5.1.2 NAND9 5.5.2 PLL Control 2 5.5.2.1 Pull-Up x10 5.5.2.2 Comparator 5.5.3 PLL Control 3 5.5.3.1 Delay Circuit 5.5.3.2 Buffers x10 5.5.3.3 Buffers x11 5.5.3.4 Adder 5.5.3.4.1 7 Bit Counter 5.5.3.4.1.1 OA222 5.5.3.4.2 Data Path 5.5.3.4.3 Data Path 1 5.5.3.4.4 Data Path 2 5.5.3.4.5 Adder 1
5.5.3.4.5.1 8 Bit Counter 2 5.5.3.4.5.1.1 OA22 5.5.3.4.5.1.2 AND4 5.5.3.4.5.2 6 Bit Counter 5.5.3.4.5.3 8 Bit Counter 1 5.5.3.4.5.4 4 Bit Counter 5.5.3.4.5.5 XOR2 X26 5.5.3.4.5.5.1 XOR2 5.5.3.4.5.5.2 XOR2_3 5.5.3.4.6 Decoder 5.5.3.5 Adder Control 5.5.3.5.1 11 Bit Counter 5.5.3.5.1.1 NOR Gate 5.5.3.5.1.2 5 Bit Counter 5.5.3.5.1.2.1 Half Adder 5.5.3.5.1.2.2 Half Adder 1 5.5.3.5.1.3 4 Bit Counter 5.5.3.5.1.4 2 Bit Counter 5.5.3.5.2 REG Cell 5.5.3.5.3 Clock Input 6.0.0 Clock Related Circuits 6.1.0 Bias Generator 6.1.1 PCASC_UNUSED 6.1.3 Amplifier 6.2.0 Clock Buffers 6.2.1 CLK_BUF 6.2.2 BUF_3 6.2.3 CLK_BUFS1 6.2.4 CLK_BUFS2 6.2.5 CLK_BUFS4 7.0.0 TRX Clocks 7.1.0 RX Clocks 7.1.1 CLK_MUX_3 7.1.1.1 MX21B12_1 7.1.1.2 MX21B12 7.1.1.3 MX31 7.1.2 ADJ_MX21 7.1.2.1 MX21B12_2
7.1.2.2 MX21B12_3 7.1.2.3 MX21B12_4 7.1.2.4 MX21B12_5 7.1.2.5 MX21B12_6 7.1.2.6 MX21B12_7 7.1.2.7 MX21B12_8 7.1.3 ADJ_TRINOT 7.1.4 ADJ_MX41 7.1.5 ADJ_1 7.1.5.1 XOR2 7.1.5.2 XNOR2_2 7.1.5.3 AND2 7.1.6 ADJ_2 7.1.6.1 AND22 7.2.0 TX Clocks 7.2.1 DELAY_LINES2 7.2.1.2 CLK_MUX 7.2.2 ADJ_3 7.3.0 Clock Control 7.3.1 Decoder 7.3.2 REG_6B 7.3.2.1 S_XNOR2_2P5_2D4 7.3.2.2 S_XNOR2_1_2D2 7.3.2.3 BUF5 7.3.3 Bit Counter 1 7.3.4 Bit Counter 2 7.3.5 CTRL_10 7.3.6 DC_4B 7.3.7 CTRL13 7.3.8 Bit REG 1 7.3.8.1 S_XNOR2_2P5_2D2 7.3.8.2 S_XNOR2_2P5_2P5 7.3.8.3 S_XOR2F_2_2D2 7.3.8.4 S_XOR2F_E3_E2P5 7.3.8.5 S_XOR2F_2P5_1P5 7.3.8.6 S_XNOR2F_2P5_2P5 7.3.9 BUF 6 7.3.10 LOGIC 1 7.3.11 MUX10_DFN 7.3.12 MUX10_DFNS1
7.3.13 DATADET3BS1 7.3.14 CTRL13S1 7.3.15 DATADET3B 7.3.16 DFN_6B 7.3.17 MUX2_6BS5 7.3.18 MUX2_6BS6 7.3.19 REGS 7.3.20 MUX2_6BS7 8.0.0 Miscellaneous Buffers 8.1.0 Buffers 8.1.1 INV_D48 8.2.0 Level Shifter 8.3.0 Miscellaneous Components 8.3.2 Unused 10 8.3.3 Unused 9 8.3.4 Inverters X13 8.3.5 Pull-Up 8.3.6 Unused 13 8.3.7 MOS Capacitors 8.4.0 Impedance Control Circuit 8.4.3 DC38F_2 8.4.4 LAN_X7 8.4.5 LANF_X5 8.4.6 BUF_X6 8.4.7 INV_X7_1 8.4.8 INV_X5 8.4.9 UNUSED_DIFX10 8.4.10 BUF_X12 8.4.11 BUF_X28 8.4.12 BUF_X5 8.4.13 INV_X14 8.4.14 BUF_X3 8.4.15 BUF_X3_1 8.4.16 BUF_X5_1 8.4.17 BUF_X12_1 8.4.18 BUF_X4 8.4.19 MUX 2-to-1 Channel Selector 8.4.20 UNUSED_14 8.4.21 INV_X14_2
8.4.22 INV_X14_3 8.4.23 UNUSED_11 8.4.24 BUF_X3_2 8.4.25 UNUSED_8 8.4.26 INV_X11 8.4.27 INV_X14_1 9.0.0 Bypass Capacitors and ESD Protection 9.1.0 RC Triggered Active MOSFET ESD Clamp Cell Library Signal Cross-Reference List About Chipworks
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