Optimization and Comparison of -Stage, -i/p NND Gate, -i/p NOR Gate Driving Standard Load By Using Logical Effort Satyajit nand *, and P.K.Ghosh ** * Mody Institute of Technology & Science/ECE, Lakshmangarh, India bstract- pplication of logical effort on transistor-level analysis of -stage inverter, -i/p stage NND and -i/p stage NOR gate is presented. Logical effort method is used to estimate delay and to evaluate the validity of the results obtained by using logical effort. The tested gate topologies were -stage inverter, -i/p- stage NND gate and, -i/p stage NOR gate. The quality of the obtained estimates is validated by circuit simulation using T-SPICE for.8v, 80nm technologies. Index Terms: NND, NOR, Gate, logical path optimization, logical effort. I. Introduction CMOS logic gates are basic building blocks for gate circuits. The delay through these gates is related to their sizes and their during loads. Logical effort is a technique, which gives insight about proper sizing of CMOS logic gates to have the minimum achievable delay. Three architectures for -stage inverter, -i/p- stage NND gate, and -i/p stage NOR gate are sized using logical effort to get the minimum possible delay simulated. The paper is organized as follows. Section II describes the theory of logical effort and the expression for delays. nalytical results are shown in section III. Simulate results are shown in section IV Finally, conclusion is given in section V. II.Logical Effort The method of logical effort is founded on a simple model of the delay through a single MOS logic gate. The model describes delays caused by the capacitive load that the logic gate drives and by the topology of the logic gate. Clearly, as the load increases, the delay increases, but delay also depends on the logic function of the gate. s, the simplest logic gates, drive loads best and are often used as amplifiers to drive large capacitances. Logic gates that compute other functions require more transistors, some of which are connected in series, making them poorer than inverters at driving current. Thus a NND gate must have more delay than an inverter with similar transistor sizes that drives the same load. The method of logical effort (LE) quantifies these effects to simplify delay analysis for individual logic gates and multi-stage logic networks. The first step in modeling delays is to isolate the effects of a particular integrated circuit fabrication process by expressing all delays in terms of a basic delay unit τ, thus we express absolute delay d abs as the product of a unitless delay of the gate, and the delay unit that characterizes a given process []: d abs =dτ () Unless otherwise indicated, we will measure all times in units of τ which is about 50 ps in a typical process. The delay incurred by a logic gate is comprised of two components, a fixed part called the parasitic delay, p and a part that is proportional to the load on the gate s output, called the effort delay or stage effort, f. The total delay, measured in units of τ, is the sum of the effort and parasitic delays.thus d= f+p () The effort delay depends on the load and on properties of the logic gate driving the load. We introduce two related terms for these effects: the logical effort g, captures properties of the logic gate, while the electrical effort h, characterizes the load. The effort delay of the logic gate is the product of these two factors. f=gh () The logical effort captures the effect of the logic gate s topology on its ability to produce output current. It is independent of the size of the transistors in the circuit. The electrical effort describes how the electrical environment of the logic gate affects performance and how the size of the transistors in the gate determines its load-driving capability. The electrical effort is defined by h = C out / () where C out is the capacitance that loads the logic gate and c in is the capacitance presented by the logic gate at one of its input terminals. Many CMOS designers also call electrical effort as fanout. Combining Equations and, we obtain the basic equation that models the delay through a single logic gate, in time scale is d = gh+ p (5) This equation shows that logical effort g and electrical effort h both contribute to delay in the same way. This formulation separates g, h, p and τ the four contributions to delay. The process parameter τ represents the speed of the basic transistors. The parasitic delay p expresses the intrinsic delay of the gate due to its own internal capacitance, which is largely independent of the size of the transistors in the logic gate. The electrical effort h combines the effects of external load, which establishes
C out with the sizes of the transistors in the logic gate, which establish of parasitic delay of various logic gate types assuming simple layout styles. typical value of p inv the parasitic delay of an inverter is.0 shown in Table. The logical effort, g expresses the effects of circuit topology on the delay free of considerations of loading or transistor size. Logical effort is useful because it depends only on circuit topology. Logical effort values for a few CMOS logic gates are shown in Table. Logical effort is defined so that an inverter has a logical effort of one. This unitless form means that all delays are measured relative to the delay of a simple inverter. n inverter driving an exact copy of it experiences an electrical effort of one. Because the logical effort of an inverter is defined to be one, an inverter driving an exact copy of it will therefore have an effort delay of one. Fig. shows the architectures of, NND and NOR gates. Table : Estimates of parasitic delay of various logic gate types assuming simple layout styles. typical value of p inv the parasitic delay of an inverter is.0. Gate type NND NOR XOR, XNOR 6 Number of inputs 8 n p inv np inv np inv np inv = g = / B = g = / (a) (b) (c) B = 5 g = 5/ i) For -stage inverter Given: N =, C out = 00f III NLTICL RESULTS To find least delay (D) = N [F /N + P in ] = [00 / +] =6.69sec For τ = ps in 80 nm process Fig.. Simple gates architecture for (a) (b) two i/p Nand gate and (c) two i/p Nor gate Table.Logical effort of static CMOS gates. (γ =,where γ is the ratio between PMOS and NMOS transistor size.) bsolute delay (d abs ) = Dτ = 6.69 0 - sec =.997 0-0 sec. ii) For -stage -i/p Nand gate Given: N =, C out = 00f Gate type Number of inputs To find least delay (D) = N [F /N + P in ] n = [(00/) / +] =.59sec For τ = ps in 80 nm process NND / 5/ 6/ (n+)/ bsolute delay (d abs ) = Dτ =.59 0 - sec =.59 0-0 sec. NOR 5/ 7/ 9/ (n+)/ iii) For -stage -i/p Nor gate XOR, XNOR Given: N =, C out = 00f
To find least delay (D) = N [F /N ] + P in = [(500/) / +] =.7sec For τ = ps in 80 nm processes bsolute delay (d abs ) = Dτ =.7 0 - sec =.68 0-0 sec IV SIMULTION RESULTS The original logical effort model has been studied and tested using 80 nm CMOS technology. n extended model has been introduced and compared against the original one. It improves by including the effect on delay time from transition times at the input. The simulation results by using logical effort shows that the new model exceeds the original model on delay accuracy for -stage inverter, -i/p stage Nand gate, -i/p stage Nor gate by 6.85%, 8%, 5.6% respectively. This result is very beneficial to circuit optimization since a more accurate model will bring closer to the best implementation of a particular logic circuit. Figure illustrates simple gate sized for roughly equal output currents.. From the ratio of input capacitances, one can see that the NND gate has logical effort / and the NOR gate has logical effort 5/. It is interesting but not surprising to note from Table that more complex logic functions have larger logical effort. Moreover, the logical effort of most logic gates grows with the number of inputs to the gate. Larger or more complex logic gates will thus exhibit greater delay. s we shall see later on, these properties make it worthwhile to contrast different choices of logical structure. Designs that minimize the number of stages of logic will require more inputs for each logic gate and thus have larger logical effort. Designs with fewer inputs and thus less logical effort per stage may require more stages of logic. The electrical effort is just a ratio of two capacitances. The load driven by a logic gate is the capacitance of whatever is connected to its output; any such load will slow down the circuit. The input capacitance of the circuit is a measure of the size of its transistors [-6]..0E-09.00E-09 8.00E-0 6.00E-0.00E-0.00E-0 0.00E+00 verage delay in sec verage Delay in sec Using logical Effort verage Delay in sec Using nalytical Method -I/p - stage Nor gate -I/p -stage NND gate -stage Table Delay Comparison between simulated and analytical of a logic gate using logical effort Design -stage -I/p - stage NND gate -I/p - stage Nor gate verage delay in sec verage Delay in sec Using logical Effort V CONCLUSION Use of Logical Effort methods for performance comparison of three different gate topologies were presented with wire capacitance included. Obtained results are found consistent with simulation and are encouraging that NND are faster than NOR in CMOS logic gates Paths are fastest when effort delays are, Path delay is weakly sensitive to stages, sizes but using fewer stages doesn t mean faster paths s and NND best for driving large capacitance. They show that incorporating Logical Effort into the analysis of VLSI three different gate topologies can help find better gate topologies. REFERENCES verage Delay in sec Using nalytical Method.576e-00.05e-00.997 0-0.759e-00.086e-00.59 0-0.89e-00.088e-00.68 0-0. I. Sutherland, B. Sproull, D. Harris, Logical Effort: Designing Fast CMOS Circuits, Morgan Kaufmann Publisher, 999.. M.J Sebastian smith, application specific integrated circuits, addision- wesely 9997.Kabbani, Modeling and optimization of switching power dissipation in static CMOS circuits, IEEE Computer Society nnual Symposium on VLSI (008), pp. 8 85 pr..j. Park et al., 70ps 6-Bit Parallel Binary dder, 000 Symposium on VLSI Circuits Digest of Technical Papers. 5.H. Q. Dao, V. G. Oklobdzija, pplication of Logical Effort Techniques for Speed Optimization and nalysis of Representative dders, 5 th nnual silomar Conference on Signals, Systems and Computers, Pacific Grove, California, November 7, 00. 6.V.G.Oklobdzija, High-Performance System Design: Circuits and Logic, IEEE Press, 999 Figure. Delay plot