Upon completion of unit 1.1, students will be able to



Similar documents
Digital Electronics Detailed Outline

Gates, Circuits, and Boolean Algebra

The components. E3: Digital electronics. Goals:

Content Map For Career & Technology

CHAPTER 11 LATCHES AND FLIP-FLOPS

Decimal Number (base 10) Binary Number (base 2)

Unit/Standard Number. High School Graduation Years 2010, 2011 and 2012

Lecture 8: Synchronous Digital Systems

Experiment # 9. Clock generator circuits & Counters. Eng. Waleed Y. Mousa

BINARY CODED DECIMAL: B.C.D.

Lesson 12 Sequential Circuits: Flip-Flops

To design digital counter circuits using JK-Flip-Flop. To implement counter using 74LS193 IC.

Copyright Peter R. Rony All rights reserved.

A Digital Timer Implementation using 7 Segment Displays

Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop.

Sequential Logic. (Materials taken from: Principles of Computer Hardware by Alan Clements )

DIGITAL COUNTERS. Q B Q A = 00 initially. Q B Q A = 01 after the first clock pulse.

Digital Logic Design Sequential circuits

Digital Logic Design. Basics Combinational Circuits Sequential Circuits. Pu-Jen Cheng

Chapter 9 Latches, Flip-Flops, and Timers

Counters and Decoders

COMBINATIONAL and SEQUENTIAL LOGIC CIRCUITS Hardware implementation and software design

Design Example: Counters. Design Example: Counters. 3-Bit Binary Counter. 3-Bit Binary Counter. Other useful counters:

CHAPTER 3 Boolean Algebra and Digital Logic

ETEC 2301 Programmable Logic Devices. Chapter 10 Counters. Shawnee State University Department of Industrial and Engineering Technologies

ELEC EXPERIMENT 1 Basic Digital Logic Circuits

So far we have investigated combinational logic for which the output of the logic devices/circuits depends only on the present state of the inputs.

Contents COUNTER. Unit III- Counters

DIGITAL ELECTRONICS. Counters. By: Electrical Engineering Department

Electronics Technology

Indiana Department of Education Academic Standards Course Framework ELECTRONICS AND COMPUTER TECHNOLOGY II

Asynchronous Counters. Asynchronous Counters

Digital Fundamentals. Lab 8 Asynchronous Counter Applications

Module 3: Floyd, Digital Fundamental

1. True or False? A voltage level in the range 0 to 2 volts is interpreted as a binary 1.

PLL frequency synthesizer

Seven-Segment LED Displays

Wiki Lab Book. This week is practice for wiki usage during the project.

Engr354: Digital Logic Circuits

Lecture-3 MEMORY: Development of Memory:

DM Segment Decoder/Driver/Latch with Constant Current Source Outputs

Design and Development of Virtual Instrument (VI) Modules for an Introductory Digital Logic Course

Digital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill

SEQUENTIAL CIRCUITS. Block diagram. Flip Flop. S-R Flip Flop. Block Diagram. Circuit Diagram

ECE380 Digital Logic

DEPARTMENT OF INFORMATION TECHNLOGY

CHAPTER IX REGISTER BLOCKS COUNTERS, SHIFT, AND ROTATE REGISTERS

CDA 3200 Digital Systems. Instructor: Dr. Janusz Zalewski Developed by: Dr. Dahai Guo Spring 2012

2 : BISTABLES. In this Chapter, you will find out about bistables which are the fundamental building blocks of electronic counting circuits.

SECTION C [short essay] [Not to exceed 120 words, Answer any SIX questions. Each question carries FOUR marks] 6 x 4=24 marks

Flip-Flops and Sequential Circuit Design. ECE 152A Winter 2012

Flip-Flops and Sequential Circuit Design

Latches, the D Flip-Flop & Counter Design. ECE 152A Winter 2012

Counters are sequential circuits which "count" through a specific state sequence.

EXPERIMENT 8. Flip-Flops and Sequential Circuits

DIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute 5. LECTURE: REGISTERS AND RELATED

Course: Bachelor of Science (B. Sc.) 1 st year. Subject: Electronic Equipment Maintenance. Scheme of Examination for Semester 1 & 2

Chapter 6: From Digital-to-Analog and Back Again

Theory of Logic Circuits. Laboratory manual. Exercise 3

Digital Electronics Part I Combinational and Sequential Logic. Dr. I. J. Wassell

Sequential Logic Design Principles.Latches and Flip-Flops

Standart TTL, Serie Art.Gruppe

ANALOG & DIGITAL ELECTRONICS

Principles of Engineering (PLTW)

Binary Numbers. Binary Octal Hexadecimal

Asynchronous counters, except for the first block, work independently from a system clock.

Electronics Technology

Digital Systems. Syllabus 8/18/2010 1

ENEE 244 (01**). Spring Homework 5. Due back in class on Friday, April 28.

Chapter 2 Logic Gates and Introduction to Computer Architecture

Operating Manual Ver.1.1

ENGI 241 Experiment 5 Basic Logic Gates

Chapter 4 Register Transfer and Microoperations. Section 4.1 Register Transfer Language

WEEK 8.1 Registers and Counters. ECE124 Digital Circuits and Systems Page 1

List of Experiment. 8. To study and verify the BCD to Seven Segments DECODER.(IC-7447).

LOGICOS SERIE Precios sujetos a variación. Ref. Part # Descripción Precio Foto Ref. Quad 2-Input NOR Buffered B Series Gate / PDIP-14

Active Learning in the Introduction to Digital Logic Design Laboratory Course

Lab 1: Study of Gates & Flip-flops

COMBINATIONAL CIRCUITS

Take-Home Exercise. z y x. Erik Jonsson School of Engineering and Computer Science. The University of Texas at Dallas

Counters. Present State Next State A B A B

COURSE SYLLABUS. PRE-REQUISITES: Take CETT-1303(41052); Minimum grade C, CR.

Modeling Sequential Elements with Verilog. Prof. Chien-Nan Liu TEL: ext: Sequential Circuit

DATA SHEETS DE COMPONENTES DA FAMÍLIA LÓGICA TTL GATES AND INVERTERS POSITIVES NAND GATES AND INVERTERS DESCRIÇÃO

Flip-Flops, Registers, Counters, and a Simple Processor

The string of digits in the binary number system represents the quantity

GRADE 11A: Physics 5. UNIT 11AP.5 6 hours. Electronic devices. Resources. About this unit. Previous learning. Expectations

NTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter

Universidad Interamericana de Puerto Rico Recinto de Bayamón Escuela de Ingeniería Departamento de Ingeniería Eléctrica

Set-Reset (SR) Latch

AUTOMATIC NIGHT LAMP WITH MORNING ALARM USING MICROPROCESSOR

Experiment teaching of digital electronic technology using Multisim 12.0

Memory Elements. Combinational logic cannot remember

Gray Code Generator and Decoder by Carsten Kristiansen Napier University. November 2004

Test Code: 8094 / Version 1

Course Requirements & Evaluation Methods

LAB #4 Sequential Logic, Latches, Flip-Flops, Shift Registers, and Counters

Counters & Shift Registers Chapter 8 of R.P Jain

Gates & Boolean Algebra. Boolean Operators. Combinational Logic. Introduction

Transcription:

Upon completion of unit 1.1, students will be able to 1. Demonstrate safety of the individual, class, and overall environment of the classroom/laboratory, and understand that electricity, even at the nominal levels used in this curriculum, can cause bodily harm or even death. 2. Explain and demonstrate how to convert numbers to scientific notation and engineering notation, along with using the correct SI prefixes. 3. Read the manufactured values of resistors and capacitors, along with their tolerances 4. Demonstrate the ability to properly and safely solder and de-solder electronic components along with recognizing improper solder connections Upon completion of unit 1.2, students will be able to 1. Identify and explain the differences between an analog and a digital signal 2. Recognize whether an element is a conductor, an insulator, or a semiconductor. 3. Demonstrate an understanding of the fundamental concepts of voltage, current, and resistance 4. Create and design circuits using Multisim (A Circuit Design Software) Upon completion of unit 1.3, students will be able to 1. Read and explain a manufacturer datasheet, which contains a logic gate s general description, connection diagram, and function table. 2. Categorized circuits by their underlying circuitry, scale of integration, and packaging style. 3. Explain and demonstrate an understanding of the various logic symbols, logic expression, and create truth tables for each gate. 4. Create combinational logic designs implemented with AND gates, OR gates and INVERTER gates. Upon completion of unit 2.1, students will be able to 1. Demonstrate an understanding of the binary number system and its relationship to the decimal number system is essential in the combinational logic design process. 2. Create combinational logic truth tables. 3. Create logic expressions that are derived from a given truth table; likewise, construct a truth table from a given logic expression.

Upon completion of unit 2.2, students will be able to 1. Create a K-map for simplifying logic expressions containing two, three, and four variables. 2. Demonstrate knowledge of NAND and NOR gates through creations of circuits. 3. Compare and implement NAND gates or NOR gates to use fewer Integrated Circuits (IC) than AOI equivalent implementations. Upon completion of unit 2.3, students will be able to 1. Create circuitry using the 7 segment display. 2. Demonstrate and understanding of the two varieties of seven-segment displays, common cathode and common anode. 3. Create any combinational logic expression implementing AOI, NAND, or NOR logic. Upon completion of unit 2.4, students will be able to 1. Demonstrate an understanding of the hexadecimal and octal number systems and their relationship to the decimal number system is necessary for comprehension of digital electronics. 2. Create circuits using XOR or XNOR gates. 3. Create circuits using multiplexors and de-multiplexors, and understand their relation to power usage 4. Apply Two s compliment when working with negative numbers in binary. Upon completion of unit 2.5, students will be able to 1. Use Circuit Design Software to enter and synthesize digital designs into programmable logic devices. 2. Create circuits using Programmable logic devices to implement combinational logic circuits. Upon completion of unit 3.1, students will be able to 1. Create circuits using flip-flop and transparent latches that have the capability to store data and can act as a memory device. 2. Use Flip-flops to design single event detection circuits, data synchronizers, shift registers, and frequency dividers. Upon completion of unit 3.2, students will be able to 1. Demonstrate their knowledge of Asynchronous counters, by creating circuits based upon the output of the previous flip-flop. 2. Understand and implemented the two different flip-flops which are, D or J/K flip-flops. 3. Create up counters, down counters, and modulus counters

Upon completion of unit 3.3, students will be able to 1. Apply their knowledge of synchronous counters, also called parallel counters into circuits. 2. Create Synchronous counters with either D or J/K flip-flops. 3. Create up counters, down counters, and modulus counters. Upon completion of unit 3.4, students will be able to 1. Create a state machine that sequences through a set of predetermined states controlled by a clock and other input signals. 2. Understand how a state machine works, and how it is used in everyday life