Rapid System Prototyping with FPGAs By R.C. Coferand Benjamin F. Harding AMSTERDAM BOSTON HEIDELBERG LONDON NEW YORK OXFORD PARIS SAN DIEGO SAN FRANCISCO SINGAPORE SYDNEY TOKYO Newnes is an imprint of Elsevier % Newnes
Chapter 1: Introduction 1 1.1 FPGA Rapid Design Implementation Potential 2 1.2 Rapidly Evolving Technology Field 4 1.3 Design Skill Set Crossover 4 1.4 Hardware Knowledge for Software/Firmware Designers 6 1.5 Software Knowledge for Hardware Designers 7 1.6 When FPGA Technology May Not Be an Ideal Fit 8 1.7 When FPGAs Technology May Be Appropriate 9 1.8 Summary 11 Chapter 2: FPGA Fundamentals 13 2.1 Overview 13 2.1.1 Categories of Programmable Logic 13 2.1.2 SPLD Device Overview 16 2.1.3 CPLD Device Overview 17 2.1.4 FPGA Device Overview 20 2.1.5 FPGATypes 22 2.2 SRAM-Based FPGA Architecture 24 2.2.1 FPGA Logic Block Structure 25 2.2.2 FPGA Routing Matrix and Global Signals 27 2.2.3 FPGA I/O Blocks 28 2.2.4 FPGA Clock Resources 30 2.2.5 FPGA Memory 32 2.3 Advanced FPGA Features 32 2.4 Summary 33 vii
Chapter 3: Optimizing the Development Cycle 35 3.1 Overview 35 3.2 FPGA Design Flow 36 3.2.1 Requirements Phase 41 3.2.2 Architecture and Design Phase 42 3.2.3 Implementation Phase 46 3.2.4 Veriflcation Phase 48 3.3 Summary 49 Chapter 4: System Engineering 51 4.1 Overview 51 4.2 Common Design Challenges and Mistakes 52 4.3 Defined FPGA Design Process 53 4-4 Project Engineering and Management 55 4.4.1 Team Communication 56 4-4.2 Design Reviews 57 4-4.3 Budgets and Scheduling 59 4.5 Training 61 4.6 Support 63 4.7 Design Configuration Management 64 4-7.1 Controlling the FPGA Design in the Lab 67 4-7.2 Archiving the Design...68 4.8 Summary 70 Chapter 5: FPCA Device-Level Design Decisions 71 5.1 Overview 71 5.2 FPGA Selection Categories 72 5.2.1 FPGA Manufacturer Selection 72 5.2.2 Family Selection 73 5.2.3 Device Selection 74 5.2.4 Package Selection 77 5.3 Design Decisions 78 5.3.1 Data Flow through the FPGA 78 5.3.2 Informed I/O Pin Assignments 79 5.4 Device Selection Checklist 83 5.5 Summary 85 viii
Chapter 6: Board-Level Design Decisions and Allocation 87 6.1 Overview 87 6.2 Packaging 88 6.3 BGA Component Considerations 90 6.3.1 BGA Signal Breakout 90 6.3.2 Mounting and Reworking BGA Components 92 6.3.3 BGA I/O to Signal Assignment 93 6.3.4 BGA Trace Signal Access 94 6.4 I/O Assignment Iteration 95 6.5 FPGA Device Schematic Symbol Generation 96 6.6 Thermal 96 6.7 Board Layout 97 6.7.1 Device Placement and Orientation 98 6.7.2 Headers and Internal Signal Access (Test and Configuration Cable)98 6.8 Signal Integrity 99 6.8.1 Signal Protocol Choices and Implementation 99 6.9 Power 100 6.9.1 Device Decoupling Considerations 100 6.10 Summary 102 Chapter 7: Design Implementation 103 7.1 Overview 103 7.2 Design Architecture 104 7.2.1 Synchronous Design 105 7.2.2 Hierarchical versus Fiat Design 106 7.2.3 Implementing a Hierarchical Design 108 7.3 Design Entry 109 7.3.1 DualNature of HDL Languages 111 7.3.2 HDL Coding Guidance 111 7.3.3 Tools 114 7.4 RTL 115 7.5 Synthesis 118 7.5.1 Logical Synthesis 118 7.5.2 Physical Synthesis 120 7.5.3 Preparing a Design for Synthesis 120 7.5.4 Design Inference versus Instantiation 122 ix
7.6 Place and Route 122 7.7 Summary 124 Chapter 8: Design Simulation 727 8.1 Overview 127 8.2 Stages of Simulation 128 8.3 Types of Simulation Files 129 8.4 How Much Simulation? 131 8.5 Hierarchical Design and Simulation 132 8.6 Common Simulation Mistakes and Tips 132 8.7 Summary 135 Chapter 9: Design Constraints and Optimization 137 9.1 Overview 137 9.2 Design Constraint Management 137 9.2.1 Avoiding Design Over-Constraint 138 9.2.2 Synthesis Constraints 138 9.2.3 Pin Constraints 140 9.2.4 Timing Constraints 144 9.2.5 Area Constraints and Floorplanning 146 9.2.6 Constraint Example 147 9.2.7 Constraints Checklist 149 9.3 Design Optimization 149 9.3.1 FPGA Design Optimization Process 150 9.4 Summary 153 Chapter 10: Configuration 755 10.1 Overview 155 10.2 On-Board Device Configuration 156 10.3 Configuration Cable Interface 156 10.4 JTAG Standard 158 10.4.1 Understanding Pin Operational States 159 10.5 Design Security 160 10.6 Summary 161 Chapter 11: Board-Level Testing 163 11.1 Overview 163 11.1.1 FPGA Design Validation Approaches 164 11.1.2 Access to Critical Internal Signals 164 X
11.1.3 Boundary Scan Support 11.2 Design Debug Checklist 11.3 Summary Chapter 12: Advanced Topics Introduction. 12.1 Overview 12.2 Reduced Power Consumption 12.3 Volume Production Options 12.4 Summary Chapter 13: Cores and Intellectual 13.1 Overview 13.2 TypesoflP 13.3 Categories of IP 13.4 Trade Studies Property.. 13.5 Make versus Buy? 13.5.1 SourcesoflP 13.5.2 Evaluating IP Options 13.5.3 Qualifying an IP Vendor... 13.5.4 Licensing Issues 13.6 IP Implementation/Tools 13.7 IP Testing/Debug 13.8 Summary Chapter 14: Embedded Processing Cores. 14.1 Overview 14.2 FPGA Embedded Processor Types 14.3 FPGA Processor Use Considerations 14-4 System Design Considerations 14.4.1 Co-Design 14-4.2 Processor Architecture 14.4.3 Processor Implementation Options 14.4.4 Processor Core and Peripheral Selection 14.4.5 Hardware Implementation Factors 14.4.6 Software Implementation Factors 14-5 FPGA Embedded Processor Concept Example... 14.6 FPGA Embedded Processor Design Checklist 14.7 Summary 165 166 166 167 167 168 168 169 171 171 173 175 175 176 178 178 179 181 182 182 183 185 185 186 188 190 190 192 195 196 198 199 201 208 209
Chapter 15: Digital Signal Processing 211 15.1 Overview 211 15.2 Basic DSP System 212 15.3 Essential DSP Terms 213 15.4 Architectures 215 15.5 Parallel Execution in DSP Components 216 15.6 Parallel Execution in FPGA 217 15.7 When to Use FPGAs for DSP 219 15.8 FPGA DSP Design Considerations 220 15.8.1 Clocking and Signal Routing 220 15.8.2 Pipelining 221 15.8.3 Algorithm Implementation Choices 221 15.8.4 DSP Intellectual Property (IP) 222 15.9 FIR Filter Concept Example 222 15.10 Summary 224 Chapter 16: Advanced Interconnect 227 16.1 Overview 227 16.2 Interconnection Categories 227 16.3 Advanced I/O Interface Challenges 230 16.4 Implementing an Advanced Parallel I/O Interface 231 16.5 Implementing an Advanced Serial I/O Interface...233 16.6 Summary 236 Chapter 17: Bringing It All Together 237 17.1 System Overview 237 17.2 Requirements Phase 238 17.3 Architectural Phase 240 17.4 Implementation Phase 243 17.5 Verification Phase 245 17.6 Prototype Delivery 247 17.7 Summary 247 Appendix A: Rapid System Prototyping Technical References 249 Appendix B: Design Phases 271 Abbreviations and Acronyms 287 Index 295 xii