2014 International Symposium on System-on-Chip
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1 2014 International Symposium on System-on-Chip (SoC 2014) Tampere, Finland October 2014 IEEE Catalog Number: ISBN: CFP14554-POD
2 Tuesday Oct. 28 SoC 2014 Detailed Programme Schedule Registration Location: in front of Studio 08:30 09:00 SESSION: Opening 09:00 WELCOME TO SOC 2014 Jari Nurmi, Tampere University of Technology, Finland SESSION: Keynote 1 Chair: Jari Nurmi, TUT, Finland 09:15 Challenges for Electronics Design in the Nano-Scale Ricardo Reis, Universidade Federal do Rio Grande do Sul, Brazil SESSION: Special Applications Chair: Geza Kolumban, Pázmány Péter Catholic University, Hungary 10:00 System on Chip Design of a Linear System Solver... 1 Bucek, Jiri; Kubalik, Pavel; Lorencz, Robert; Zahradnicky, Tomas Czech Technical University in Prague, Czech Republic 10:20 Adaptive Runtime Management of Heterogeneous MPSoCs: Analysis, Acceleration and Silicon Prototype (PhD forum submission)... 7 Arnold, Oliver; Fettweis, Gerhard; TU Dresden, Germany 10:40 11:25 Coffee and NORCHIP posters SESSION: Design Analysis Chair: Claudio Brunelli, Microsoft, Finland 11:25 A Cycle-Accurate Network-on-Chip Simulator with Support for Abstract Task Graph Joseph, Jan Moritz; Pionteck, Thilo; Universität zu Lübeck, Germany 11:45 Fast Memory Region: 3D DRAM memory concept evaluated for JPEG2000 algorithm Schoenberger, Alex; Hofmann, Klaus; TU Darmstadt, Germany 12:05 A Transaction-Level Framework for Design-Space Exploration of Hardware- Enhanced Operating Systems Gregorek, Daniel; García-Ortiz, Alberto; University of Bremen, Germany SESSION: Lunch Location: Restaurant Fuuga 12:25 13:30
3 SESSION: Keynote 2 Chair: Roberto Airoldi, NSN, Finland 13:30 New approach for design and implementation of future communications systems Geza Kolumban, Pázmány Péter Catholic University, Hungary SESSION: NORCHIP & SoC 2015 Announcement 14:15 14:30 SESSION: Data-Path Optimizations Chair: Erno Salminen, TUT, Finland 14:30 Optimal Data Path Widths for Energy- and Area-efficient Max-Log-MAP Based LTE Turbo Decoders Broich, Martin; Noll, Tobias G.; RWTH Aachen University, Germany 14:50 Energy-efficiency of floating-point and fixed-point SIMD cores for MIMO processing systems Günther, Daniel; Bytyn, Andreas; Leupers, Rainer; Ascheid, Gerd RWTH Aachen University, Germany 15:10 L2_ISA++: Instruction Set Architecture Extensions for 4G and LTE-Advanced MPSoCs Arnold, Oliver; Neumärker, Felix; Fettweis, Gerhard; TU Dresden, Germany 15:30-16:00 SESSION: Physical Level Design Issues Chair: Peeter Ellervee, Tallinn University of Technology, Estonia 16:00 Limits of gate-level power estimation considering real delay effects and glitches Meixner, Michael; Noll, Tobias G.; RWTH Aachen University, Germany 16:20 Unbalanced Buffer Tree Synthesis to Suppress Ground Bounce for Fine-grain Power Gating Usami, Kimiyoshi 1 ; Miyauchi, Makoto 1 ; Kudo, Masaru 1 ; Takagi, Kazumitsu 1 ; Amano, Hideharu 2 ; Namiki, Mitaro 3 ; Kondo, Masaaki 4 ; Nakamura, Hiroshi 4 1) Shibaura Institute of Technology, Japan; 2) Keio University, Japan; 3) Tokyo University of Agriculture and Technology, Japan; 4) The University of Tokyo, Japan 16:40 Keyed Logic BIST for Trojan Detection in SoC Dubrova, Elena 1 ; Näslund, Mats 2 ; Carlsson, Gunnar 2 ; Smeets, Ben 2 1) KTH, Sweden 2) Ericsson AB, Sweden 17:00 End of session 17:30 Bus transport SESSION: Ice-Hockey Location: Hakametsä Ice Hall 18:30 20:45 Bus transport after the game SESSION: Supper Location: Brewery Restaurant Plevna, Itäinenkatu 8 21:00 23:00
4 WEDNESDAY Oct. 29 SESSION: Invited 3 09:00 Untapped Opportunities for Manycore Communication Optimization Hank Hoffmann, University of Chicago, IL, USA SESSION: Alternative Computing Concepts Chair: Jari Nurmi, TUT, Finland 09:45 Soft-Core efpga for Smart Power Applications Cuppini, Matteo 1 ; Mucci, Claudio 2 ; Franchi Scarselli, Eleonora 1 ; Canegallo, Roberto 2 1) University of Bologna, Italy; 2) STMicroelectronics, Agrate Brianza, Italy 10:05 An Implementation of Auto-Memoization Mechanism on ARM-based Superscalar Processor Shibata, Yuuki 1 ; Tsumura, Takanori 1 ; Tsumura, Tomoaki 1 ; Nakashima, Yasuhiko 2 1) Nagoya Institute of Technology, Japan 2) Nara Institute of Science and Technology, Japan 10:25-11:00 SESSION: Design Methodology Chair: Tapani Ahonen, TUT, Finland 11:00 WOKE: A novel workflow model editor Salminen, Erno; Honkonen, Mikko; Matilainen, Lauri; Hämäläinen, Timo D. Tampere University of Technology, Finland 11:20 Early Power-aware Design Space Exploration for Embedded Systems: MPEG-2 Case Study Ben Abdallah, Feriel 1 ; Trabelsi, Chiraz 2 ; Ben Atitallah, Rabie 2 ; Abed, Mourad 2 1) Institut Mines-Telecom, Telecom ParisTech, France 2) University of Valenciennes, France 11:40 Gamification of System-on-Chip Design Hämäläinen, Timo D.; Salminen, Erno; Tampere University of Technology, Finland 12:00 Formal Verification of Circuit-Switched Network on Chip (NoC) Architectures using SPIN Zaman, Anam; Hasan, Osman; National University of Science and Technology, Pakistan SESSION: Lunch Location: Restaurant Fuuga 12:20 13:30 SESSION: Invited 4 13:30 A Dynamically Reconfigurable Multi-ASIP Architecture for Multi-Standard and Multi-Mode Turbo Decoding Vianney Lapôtre, Université de Bretagne-Sud, France
5 SPECIAL SESSION: Multicore and Manycore Architectures, Applications and Platforms 14:00 A Many-Core Hardware Acceleration Platform for Short Read Mapping Problems Using Distributed Memory Interface with 3D-stacked Architecture Liu, Pei; KTH, Sweden 14:20 Implementation of Multicore Communications API Virtanen, Janne; Matilainen, Lauri; Salminen, Erno; Hämäläinen, Timo D.; TUT, Finland 14:40 I/O Virtualization Utilizing an Efficient Hardware System-level Memory Kornaros, George; Harteros, Kostantinos; Christoforakis, Ioannis; Astrinaki, Maria Technological Educational Institute of Crete, Greece 15:00 A Communication Model and Partitioning Algorithm for Streaming Applications for an Embedded MPSoC Kelly, Wayne 1 ; Flaßkamp, Martin 2 ; Sievers, Gregor 2 ; Ax, Johannes 2 ; Chen, Jianing 1 ; Klarhorst, Christian 2 ; Ragg, Christoph 2 ; Jungeblut, Thorsten 2 ; Sorensen, Andrew 1 1) Queensland University of Technology, Brisbane, Australia 2) Bielefeld University, Germany 15:20 15:40 SPECIAL SESSION: Advances in High Performance Reconfigurable Architectures Chair: Tapani Ahonen, TUT, Finland 15:40 Constraint-Driven Frequency Scaling in a Coarse Grain Reconfigurable Array Hussain, Waqar 1 ; Hoffmann, Henry 2 ; Ahonen, Tapani 1 ; Nurmi, Jari 1 1) TUT, Finland; 2) University of Chigago, IL, USA 16:00 A Reconfigurable MapReduce Accelerator for multi-core all-programmable SoCs Kachris, Christoforos; Sirakoulis, Georgios; Soudris, Dimitrios Democritus University of Thrace, Greece 16:20 Parallel and Distributed Simulation of networked Multi-Core Systems Wehner, Philipp; Göhringer, Diana; Ruhr-University Bochum, Germany SESSION: Closing 16:40 16:50 SESSION: Farewell Banquet Location: Ristorante Como, Hämeenkatu 7 19:00 22:00
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