Interconnection Generation for System-on-Chip Design and Design Space Exploration
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1 Vodafone Chair Mobile Communications Systems, Prof. Dr.-Ing. G. Fettweis Interconnection Generation for System-on-Chip Design and Design Space Exploration Dipl.-Ing. Markus Winter Vodafone Chair for Mobile Communications Systems TU Dresden Kleinheubacher Tagung, Integrierte digitale und analoge Schaltungen
2 TOMAHAWK System-on-Chip WIGWAM demonstration chip 1GBit/s data rate Proof of processor development concept (GenCore) Test of SoC design methodology Scope of this presentation: interconnection as critical part of system! TU Dresden, Markus Winter, Gerhard Fettweis Slide 2
3 Agenda Introduction Problems at interconnection Idea of solution Implementation Results TU Dresden, Markus Winter, Gerhard Fettweis Slide 3
4 Interconnection types Bus based system (tristate): Well-known and well-understood Easy to apply Little area Low protocol overhead Very slow High power consumption Circuit-switched star: Harder to apply (network logic) More area (multiplexer) Low protocol overhead Fast (parallel connections, no tristate) TU Dresden, Markus Winter, Gerhard Fettweis Slide 4
5 Interconnection types Network-on-Chip: Packet-switched system Fast (parallel communication) GALS independent clock domains Complex protocol Error correction mechanisms Hard to apply (router development and linking) Problems with latency and packet loss depending on network load Much more area (multiple routers and FIFOs) TU Dresden, Markus Winter, Gerhard Fettweis Slide 5
6 Problems Problems at application of interconnection scheme to system: What network architecture/topology shall be used? Who instantiates network/arbiter/routers and links s together? Who tests interconnection and communication? Reuse components developed once! Automate instantiation, linking, testing! TU Dresden, Markus Winter, Gerhard Fettweis Slide 6
7 Generation flow Choose network type Define network parameters in XML Generate network description Instantiate and link network and s on top-level Processors with GenCore Instantiation, linking with network gen tool Fast SoC design/design space exploration TU Dresden, Markus Winter, Gerhard Fettweis Slide 7
8 Network architecture Up to now: circuit-switched star topology in network generator Slave side arbitration parallel connections Easy protocol: 2 kinds of requests, 2 kinds of responses Master Network logic address request Slave address response address request write data request next address request read/write response TU Dresden, Markus Winter, Gerhard Fettweis Slide 8
9 Network capabilities - throughput Maximum throughput: TP = n*f*b n number of maximum parallel connections; min(master, slave) f clock frequency B Bit width e.g. 4 masters, 5 slaves, 400MHz, 32 Bit data: TP = 51.2GBit/s Throughput in GBit/s Theoratical maximum read transfers write transfers Burst length TU Dresden, Markus Winter, Gerhard Fettweis Slide 9
10 Network capabilities clock cycle time Minimum cycle time in ns Minimum cycle time depending on number of master slave 4 slaves slaves 10 slaves Number of masters Time to compute arbitration, multiplexing, counter setting Indicates maximum possible clock frequency 600 MHz -> 1.6ns clock cycle, 0.8ns for signal propagation TU Dresden, Markus Winter, Gerhard Fettweis Slide 10
11 Network capabilities area knand Area consumption depending on number of masters 20 1 slave 3 slaves 15 6 slaves 10 slaves Number of masters Area for arbitration logic, multiplexing, counter setting Nearly no overhead -> scales completely with number of s TU Dresden, Markus Winter, Gerhard Fettweis Slide 11
12 Thank you for your attention! TU Dresden, Markus Winter, Gerhard Fettweis Slide 12
13 TU Dresden, Markus Winter, Gerhard Fettweis Slide 13
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