Martino Sykora CURRICULUM VITAE ET STUDIORUM

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1 Martino Sykora CURRICULUM VITAE ET STUDIORUM Via L. Pasteur, Milano Italy Mob: Mail: Personal Information Birthdate: June 15th, 1978 Birthplace: Basel, Switzerland Marital Status: Single Italian Nationality Native Language: Italian Foreign Languages: Good knowledge of English (spoken and written). Skills Programming Languages: Strong knowledge of C, gained both at University and during four years of employement as embedded firmware developer. Strong knowledge of Object Oriented principles and capacity to apply them in practice. Strong knowledge of Java. Good knowledge of C++ and Python. Database: Good knowledge of SQL. Relational databases design skills, from ER schema to its normalization and optimization, focusing the attention on performances and coherency. Use of Apache Derby DBMS. Modeling Languages and Principles: Knowledge of UML and Design Patterns principles.

2 Compilation Systems: Flex, Bison, GCC Internals Integer Linear Programming Tools: Interested in modeling processes as integer linear programming problems, then using tools as AMPL or glpk for their solution. Interest in Graph Theory and Operation Research. Relational Skills: Aptitude for team work: a close interaction and collaboration with collegues, company divisions, partners and customers has been fundamental during my work experience. Powers of work under pressure and to positively face stressful periods. Problem Solving: Hierarchical and modular problems approach, exploiting theoretical and engineering principles for their solution, aiming at a high degree of abstraction. Other: Interested both in applied and theoretical research themes. Education Post-Doc at Politecnico di Milano Ph.D. studies in Information Technology (Ingegneria dell Informazione) at Politecnico di Milano Engineering studies in Computer Engineering (Ingegneria Informatica) at Politecnico di Milano Istituto Tecnico Industriale Statale Stanislao Cannizzaro, Rho (Milano). Work Experiences 2008-today Firmware and Software Engineer at Inpeco S.p.A Inpeco is dedicated to design and manufacture automation systems to improve and simplify biological sample processing in clinical laboratories. My current position is Firmware and Software Engineer, inside the Software Design and Automation Team of Research and Development area. A brief summary of the main activities is reported here below. 1. Development of several automation modules projects, following them in their whole lifecycle, from the requirements analysis to code implementation, debug, test phase, versioning and final release. The final goal is to integrate third party medical devices with Inpeco automation. As embedded firmware engineer, this leads to program a

3 16-bits (C166 family) microcontrolled board, which runs a tiny, realtime and multitask operating system. Each task is implemented in C language, through a licensed IDE (Keil). 2. Design and development of a SQL Apache Derby based Java application, which manages the stored data of a Sample Storing and Retrieval automation module. 3. Design and development (Java) of a Graphic User Interface which allows the user to interact and monitor the automation modules, exchanging messages on Controller Area Network (CAN ). Use of Java Native Interface (JNI) technology to interface the application with a C++ CANOpen Master API dll Post-Doc at Politecnico di Milano. Main research themes follow. 1. Development of a compilation back-end prototype for DSP-Fabric, a emphmulticlustered coprocessor (loop accelerator) designed by STMicroelectronics, Grenoble. The prototype was implemented in Python. 2. Development of an optimizing GCC back-end for ReISC microprocessor, designed by STMicroelectronics, Agrate. 3. Research studies on compilation techniques for parallel architectures. 4. Research studies on dynamic compilation systems Ph.D. studies at Politecnico di Milano Main research theme aimed at the investigation and proposal of novel approaches to the problem of clustering and scheduling for multiclustered and reconfigurable architectures[c3]. Minor research themes focused on advanced techniques for dynamic compilation of Java Bytecode on VLIW architectures. Research studies in Operation Resarch. From May to September 2005 I was a visiting scholar at University of California, San Diego (UCSD) Java developer at Reitek S.p.A., Milano Teaching Teaching Assistant at Politecnico di Milano and Università della Svizzera Italiana (Advanced Learning and Research Institute (ALaRI)), Lugano, CH. A courses summary follow. Software Compilers at ALaRI, within the Master in Embedded Systems Engeneering.

4 Formal Languages and Compilers at Politecnico di Milano, within the Laurea in Ingegneria Informatica (Computer Engineering) program. Algorithms and Data Structures at Politecnico di Milano, within the Laurea in Ingegneria Matematica (Mathematics Engineering) program. Theoretical Computer Science at Politecnico di Milano, within the Laurea in Ingegneria Informatica (Computer Engineering) program. Architectures for multimedia systems at Politecnico di Milano (Como), within the Laurea in Ingegneria Informatica (Computer Engineering) program. Computer Science C at Politecnico di Milano, within the Laurea in Ingegneria Chimica (Chemistry Engineering) program. Laboratory of Information and Business Processes Analysis at Politecnico di Milano, with the Laurea in Ingegneria Gestionale ((Management, Economics and Industrial Engineering) program. Formal Languages at Università della Svizzera Italiana, Lugano, CH, within the Laurea in Scienze della Comunicazione (Communication Science) program. Publications on Journals e Conference Proceedings J1 G. Agosta, L. Breveglieri, G. Pelosi and M. Sykora. Programming Highly Parallel Reconfigurable Architectures for Symmetric and Asymmetric Cryptographic Applications. Journal of Computers, Vol 2, No 8, 2007, Academy Publisher. J2 G. Agosta, S. Crespi Reghizzi, G. Falauto, M. Sykora, JIST: Just-in-Time Scheduling Translation for Parallel Processors. Scientific Programming 3(13), 2005, IOS Press: C0 S. Campanoni, M. Sykora, G. Agosta, S. Crespi Reghizzi, Dynamic Look Ahead Compilation: A Technique to Hide JIT Compilation Latencies in Multicore Environment, Proceeding of CC 2009: C1 M. Sykora, G. Agosta and C. Silvano, Dynamic Configuration of Application- Specific Implicit Instructions for Embedded Pipelined Processors. Proceedings of the 23rd Annual ACM Symposium on Applied Computing (SAC), March , Fortaleza, Brazil C2 G. Agosta, L. Breveglieri, G. Pelosi, M. Sykora, Programming Highly Parallel Reconfigurable Architectures for Public-Key Cryptographic Applications, Proceedings of ITNG 2007, Las Vegas NE, USA.

5 C3 M. Sykora, D. Pavoni, J. Cambonie, R. Costa, S. Crespi Reghizzi, Hierarchical Cluster Assignment for Coarse Grain Reconfigurable Coprocessors, Proceedings of RAW 2007, Long Beach CA, USA. C4 G. Agosta, S. Crespi Reghizzi, D. Domizioli, M. Sykora, Global Instruction Scheduling in Dynamic Compilation for Embedded Systems, Proceedings of JTRES 2006, Paris, France: C5 G. Agosta, S. Crespi Reghizzi, P. Palumbo, M. Sykora, Selective Compilation via Fast Code Analysis and Bytecode Tracing, Proceedings of SAC 2006, Dijon, France: C6 G. Agosta, S. Crespi Reghizzi, G. Falauto, M. Sykora, JIST: Just-in- Time Scheduling Translation for Parallel Processors. Proceedings of IS- PDC/HeteroPar 2004, Cork, Ireland: Awards Best Paper: M. Sykora, G. Agosta and C. Silvano, Dynamic Configuration of Application-Specific Implicit Instructions for Embedded Pipelined Processors. Proceedings of the 23rd Annual ACM Symposium on Applied Computing (SAC), March , Fortaleza, Brazil