Hot Chips Aug 21, HBM Package Integration: Technology Trends, Challenges and Applications Suresh Ramalingam
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1 Hot Chips Aug 21, 2016 HBM Package Integration: Technology Trends, Challenges and Applications Suresh Ramalingam
2 Motivation HBM Packaging Options Interposer Design Supply Chain Agenda Application and Challenges Summary Stacked Silicon Interconnect Technology Refers to Xilinx 3D solutions Page 2
3 FPGA s in the Data Center Today The Accelerator (FPGA or GPU) is used to offload only certain tasks These tasks are called Workloads, and FPGA s are well suited for many workloads Note: Accelerators don t replace the CPU! Hard and Soft is the basic approach Hard is the IO, Memory and PCIe interfaces Does not change Soft is the workload being accelerated Is configured on the fly using PR API s are run on the CPU to reprogram the FPGA to accelerate the workload as needed Average PR happens every 15 minutes! Acceleration requires lots of memory BW
4 I/O density (continuous interface) Multi-Die Technology for HBM (Side-by-Side) >10 4 MCM: Multi-chip Module FO-MCM: Fan-out MCM FL-MCM: Fine-line MCM NTI: No TSV Interconnection SLIM: Silicon-Less Integrated Module EMIB: Embedded Multi-die Interconnect Bridge Cisco, ECTC
5 I/O density (continuous interface) Multi-Die Technology for HBM (Side-by-Side) >10 4 MCM: Multi-chip Module FO-MCM: Fan-out MCM FL-MCM: Fine-line MCM NTI: No TSV Interconnection SLIM: Silicon-Less Integrated Module EMIB: Embedded Multi-die Interconnect Bridge 10 3 EMIB (Intel) 10 2 Grey Zone: Scaling (multi-die integration & fine line & metal layer) EMIB Fan-out Fine Line Substrate NTI/SLIM
6 I/O density (continuous interface) Multi-Die Technology for HBM (Side-by-Side) >10 4 MCM: Multi-chip Module FO-MCM: Fan-out MCM FL-MCM: Fine-line MCM NTI: No TSV Interconnection SLIM: Silicon-Less Integrated Module EMIB: Embedded Multi-die Interconnect Bridge 10 3 FL-MCM (Shinko/Hitachi/UMTC/Ibiden) 10 2 Organic/
7 I/O density (continuous interface) Multi-Die Technology for HBM (Side-by-Side) >10 4 MCM: Multi-chip Module FO-MCM: Fan-out MCM FL-MCM: Fine-line MCM NTI: No TSV Interconnection SLIM: Silicon-Less Integrated Module EMIB: Embedded Multi-die Interconnect Bridge NTI (SPIL) 10 3 FO-MCM (TSMC/ASE/SPIL/Amkor) 10 2
8 I/O density (continuous interface) Multi-Die Technology for HBM (Side-by-Side) >10 4 MCM: Multi-chip Module FO-MCM: Fan-out MCM FL-MCM: Fine-line MCM NTI: No TSV Interconnection SLIM: Silicon-Less Integrated Module EMIB: Embedded Multi-die Interconnect Bridge SSIT (Xilinx) Fiji (AMD)
9 Multi-Die Package Design Rule Comparison Design Rules for Die to Die interconnection Minimum Bump pitch (um) MCM (Substrate) Integrated Fine Layers 130 (C4) 40 (u-bump d2d interface) EMIB (Embedded Multi-die Interconnect bridge) 130 (C4) 40 (u-bump) bridge Silicon Interposer (65 nm BEOL) WLFO (Wafer Level Fan-out) < 40 (u-bump) 40 um RDL pad pitch Via size / pad size (um) 10 / / / 07 10/25 Minimum Line & Space (um) 2 / 2 04 / / 04 2 / 2 Metal thickness (um) Dielectric thickness (um) ~5 1 1 < 5 # of die-to-die connections per layer + GND shield layer (2L) 1000 s 1000 s (bridge interface length limited) 10,000 s 1000 s Minimum die to die spacing (um) < 500 <2500 <100 < 250 # of High density layers feasible Not a limitation 1-3L Not a limitation Not a limitation 1-3L layers Die Sizes for assembly and # of assemblies Not a concern d2d interconnect only Size & # limitation? Not a concern Size limitation? In Production No (2018) No (2017) Yes No not for 2/2um L/S (2018)
10 HBM2 System Overview (Jedec) HBM2 system with SOC/DRAM on interposer with 3-6mm length 24 signals across 55um u-bump pitch across interface Supports 2Gb/s PHY (1Tb/sec bandwidth for 4-Hi) Intel (Jedec) Interposer Parameters * Width Space Thickness Length Resistance 2u 2u 05-2u 6mm 36 ohms
11 Interposer Design Tools & Methodology Vertical Routing a model from ubump to package pin is generated and used by high frequency designs (eg GT and IO) Horizontal Routing Die LVS and extraction Standard extraction ubump is extracted as a subcircuit Vertical route Interposer Top-down view Top Die Interposer with box die LVS and extraction Interposer metal extraction TSV is extracted as a subcircuit TSV ubump Horizontal route Die 1 Die 2 Die 3 Combine the extracted netlists from die and interposer for simulation TSV ubump Interposer side die side Page 11
12 Interposer Design Tools & Methodology 25D - uses the same tool sets as single die design with customized interposer / top die PDK EDA vendor Tools are validated by TSMC design reference flow PKG - uses same tool sets as Flip chip (C4-to-BGA) TSV budget is handled in the Silicon design environment Layout and PI tools must be capable to handle large data sets Interposer Die1 HBM Interposer Design Circuit Design Functional Verification DRC LVS Extraction Extraction Extraction Spice Simulation STA/SI Electrical Analysis u-bump connectivity Page 12
13 Supply Chain Silicon Interposer Approach Xilinx in production with 2 nd generation of products with TSMC CoWoS Logic IP (3) Memory (2) FPGA (1) ubump/sort ubump/sort ubump/sort TSMC CoWoS TM UMC/Inotera SPIL/Amkor/ASE TSV Si Interposer Chip-on-Wafer Bonding (1) Thinning/ C4/Sorting De-carrier & Dicing Packaging on substrate Final Test & Shipment TSV Si Interposer Interposer Thinning/ C4/Sorting KGI die reconfiguration KGD (1~3) chip stacking Packaging on substrate *CoC/CoS/CoWoS-last
14 HBM Integration HPC Application HBM can be 97C and HBM I/F HBM gradient ~14C (~25C/Layer) PCI-e card: Full Length/Full Height Card power: 320W Airflow: 15CFM Typical ambient 30C Air cooling can be a challenge! HBM 8-Hi needs to support > 95C T j HBM I/F:95C - HBM Power map provided by vendors - Thermal model can be done in Flotherm or IcePak environments for example HBM: 30C Inlet ambient to PCI-e card
15 Telecom Application with HBM ( 800GHz and 350 MHz) PKG size:525x525 mm Total Heat Dissipation is 1163 W I/O HBM HBM controller I/O 94C Temperature Rise above C 102C 104C HBM1 HBM3 50C ambient HBM4 105C HBM2 I/O I/O 102C 104C HBM controller 95C Air cooling is a challenge! HBM needs to support > 95C T j Page 15 94C
16 Summary Tb/s low latency bandwidth and lower system power is driving the need for HBM adoption Silicon Interposer (25D) is the incumbent technology of choice Potentially lower cost, fine pitch interconnect wafer-level and substrate based technologies are emerging To drive broader adoption of HBM applications (cooling limited) and higher performance stacks (8-Hi), higher HBM junction temperature (>95C) needs to be supported
17 Follow Xilinx facebookcom/xilinxinc twittercom/xilinxinc youtubecom/xilinxinc linkedincom/company/xilinx plusgooglecom/+xilinx Page 17
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