Temporary Bond Material and Process: Survey Drivers and Reference Flow

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1 Accelerating the next technology revolution Temporary Bond Material and Process: Survey Drivers and Reference Flow SEMICON WEST Temporary Bonding Workshop July 11th, 2011 Sitaram Arkalgud / MJ Yim Copyright 2010 SEMATECH, Inc. SEMATECH, and the SEMATECH logo are registered servicemarks of SEMATECH, Inc. International SEMATECH Manufacturing Initiative, ISMI, Advanced Materials Research Center and AMRC are servicemarks of SEMATECH, Inc. All other servicemarks and trademarks are the property of their respective owners.

2 Outline 3D TSV Outlook 3D TSV Integration Reference Flow and Temporary Bonding Challenges/Survey Drivers 5 August

3 3D options (ref: 2009 ITRS) 3D system-in-package Eg: wire bonding, packageon-package 3D wafer-level packaging TSVs used at bond pads Eg: stacked memory, CIS 3D global interconnects Stacked IC, 3D system-onchip, through silicon stacking TSVs connect circuit blocks at the global wiring level 3D intermediate interconnects Higher density than global Interconnects smaller circuit blocks Local (device) level Transistor level stacking Courtesy: Samsung. Source: Qualcomm K Saraswat Stanford U. Source: Samsung Source: IBM Source: Intel 5 August

4 3D TSV Outlook Near future ( ) Interposer products Wide IO DRAM (mobile) Source: Xilinx Source: Nokia Future ( ) Heterogenous integration (beyond memory on logic) Higher (>> 5 stacking levels) Smaller (<< 5 micron width, >> 10 aspect ratio) Far future ( ) Beyond CMOS (photonics, sensors, etc) 5 August

5 Schematic Of Wide IO TSV Product (Source: Nokia, Qualcomm) Focus area for SEMATECH Tier 2 Thickness ~ 100 µm Active Face Down Other products and integrations exist Wide IO provides context for SEMATECH development work Tier 2 could be a single die or multiple dies (Eg: a 4-tier Wide IO DRAM stack) Graphics adapted from R. Radojcic, Qualcomm Underfill Gap ~ 10 µm µ-bump Pitch ~ µm BackSide Metal Pitch ~ 5-25 µm Tier 1 Thickness ~ 50 µm Active Face Down TSV Size ~ 5-10 µm Pitch ~ µm Underfill Gap ~ hi 10 s of µm Flip Chip Bump Size ~ <100 um Pitch ~ um Package Substrate Thickness ~ 100 s of µm BGA Bump Pitch ~ 1mm 5 August

6 Various Key Process Modules and 3D-stacking Options (source: ITRS 2009, ISMI 2009) 5 August

7 Industry Reference Flows and Temporary Bonding Adhesive Challenges Option 1 (WtW) Process Flow Carrier wafer Issues Option 2 (WtW) Glass or Si Adhesive coating Spin coating Bake Thickness tolerance No residual solvent Wafer bonding T/T/P Void free Alignment TSV process Back-grind Cu reveal Passivation Planarization RDL/Bumping Large TTV & chipping Side etching Delamination Void & Delamination Warpage Final bonding Cu-Cu Cu-Sn-Cu w/ WLUF Void & Delamination De-bonding De-bonding Thermal/chemical/ UV laser release Cleaning Bump deformation 5 August Residue

8 Industry Reference Flows and Temporary Bonding Adhesive Challenges Option 3 (DtW) Process Flow Carrier wafer Issues Option 4 (DtW) Glass or Si Adhesive coating Spin coating Thickness tolerance Bake No residual solvent Wafer bonding T/T/P Void free Alignment TSV process Back-grind Large TTV & chipping Cu reveal Side etching Passivation Delamination Planarization RDL/Bumping Void & Delamination Warpage Dicing tape transfer lamination Void & Delamination De-bonding De-bonding Thermal/chemical/ UV laser release Cleaning UV layer damage 5 August Residue

9 Reference Flow Options Option 3 Sematech 3D baseline: DtW, bumpless, Cu-Cu Reference flow options memory memory memory memory Logic Logic TSV (DtS)=>Memory cube to Logic TSV (DtD)=>Backend (Molding/BA/singulation) Option 2 or 4 Option 4 Logic die w/ncf (C4 bump face down) C4 process for Tier 1 Tier 2 Die to Tier 1 die attach process (T/C bonding) Molding, etc Various temporary bonding/debonding supports are required for WtW and DtW processes. 5 August

10 Temporary Bond Process Flow Issues APPLY ALIGN & BOND WAFER PAIR DEBOND CLEAN PROCESSING ISSUE / CHALLENGE METHODS Thickness Uniformity Spin coat < 10 um Room Temp? Bond Strength Thermal up to what max. temp? Chemicals Grind/polish Handling Room Temp? Method Throughput Thermal C4 or ubump? Cleaning chemical at dicing tape? Spray Laminate UV UV / Laser Immersion Zone Combination Mechanical Plasma Combination Chemical Combination Zone Process Requirements Must be Established to Identify Temporary Bond Materials (adhesive and carrier) as well as Associated Debond Methods 5 August

11 3D Temporary Bonding Adhesive Requirements Si or glass carrier wafer compatible Protect the topography of the device wafer Bumped (C4 or micro-bumped) or non-bumped wafers 5 um TTV (thin adhesive and thick adhesive) Strong enough to withstand wafer backside process Thermally stable to withstand backside process Chemically stable to withstand backside process Easily de-bonded Residue free Device wafer side & carrier wafer side for re-use Other thermo-mechanical properties considerations Low out-gassing, low or higher modulus for low stress and warpage, etc 5 August

12 Temporary Bonding Materials These temporary bonding materials are generally chemically stable to temperatures of 250 ºC, above which some decomposition or out-gassing occurs Broad range of process conditions depending on materials and bonding/debonding methods Bonding method: thermal (High, Medium or Low temperature) or UV or others? De-bonding method: Room to Low, Medium or High temperature de-bonding? Adhesive thickness: any thickness guideline? Thermal stability during TSV backside processes and permanent bonding Cleaning chemical?? How to differentiate the materials is primarily dependant to (1) TSV applications, (2) backside process conditions, (3) release process conditions and where to release, etc Real temporary adhesive material capabilities should be evaluated not only by back end process temperatures, but also by other factors including time at those temperatures, the presence of a vacuum or pressure environment, energy level in a PECVD, and the residual wafer stress at elevated temperature 5 August

13 Bond Material Application Space De-bonding temp (oc) Max Process Temp. of Materials in Bumped Flow Sn-based Solder Liquidis Start Bumped Thermal Stability of Dicing Tape (desired debond temperature is 25 C) Thermal stability (oc) Max Process Temp. of Materials in Bumpless Flow Bumpless Bond Material and Debond Process Must Satisfy Process Requirements Space Limited options if high temp processing & low temp debonding needed 500 Debond Process Zone Debond Thermal Slide-off Chemical de-bond Mechanical de-bond Laser De-bond Adhesives A B C D E F G H 5 August

14 Industry User Community Survey Temporary Bonding / Debonding Landscape Unsettled Process / Material Selection Dependent on Reference Flow Material and Tool Suppliers offer multiple solutions 3D TSV Reference Flow Critical to Identifying Consensus Solution Limited Feedback suggests a desire for room temperature bond and debond processes with an adhesive material which can withstand temperatures of up to 400C Build Consensus Temporary Bonding / Debonding is an ENABLING technology; lowering costs requires broad acceptance of application requirements Industry User Survey to help set technical requirements of Temporary Bond Materials and Debond Process; validation of reference flow approach Accelerate Innovation and Collaboration Identify supplier partners to develop temporary bond solutions. 5 August

Welcome & Introduction

Welcome & Introduction Accelerating the next technology revolution Sitaram Arkalgud, PhD Director Interconnect Temporary Bond Workshop SEMICON West July 11, 2011 San Francisco CA Copyright 2008 SEMATECH,