Outline. nmos Transistor. MOS Capacitor. Transistors and Scaling Introduction to Nanotechnology. Transistor theory Transistor reality Scaling

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1 15398 ntroduction to Nanotechnology Transistors and Scaling Transistor theory Transistor reality Scaling Outline Seth Copen Goltein CMU Adapted from ntro to CMOS S Design, Harris lecture Seth Copen Goltein 1 lecture Seth Copen Goltein nmos Transistor Four terminals:, source, drain, body Gate oxide body stack looks like a capacitor Gate and body are conductors SiO (oxide) is a very good insulator Called metal oxide semiconductor (MOS) capacitor Even though is Source Gate Drain no longer made of metal Polysilicon SiO MOS Capacitor Gate and body form MOS capacitor Operating modes Accumulation g < + Depletion (a) nversion polysilicon silicon dioxide insulator ptype body < g < t depletion region + (b) p bulk Si g > t + inversion region depletion region (c) lecture Seth Copen Goltein 3 lecture Seth Copen Goltein 4

2 Terminal oltages Mode of operation depen on g, d, s + + gd = g s gd = g d s d = d s = + gd Source and drain are symmetric diffusion terminals By convention, source is terminal at lower voltage Hence nmos body is grounded. First assume source is too. Three regions of operation Cutoff inear Saturation g No channel = nmos Cutoff = + s ptype body b g + gd d lecture Seth Copen Goltein 5 lecture Seth Copen Goltein 6 nmos inear Channel forms Current flows from d to s (e from s to d) as > t Similar to + g linear resistor s d > t + gd = lecture Seth Copen Goltein 7 + s ptype body b g ptype body b = + > gd > t d < < t nmos Saturation Channel pinches off independent of e say current saturates > t + s ptype body b + gd < t > t lecture Seth Copen Goltein 8 g d

3 Characteristics n inear region, depen on How much charge is in the channel? How fast is the charge moving? Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Q channel = t ox polysilicon ptype body SiO oxide (good insulator, ε ox = 3.9) g + + source C g gd drain channel + s ptype body d lecture Seth Copen Goltein 9 lecture Seth Copen Goltein 1 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Q channel = C C = Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Q channel = C C = C g = ε ox /t ox = C ox C ox = ε ox / t ox = t ox polysilicon ptype body SiO oxide (good insulator, ε ox = 3.9) g + + source C g gd drain channel + s ptype body d t ox polysilicon ptype body SiO oxide (good insulator, ε ox = 3.9) g + + source C g gd drain channel + s ptype body d lecture Seth Copen Goltein 11 lecture Seth Copen Goltein 1

4 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Q channel = C C = C g = ε ox /t ox = C ox C ox = ε ox / t ox = gc t = ( /) t Carrier velocity Charge is carried by e Carrier velocity v proportional to lateral E field between source and drain v = t ox polysilicon ptype body SiO oxide (good insulator, ε ox = 3.9) g + + source C g gd drain channel + s ptype body d lecture Seth Copen Goltein 13 lecture Seth Copen Goltein 14 Carrier velocity Charge is carried by e Carrier velocity v proportional to lateral E field between source and drain v = μe μ called mobility E = Carrier velocity Charge is carried by e Carrier velocity v proportional to lateral E field between source and drain v = μe μ called mobility E = / Time for carrier to cross channel: t = lecture Seth Copen Goltein 15 lecture Seth Copen Goltein 16

5 Carrier velocity Charge is carried by e Carrier velocity v proportional to lateral E field between source and drain v = μe μ called mobility E = / Time for carrier to cross channel: t = / v Now we know = nmos inear How much charge Q channel is in the channel How much time t each carrier takes to cross lecture Seth Copen Goltein 17 lecture Seth Copen Goltein 18 Now we know nmos inear How much charge Q channel is in the channel How much time t each carrier takes to cross Now we know nmos inear How much charge Q channel is in the channel How much time t each carrier takes to cross Q = t = channel Qchannel = t = μc = β gs t ox gs t β: gain factor Depen on: Process geometry β = μcox lecture Seth Copen Goltein 19 lecture Seth Copen Goltein

6 nmos Saturation f gd < t, channel pinches off near drain hen > at = t Now drain voltage no longer increases current = nmos Saturation f gd < t, channel pinches off near drain hen > at = t Now drain voltage no longer increases current = β at gs t at lecture Seth Copen Goltein 1 lecture Seth Copen Goltein nmos Saturation f gd < t, channel pinches off near drain hen > at = t Now drain voltage no longer increases current at = β gs t at β = ( ) gs t nmos Summary Shockley 1 st order transistor models gs < t = β < β ( ) > gs t at gs t at cutoff linear saturation lecture Seth Copen Goltein 3 lecture Seth Copen Goltein 4

7 Example Consider a.6 μm process From AM Semiconductor t ox = 1 Å μ = 35 cm /*s t =.7 Plot vs. =, 1,, 3, 4, 5 Use / = 4/ λ (ma) 35 1 A/ ox 8 β = μc = ( ) = μ = 5 = 4 = 3 = gs = pmos All dopings and voltages are inverted for pmos Mobility μ p is determined by holes Typically 3x lower than that of electrons μ n 1 cm /*s in AM.6 μm process Thus pmos must be wider to provide same current lecture Seth Copen Goltein 5 lecture Seth Copen Goltein 6 deal Transistor Shockley 1 st order transistor models deal nmos Plot 18 nm TSMC process gs < t = β < β ( ) > gs t at gs t at cutoff linear saturation deal Models β = 155(/) μa/ t =.4 DD = 1.8 (μa) 4 3 = 1.8 = 1.5 = 1. 1 =.9 = lecture Seth Copen Goltein 7 lecture Seth Copen Goltein 8

8 Simulated nmos Plot 18 nm TSMC process BSM 3v3 SPCE models hat differs? (μa) 5 = = 1.5 = 1. 1 =.9 5 = Simulated nmos Plot 18 nm TSMC process BSM 3v3 SPCE models hat differs? (μa) 5 ess ON current No square law 15 Current increases 1 in saturation = 1.8 = 1.5 = 1. =.9 =.6 lecture Seth Copen Goltein 9 lecture Seth Copen Goltein 3 elocity Saturation el Sat Effects e assumed carrier velocity is proportional to Efield v = μe lat = μ / At high fiel, this ceases to be true Carriers scatter off atoms elocity reaches v sat Electrons: 61 x 1 6 cm/s Holes: 48 x 1 6 cm/s Better model μelat v = vsat = μesat Elat 1+ E sat ν sat ν sat / ν slope = μ E sat E lat E sat 3E sat deal transistor ON current increases with DD ( gs t ) β = μc = ( ) ox gs t elocitysaturated ON current increases with DD ( ) = C v ox gs t max Real transistors are partially velocity saturated Approximate with αpower law model α DD 1 < α < determined empirically lecture Seth Copen Goltein 31 lecture Seth Copen Goltein 3

9 (μa) αpower Model gs < t cutoff = at < at linear at at > at saturation Simulated αlaw Shockley β = P = 1.8 = 1.5 = 1. =.9 =.6 lecture Seth Copen Goltein 33 ( ) α ( ) / at c gs t = P at v gs t α Channel ength Modulation Reversebiased pn junctions form a depletion region Region between n and p with no carriers idth of depletion d region grows with reverse bias eff = d Shorter eff gives more current increases with Even in saturation GND Source eff p GND lecture Seth Copen Goltein 34 DD Gate DD Drain Depletion Region idth: d bulk Si OFF Transistor Behavior hat about current in cutoff? Simulated results hat differs? Current doesn t go to in cutoff 1 ma 1 μa 1 μa 1 μa 1 na 1 na 1 na 1 pa 1 pa Subthreshold Region Subthreshold Slope t Saturation Region = eakage Sources Subthreshold conduction Transistors can t abruptly turn ON or OFF Junction leakage Reversebiased PN junction diode current Gate leakage Tunneling through ultrathin dielectric Subthreshold leakage is the biggest source in modern transistors lecture Seth Copen Goltein 35 lecture Seth Copen Goltein 36

10 Subthreshold eakage Subthreshold leakage exponential with e nvt = 1 e gs t vt 1.8 = βvte n is process dependent, typically DB Drainnduced Barrier owering Drain voltage also affect t t = t η ttη High drain voltage causes subthreshold leakage to. lecture Seth Copen Goltein 37 saraswat Punch through lecture Seth Copen Goltein 38 DB Drainnduced Barrier owering Drain voltage also affect t t = t η ttη High drain voltage causes subthreshold leakage to increase. Junction eakage Reversebiased pn junctions have some leakage D T e v D = S 1 s depen on doping levels And area and perimeter of diffusion regions Typically < 1 fa/μm p+ p+ p+ n well p substrate saraswat lecture Seth Copen Goltein 39 lecture Seth Copen Goltein 4

11 Gate eakage Carriers may tunnel thorough very thin oxides Predicted tunneling current (from [Song1]) JG (A/cm ) 1 9 t ox 1 6 DD trend.6 nm.8 nm nm 1. nm nm 1.9 nm 1 3 Temperature Sensitivity ncreasing temperature Reduces mobility Reduces t with temperature ON OFF with temperature 1 6 Negligible for older processes May soon be critically important DD lecture Seth Copen Goltein 41 lecture Seth Copen Goltein 4 Temperature Sensitivity ncreasing temperature Reduces mobility Reduces t ON decreases with temperature OFF increases with temperature increasing temperature So hat? So what if transistors are not ideal? They still behave like switches. But these effects matter for Supply voltage choice ogical effort Quiescent power consumption Pass transistors Temperature of operation lecture Seth Copen Goltein 43 lecture Seth Copen Goltein 44

12 Scaling Metho Dennard: scaling method that maintains constant electric field polysilicon t ox ptype body X j SiO (good in saraswat lecture Seth Copen Goltein 45