Design of VLSI Circuits and Systems

Transcription

1 EEM216A Fall 2008 Design of VLSI ircuits and Systems Mon & Wed 2:00-3:50pm 2444 Boelter Hall ourse Description This course focuses on advanced concepts of VLSI circuit and system design in state of the art MOS technologies. Topics include: ircuit-level optimization using gate size, supply and threshold voltage; layout of circuit blocks optimized for speed, power, or area. Advanced concepts of retiming, place and route will be employed in class projects, in addition to the design of custom blocks. The applications include micro-processors, signal and multimedia processors, portable devices, memory and periphery. ourse topics are continuously updated to track unique technological features such as power leakage, interconnect, clock and power distribution, impact of device variability on the design. This quarter, special focus will be given to design optimization. EEM216A / Fall 2008 D. Markovic / Slide 2

2 EE115 vs. EEM216A EE115 (introductory material) Basic transistor and circuit models Basic circuit design styles and logic gates Design of custom blocks (adders, memories, ) EEM216A (advanced material) Transistor models of varying accuracy Design under constraints: power, area, performance, robustness More advanced design techniques Learning challenges in the coming years reating new solutions to challenging design problems EEM216A / Fall 2008 D. Markovic / Slide 3 lass Topics Fundamentals Technology and modeling Scaling and limits of scaling Design for deep sub-micron MOS Static MOS, transistor sizing, buffer design, high-speed MOS design styles, dynamic logic Process variations, leakage Design techniques for low power and low voltage Power minimization at technology, circuit, architecture levels Energy-delay optimization Arithmetic circuits System-level issues Timing strategies, logic synthesis lock and power distribution Physical design EEM216A / Fall 2008 D. Markovic / Slide 4

3 Teaching Staff Instructor Dejan Markovic Office hours: E Eng-IV Mon & Wed 4:30-6pm TA Vaibhav Karkare AD tools / reader [email protected] Assistant Lori Miller Homework drop-off Eng-IV EEM216A / Fall 2008 D. Markovic / Slide 5 lass Material Textbook: J. Rabaey, A. handrakasan, B. Nikolic, Digital Integrated ircuits: A Design Perspective, (2nd Edition), Prentice Hall, Other books: N. Weste, D. Harris, MOS VLSI Design: A ircuits and Systems Perspective, (3rd Edition), Addison Wesley, A. handrakasan, W. Bowhill, F. Fox, Design of High-Performance Microprocessor ircuits, IEEE Press, W.J. Dally and J.W. Poulton, Digital System Engineering, ambridge University Press, B. Wong, A. Mittal, Y. ao, G.W. Starr, Nano MOS ircuit and Physical Design, Wiley-Interscience, Selected papers: Available on classwiki Linked from IEEE Xplore ( (need to be logged in to a campus machine) EEM216A / Fall 2008 D. Markovic / Slide 6

4 Other Sources ore material IEEE Journal of Solid-State ircuits (JSS) IEEE International Solid-State ircuits onference (ISS) European Solid-State ircuits onference (ESSIR) Symposium on VLSI ircuits (VLSI) ustom Integrated ircuits onference (I) Other conferences and journals AD topics International onference on omputer Aided Design (IAD) Design Automation onference (DA) EEM216A / Fall 2008 D. Markovic / Slide 7 lass Organization & Grading Five items will make your final grade: Homeworks (4) 15% Project 30% Midterm 25% Final exam 25% Participation 5% lass project Phase 1 Phase 2 Report Wk h1 h2 h3 h4 10/8 10/20 10/29 11/14 M 11/X (x = 5 or 6) P 12/3 EEM216A / Fall 2008 D. Markovic / Slide 8

5 lass Website EEweb: class notes, handouts, assignments, discussion AD tools, papers: classwiki classwiki EEM216A / Fall 2008 D. Markovic / Slide 9 lasswiki reate an account: use your ULA username! EEM216A / Fall 2008 D. Markovic / Slide 10

6 Setting up EEM216A AD Environment You need an ee account machines Your account will be mapped to i2950g1 and i2950g2 Sign up for classwiki (do it today!) Use your ee/seas username to sign up Once you sign up, I need to add you to ee216a group Homework coming out on Wed which will assume that you are all set! EEM216A / Fall 2008 D. Markovic / Slide 11 Tools adence software only! Phased out Electric software Online documentation and tutorials 90nm MOS technology adence gpdk090 & gsclib 9 metal layers Important tools / skills from EE115 Design apture: Virtuoso Schematic / Layout Editor ircuit Simulation: Spectre / Ocean Design Verification (DR, LVS, Extraction): Assura EE115 tutorials (if you think you need to catch up): (ourtesy: IBM) EEM216A / Fall 2008 D. Markovic / Slide 12

7 EEM216A Goals Understanding the basic building blocks of VLSI Transistors/Wires Logic Gates and Layout Datapath Blocks Be able to conceptually model a system Logic Optimization State Machine Design (RTL) Be able to build a system (using a subset of the tools) Verilog Modeling Synthesis Place and Route Understanding the constraints and tradeoffs Delay analysis (gates and interconnects) locking methodology System integration issues (Power/Ground routing, Noise) EEM216A / Fall 2008 D. Markovic / Slide 13 EEM216A Fall 2008 Lecture 1: Introduction Digital Integrated ircuit Design: Trends and hallenges Dejan Markovic [email protected]

8 Moore s Law In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months He made a prediction that semiconductor industry will double its effectiveness every 18 months The complexity for minimum component costs has increased at a rate of roughly a factor of two per year. ertainly over the short term, this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years. That means by 1975, the number of components per integrated circuit for minimum cost will be 65,000. [G. Moore, Electronics, 1965] EEM216A / Fall 2008 D. Markovic / Slide 15 Moore s Law 1965 [ Intel, ISS 2005] EEM216A / Fall 2008 D. Markovic / Slide 16

9 Moore s Law 2005 [ Intel, ISS 2005] EEM216A / Fall 2008 D. Markovic / Slide 17 Evolution in omplexity EEM216A / Fall 2008 D. Markovic / Slide 18

10 Microprocessor Examples Moore s law Number of transistors Logic density Die size Frequency Power EEM216A / Fall 2008 D. Markovic / Slide 19 Number of Transistors Transistors (MT) X growth in 1.96 years! Pentium 4 Pentium Pro (P6) Pentium (P5) 486 (P4) 386 (P3) 286 (P2) (P1) Year S. Borkar (Intel) Transistors on lead microprocessors double every 2 years EEM216A / Fall 2008 D. Markovic / Slide 20

11 Logic Density 1000 Logic Transistors/mm 2 Logic Density i860 Pentium II (R) 486 Pentium Pro (R) Pentium (R) 2x trend Intel 1.5µ 1.0µ 0.8µ 0.6µ 0.35µ 0.25µ 0.18µ 0.13µ Shrinks and compactions meet density goals New micro-architectures drop density EEM216A / Fall 2008 D. Markovic / Slide 21 Die Size Growth 100 Die size (mm) Pentium Pro 486 Pentium ~7% growth per year ~2X growth in 10 years Year S. Borkar (Intel) Die size grows by 14% to satisfy Moore s law EEM216A / Fall 2008 D. Markovic / Slide 22

12 Frequency Frequency (Mhz) Doubles every 2 years Pentium 4 Pentium Pro Pentium Year S. Borkar (Intel) Lead microprocessor frequency doubles every 2 years EEM216A / Fall 2008 D. Markovic / Slide 23 Processor Frequency Trend 10,000 Intel IBM Power P DE Gate delays/clock Processor freq scales by 2X per generation 100 Game over! 1, S 21164A A Pentium(R) II MP Pentium Pro 601, 603 (R) Pentium(R) Mhz 10 1 Gate Delays/ lock V. De, S. Borkar ISLPED 99 Frequency doubles each generation Number of gates/clock reduce by 25% EEM216A / Fall 2008 D. Markovic / Slide 24

13 Technology Roadmap (2002) International Technology Roadmap for Semiconductors (ITRS) Year DRAM ½ pitch [nm] MPU transistors/chip 97M 153M 243M 386M 773M 1.55G 3.09G Wiring levels High-perf. phys. gate [nm] High-perf. VDD [V] Local clock [GHz] High-perf. power [W] Low-power phys. gate [nm] Low-power VDD [V] Low-power power [W] Node years: 2007/65nm, 2010/45nm, 2013/32nm, 2016/22nm EEM216A / Fall 2008 D. Markovic / Slide 25 Technology Scaling ISS data 100 x1.4 / 3 years 1000 κ 0.7 Power Dissipation (W) x4 / 3 years 85 (a) Power dissipation vs. year. 90 Year MPU DSP 95 Power Density (mw/mm 2 ) κ Scaling Factor κ (normalized by 4µm design rule) 10 (b) Power density vs. scaling factor. T. Kuroda EEM216A / Fall 2008 D. Markovic / Slide 26

14 Processor Power 100 Max Power (Watts) Pentium II (R) Pentium Pro (R) Pentium(R) 486 Pentium(R) MMX? µ 1µ 0.8µ 0.6µ 0.35µ 0.25µ 0.18µ 0.13µ Intel Lead processor power increases every generation ompactions provide higher performance at lower power EEM216A / Fall 2008 D. Markovic / Slide 27 Power will be a Problem Power (Watts) KW 5KW 1.5KW 500W Pentium Pro Pentium Year S. Borkar (Intel) Power delivery and dissipation will be prohibitive EEM216A / Fall 2008 D. Markovic / Slide 28

15 New Trend: Parallel Hardware Vdd Logic Block 0.7 x Vdd Freq = 1 Throughput = 1 Active Power = 1 SD Lkg Power = 1 S. Borkar (Intel) Logic Block Freq = 0.7 Throughput = 1.4 Logic Block Active Power = 0.7 SD Lkg Power = 0.7 Higher logic throughput, yet lower power EEM216A / Fall 2008 D. Markovic / Slide 29 Dual ore Rule of thumb Voltage Frequency Power Performance 1% 1% 3% 0.66% In the same process technology ache ache ore ore ore S. Borkar (Intel) Voltage = 1 Freq = 1 Area = 1 Power = 1 Perf = 1 Voltage = -15% Freq = -15% Area = 2 Power = 1 Perf = ~1.8 EEM216A / Fall 2008 D. Markovic / Slide 30

16 From Multi to Many 13mm, 100W, 48MB ache, 4B Transistors, in 22nm 12 ores 48 ores 144 ores S. Borkar (Intel) Relative Performance Single ore Performance Large Med Small System Performance TPT Large Med Small One App Two App Four App Eight App EEM216A / Fall 2008 D. Markovic / Slide 31 Future Multi-core Platform S. Borkar (Intel) GP GP GP GP General Purpose ores GP SP GP SP GP GP GP GP GP SP SP GP Special Purpose HW Interconnect fabric Heterogeneous Multi-ore Platform SO EEM216A / Fall 2008 D. Markovic / Slide 32

17 Typical Power Delivery System S. Borkar (Intel) Power Delivery Electronics Mobile Platform, ~50W EEM216A / Fall 2008 D. Markovic / Slide 33 Software hallenge ITRS 2007 EEM216A / Fall 2008 D. Markovic / Slide 34

18 Impact of Process Variations 1.4 Today S. Borkar (Intel) Normalized Frequency % 5X 130nm Normalized Leakage (Isb( Isb) Frequency ~30% Leakage Power ~5-10X EEM216A / Fall 2008 D. Markovic / Slide 35 Implications Reliability Extreme variations (Static & Dynamic) will result in unreliable components Impossible to design reliable system as we know today Transient errors (Soft Errors) Gradual errors (Variations) Time dependent (Degradation) Test One-time-factory testing will be out S. Borkar (Intel) Burn-in to catch chip infant-mortality will not be practical Test HW will be part of the design Dynamically self-test, detect errors, reconfigure, & adapt EEM216A / Fall 2008 D. Markovic / Slide 36

19 In a Nut-shell 100 BT integration capacity 100 Billion Transistors Billions unusable (variations) Some will fail over time Intermittent failures S. Borkar (Intel) Yet, deliver high performance in the power & cost envelope EEM216A / Fall 2008 D. Markovic / Slide 37 Advantage of a Small ore Large ore Medium ore Small ore S. Borkar (Intel) Error Error Error Large Area of onfinement High Performance Loss Small Area of onfinement Low Performance Loss Too many small cores provide higher throughput and resiliency EEM216A / Fall 2008 D. Markovic / Slide 38

20 The Quest for Parallel Began in 1965 It is difficult to predict at the present time just how extensive the invasion of the microwave area by integrated electronics will be. The successful realization of such items as phased array antennas, for example, using a multiplicity of integrated microwave power sources, could completely revolutionize radar. [G. Moore, Electronics, 1965] EEM216A / Fall 2008 D. Markovic / Slide 39 Parallel Data Processing Power limited technology scaling Increased impact of process variations More leakage power, multiple threshold devices Single dimensional Multidimensional data Multi-core Processors MIMO ommunications Neuroscience IBM / Sony / Toshiba Belkin EEM216A / Fall 2008 D. Markovic / Slide 40

21 Different Energy-Delay Requirements Same principle, different optimization goals Processors Maximize performance Highest V DD required ommunications Minimize energy & area Typically, sensitivity ~ 1 Neuroscience Power density: 0.8mWmm 2 Aggressive V DD scaling Energy 0 V DD scaling Processors ommunications Neural Delay EEM216A / Fall 2008 D. Markovic / Slide 41 ASIs on The Road to Extinction? EEM216A / Fall 2008 D. Markovic / Slide 42

22 The Age of oncurrency and Flexibility UB Pleiades Heterogeneous reconfigurable fabric Xilinx Vertex 4 Intel Montecito ARM AMD Dualore NTT Video codec (4 Tensilica cores) IBM/Sony ell Processor ourtesy: J. Rabaey (UB) EEM216A / Fall 2008 D. Markovic / Slide 43 FPGAs going Multi-core BEE2 compute module 14 x17 22 layer PB ourtesy: J. Wawrzynek (UB) EEM216A / Fall 2008 D. Markovic / Slide 44

23 Moore s Law and the Long Term What level? EEM216A / Fall 2008 D. Markovic / Slide 45 Moore s Law and the Long Term What level? Within your working life? ? When? EEM216A / Fall 2008 D. Markovic / Slide 46

24 Silicon Technology Reaches Nanoscale Intel EEM216A / Fall 2008 D. Markovic / Slide 47 Sub-wavelength Optical Lithography EEM216A / Fall 2008 D. Markovic / Slide 48

25 5 nm Scaling toward 10 nm Node Bulk/SOI MOS Multi-gate MOS Post-Silicon 5 nm 65nm 45nm 32nm 22nm 16nm 12nm Technology: scaling, alternative structures and materials, post-silicon devices Design: billion transistors, gigahz operation K. ao (ASU) EEM216A / Fall 2008 D. Markovic / Slide 49 Transition to the Post-Silicon Age Organic (polymer) Nanotube Molecular Unpredictable, non-deterministic, unreliable, and very low SNR Strong demand of predictive modeling for robust system integration K. ao (ASU) EEM216A / Fall 2008 D. Markovic / Slide 50

26 Design of Nanoelectronics [TI] ??? arbon Nanotube FET [IBM] K. ao (ASU) EEM216A / Fall 2008 D. Markovic / Slide 51 Moore s Law hallenge Double transistors every two years Stay within the expected power trend Still deliver the expected performance Power-limited scaling regime Two key issues: Design complexity Power efficiency Looking at solutions to these challenges is what this course is all about! EEM216A / Fall 2008 D. Markovic / Slide 52