Design of Digital Circuits (SS16)

Transcription

1 Design of Digital Circuits (SS16) L (6 ECTS), BSc in CS, ETH Zurich Lecturers: Srdjan Capkun, D-INFK, ETH Zurich Frank K. Gürkaynak, D-ITET, ETH Zurich Labs: Der-Yeuan Yu Website: 1

2 In This Lecture Motivation for the lecture series Why should you care about Digital Circuits? The Art of Managing Complexity How can extremely complex systems be designed? Organization of the Course Information on the lectures Laboratory Exercises Exam How to get help when you are stuck 2

3 Introduction Design of Digital Circuits 2016 Srdjan Capkun Frank K. Gürkaynak Adapted from Digital Design and Computer Architecture, David Money Harris & Sarah L. Harris 2007 Elsevier 3

4 Background Microprocessors have revolutionized our world Cell phones, Internet, rapid advances in medicine, etc. The semiconductor industry has grown from $21 billion in 1985 to $345 billion in source: (semiconductor industry association)

5 The Purpose of This Course Is That You: Learn what s under the hood of a computer Learn the principles of digital design Learn to systematically debug increasingly complex systems Design and build a microprocessor 5

6 Goal Be able to understand a statement such as: The microarchitecture is a three-way superscalar, pipelined architecture. Three-way superscalar means that by using parallel processing techniques, the processor is able on average to decode, dispatch, and complete execution of (retire) three instructions per clock cycle. To handle this level of instruction throughput, the P6 processor family uses a decoupled, 12-stage superpipeline that supports out-of-order instruction execution. Taken from: ia-32-architectures-software-developer-manual pdf 6

7 What Is This Lecture About? Computers 7

8 What Is This Lecture About? What s inside? 8

9 What Is This Lecture About? 9

10 What Is This Lecture About? How can we build them? 10 Intel Westmere:

11 The Art of Managing Complexity Abstraction Discipline The Three -Y s Hierarchy Modularity Regularity 11

12 Abstraction Hiding details when they are not important Abstraction Levels Application Software Operating Systems Architecture Micro architecture Logic Digital Circuits Analog Circuits Devices Physics Examples Programs Device drivers Instructions, Registers Datapath, Controllers Adders, Memories AND gates, NOT gates Amplifiers Transistors, Diodes Electrons 12

13 This Course Carnegie Mellon Abstraction Hiding details when they are not important Abstraction Levels Application Software Operating Systems Architecture Micro architecture Logic Digital Circuits Analog Circuits Devices Physics Examples Programs Device drivers Instructions, Registers Datapath, Controllers Adders, Memories AND gates, NOT gates Amplifiers Transistors, Diodes Electrons 13

14 Discipline Intentionally restricting your design choices to that you can work more productively at higher abstraction levels 14

15 The Three -Y s Hierarchy A system is divided into modules of smaller complexity Modularity Having well defined functions and interfaces Regularity Encouraging uniformity, so modules can be easily re-used 15

16 The Digital Abstraction Most physical variables are continuous, for example: Voltage on a wire Frequency of an oscillation Position of a mass Instead of considering all values, the digital abstraction considers only a discrete subset of values 16

17 Digital Discipline: Binary Values Typically consider only two discrete values: 1 s and 0 s 1 = TRUE = HIGH 0 = FALSE = LOW 1 and 0 can be represented by specific voltage levels, rotating gears, fluid levels, etc. Digital circuits usually depend on specific voltage levels to represent 1 and 0 Bit: Binary digit 17

18 How Much Can We Do with 1s and 0s? How do you write 2016 if you only had 1s and 0s to write with? 18

19 How Much Can We Do with 1s and 0s? How do you write 2016 if you only had 1s and 0s to write with? How about: x We will learn how to calculate with only 1s and 0s. 19

20 From Real Problems to 1s and 0s Example Problem: You are going to the cafeteria for lunch You won t eat lunch (E) If it is not open (O) or If they only serve cabbage (C) 20

21 From Real Problems to 1s and 0s Example Problem: You are going to the cafeteria for lunch You won t eat lunch (E) If it is not open (O) or If they only serve cabbage (C) O C E We will learn how to formulate problems in truth tables

22 From Logic to Circuits Example: Alyssa P. Hacker has a snail that crawls down a paper tape with 1 s and 0 s on it. The snail smiles whenever the last four digits it has crawled over are

23 From Logic to Circuits Example: Alyssa P. Hacker has a snail that crawls down a paper tape with 1 s and 0 s on it. The snail smiles whenever the last four digits it has crawled over are A CLK S' 1 S 1 Y S' 0 Reset S 0 S 0 S 1 23

24 Verilog Will Help us Describe Circuits module divideby3fsm (input clk, input reset, output q); reg [1:0] state, nextstate; parameter S0 = 2'b00; parameter S1 = 2'b01; parameter S2 = 2'b10; (posedge clk, posedge reset) // state register if (reset) state <= S0; else state <= nextstate; (*) // next state logic case (state) S0: nextstate = S1; S1: nextstate = S2; S2: nextstate = S0; default: nextstate = S0; endcase assign q = (state == S0); // output logic endmodule 24

25 How Can We Add/Multiply Binary Numbers? A N B N ALU Y N 3 F 25

26 3 Zero Extend Carnegie Mellon How Can We Add/Multiply Binary Numbers? A N B N A N B N N N F 2 ALU N 3 F C out + [N-1] S Y N N N N 2 F 1:0 Y N 26

27 27 The Single-Cycle MIPS Architecture SignImm CLK A RD Instruction Memory + 4 A1 A3 WD3 RD2 RD1 WE3 A2 CLK Sign Extend Register File A RD Data Memory WD WE 0 1 PC 0 1 PC' Instr 25:21 20:16 15:0 5:0 SrcB 20:16 15:11 <<2 + ALUResult ReadData WriteData SrcA PCPlus4 PCBranch WriteReg 4:0 Result 31:26 RegDst Branch MemWrite MemtoReg ALUSrc RegWrite Op Funct Control Unit Zero PCSrc CLK ALUControl 2:0 ALU

28 Program Running on MIPS # MIPS assembly code # $s0 = array base address, $s1 = i # initialization code lui $s0, 0x23B8 # $s0 = 0x23B80000 ori $s0, $s0, 0xF000 # $s0 = 0x23B8F000 addi $s1, $0, 0 # i = 0 addi $t2, $0, 1000 # $t2 = 1000 loop: slt $t0, $s1, $t2 # i < 1000? beq $t0, $0, done # if not then done sll $t0, $s1, 2 # $t0 = i * 4 (byte offset) add $t0, $t0, $s0 # address of array[i] lw $t1, 0($t0) # $t1 = array[i] sll $t1, $t1, 3 # $t1 = array[i] * 8 sw $t1, 0($t0) # array[i] = array[i] * 8 addi $s1, $s1, 1 # i = i + 1 j loop # repeat done: 28

29 C to Machine Code Start writing program in a high-level language Compiler translates this into simple instructions that the processor will understand Assembler translates this into 1s and 0s that will control the processor 29

30 This Course Carnegie Mellon Abstraction Hiding details when they are not important Abstraction Levels Application Software Operating Systems Architecture Micro architecture Logic Digital Circuits Analog Circuits Devices Physics Examples Programs Device drivers Instructions, Registers Datapath, Controllers Adders, Memories AND gates, NOT gates Amplifiers Transistors, Diodes Electrons 30

31 In This Lecture Motivation for the lecture series Why should you care about Digital Circuits? The Art of Managing Complexity How can extremely complex systems be designed? Organization of the Course Information on the lectures Laboratory Exercises Exam How to get help when you are stuck 31

32 Schedule Lectures: Thursday, Friday, 10:00-12:00, ETH HG E7 09:00-10:00, ETH ML D28 No lectures on: 25 th, 31 st of March, 1 st of April (Easter) 5 th of May (Ascension) 3 rd of June (Last Day of School) Lab exercises: Will start in the third week of the semester (8 th of March) 10 lab sessions 2 hours each Lab sessions on Tuesday, Wednesday, Thursday and Friday In HG E 26.1 and HG E

33 Changes to the Lecture This Year Record number of students, changes to labs: In previous years all groups had one board. This year, we may not have enough boards, we will make them available for exercises. We will have some boards available for interested students Even more assistants for the laboratory exercises 6 assistants for every lab session One more session (Tuesday) Lectures (mostly) in German for technical problems Read by all TAs and the lecturers Quick help at all (well, almost all) times 33

34 Course Book Literature: Digital Design and Computer Architecture, David Harris and Sarah Harris ISBN-10: The course closely follows this book: (first edition) (second edition) PDFs for download from ETH or with ETH VPN from home 34

35 Content The story of 1s/0s (ch1) Logic Design (ch2-3) Verilog (ch4) Digital Building Blocks (ch5) Assembly (ch6) Microarchitecture (ch7) Memory Systems (ch8) The older (2007) edition of the book is more aligned to the lecture 35

36 Laboratory Exercises Goal: By the end of the lecture (with a little help) design your own processor and make it work! Understand how processors are built Get an insight of how everything comes together This is an ambitious goal, so some of the exercises will be challenging 36

37 Laboratory Exercises Every group will work using an FPGA* board We will have some boards available to take home and experiment on your own if you want We will work in groups of two You will be able to enroll yourself electronically Four sessions per week Tuesday 08:15-10:00 Wednesday 13:15-15:00 Thursday 15:15-17:00 Friday 13:15-15:00 37 * Field Programmable Gate Array: a generic system that can be programmed to perform any digital function

38 Laboratory Exercise Topics Drawing Schematics Programming FPGAs Using Verilog Understanding Finite State Machines Developing your Arithmetic Logic Unit Writing MIPS assembly programs Implementing a single-cycle MIPS architecture 38

39 Laboratory Exercises will be Graded Laboratory exercises will account for 25 out of 100 points of your final grade You will be required to demonstrate your implementation Hand in a short report within 1 week of finishing every lab Only one report per group The report will be graded within the following week Each lab is 2.5 points Repeating students can choose: Take last years lab grade and not follow them this year Follow the lab exercises and get a new grade Decision must be made during enrolling in lab groups. No change afterwards! 39

40 Laboratory Exercises are Supervised There will be 2 hour supervised laboratory sessions Assistants will be there to answer your questions, and evaluate your results You can also work on your own, and come to present your results during the lab sessions You just need to show your results to an assistant during lab hours 40

41 Alternatives for Using the Software Come during laboratory hours and use the labs no need for setup, the computers are already pre-installed with what you need Install the software on your computer manually (approx. 10GB) Installation instructions: 41

42 About the Software Xilinx ISE Synthesis tool and environment (Verilog circuits) Professional software used in industry Not designed for education Can be a bit tough in the beginning But you learn the real thing So: Attend the lab sessions 42

43 Examination 90 minute exam within the exam period Scheduled by the school, we have no influence on the exam time. 6 to 8 questions, related to the lectures and labs Everything covered in the lectures can be part of the exam Six pages of hand-written notes allowed Accounts for 75 out 100 points of the final grade 25 points will come from the exercises Previous exams available through VIS 43

44 If You Need Help Write an to: All lecturers and assistants will receive this Write directly to: Frank Gürkaynak: Srdjan Capkun: 44

45 Further Information Lecture web page Any questions? 45