An ASCII data format, used to describe a standard cell library

Transcription

1 Advanced VLSI Design Standard Cell Library/ CMPE 641 An ASCII data format, used to describe a standard cell library Includes the design rules for routing and the Abstract of the cells, no information about the internal netlist of the cells A LEF file contains the following sections: Technology: layer, design rules, via definitions, metal capacitance Site: Site extension Macros: cell descriptions, cell dimensions, layout of pins and blockages, capacitances. The technology is described by the Layer and Via statements. To each layer the following attributes may be associated: type: Layer type can be routing, cut (contact), masterslice (poly, active), overlap. width/pitch/spacing rules direction resistance and capacitance per unit square antenna Factor 1

2 Advanced VLSI Design Standard Cell Library/ CMPE 641 Layers are defined in process order from bottom to top poly masterslice cc cut metal1 routing via cut metal2 routing via2 cut metal3 routing Cut Layer definition LAYER layername TYPE CUT; SPACING Specifies the minimum spacing allowed between via cuts on the same net or different nets. This value can be overridden by the SAMENET SPACING statement (we are going to use this statement later) END layername 2

3 Advanced VLSI Design Standard Cell Library/ CMPE 641 Implant Layer definition LAYER layername TYPE IMPLANT ; SPACING minspacing END layername Defines implant layers in the design. Each layer is defined by assigning it a name and simple spacing and width rules. These spacing and width rules only affect the legal cell placements. These rules interact with the library methodology, detailed placement, and filler cell support. Masterslice or Overlap Layer definition LAYER layername TYPE {MASTERSLICE OVERLAP} ; Defines masterslice (nonrouting) or overlap layers in the design. Masterslice layers are typically polysilicon layers and are only needed if the cell MACROs have pins on the polysilicon layer. 3

4 Advanced VLSI Design Standard Cell Library/ CMPE 641 Routing Layer definition LAYER layername TYPE ROUTING ; DIRECTION {HORIZONTAL VERTICAL} ; PITCH distance; WIDTH defwidth; OFFSET distance ; SPACING minspacing; RESISTANCE RPERSQ value ; Specifies the resistance for a square of wire, in ohms per square. The resistance of a wire can be defined as RPERSQU x wire length/wire width CAPACITANCE CPERSQDIST value ; Specifies the capacitance for each square unit, in picofarads per square micron. This is used to model wire-to-ground capacitance. 4

5 Advanced VLSI Design Standard Cell Library/ CMPE 641 Manufacturing Grid MANUFACTURINGGRID value ; Defines the manufacturing grid for the design. The manufacturing grid is used for geometry alignment. When specified, shapes and cells are placed in locations that snap to the manufacturing grid. Via VIA vianame DEFAULT TOPOFSTACKONLY FOREIGN foreigncellname [pt [orient]] ; RESISTANCE value ; {LAYER layername ; {RECT pt pt ;}...}... END vianame Defines vias for usage by signal routers. Default vias have exactly three layers used: a cut layer, and two layers that touch the cut layer (routing or masterslice). The cut layer rectangle must be between the two routing or masterslice layer rectangles. 5

6 Advanced VLSI Design Standard Cell Library/ CMPE 641 Via Rule Generate VIARULE viarulename GENERATE LAYER routinglayername ; { DIRECTION {HORIZONTAL VERTICAL} ; OVERHANG overhang ; METALOVERHANG metaloverhang ; ENCLOSURE overhang1 overhang2 ;} LAYER routinglayername ; { DIRECTION {HORIZONTAL VERTICAL} ; OVERHANG overhang ; METALOVERHANG metaloverhang ; ENCLOSURE overhang1 overhang2 ;} LAYER cutlayername ; RECT pt pt ; SPACING xspacing BY yspacing ; RESISTANCE resistancepercut ; END viarulename Defines formulas for generating via arrays. Use the VIARULE GENERATE statement to cover special wiring that is not explicitly defined in the VIARULE statement. 6

7 Advanced VLSI Design Standard Cell Library/ CMPE 641 Same-Net Spacing SPACING SAMENET layername layername minspace [STACK] ;... END SPACING Defines the same-net spacing rules. Same-net spacing rules determine minimum spacing between geometries in the same net and are only required if same-net spacing is smaller than different-net spacing, or if vias on different layers have special stacking rules. Thesespecifications are used for design rule checking by the routing and verification tools. Spacing is the edge-to-edge separation, both orthogonal and diagonal. Site SITE sitename CLASS {PAD CORE} ; [SYMMETRY {X Y R90}... ;] (will discuss this later in macro definition) SIZE width BY height ; END sitename 7

8 Advanced VLSI Design Standard Cell Library/ CMPE 641 Macro MACRO macroname [CLASS { COVER [BUMP] RING BLOCK [BLACKBOX] PAD [INPUT OUTPUT INOUT POWER SPACER AREAIO] CORE [FEEDTHRU TIEHIGH TIELOW SPACER ANTENNACELL] ENDCAP {PRE POST TOPLEFT TOPRIGHT BOTTOMLEFT BOTTOMRIGHT} } ;] [SOURCE {USER BLOCK} ;] [FOREIGN foreigncellname [pt [orient]] ;]... [ORIGIN pt ;] [SIZE width BY height ;] [SYMMETRY {X Y R90}... ;] [SITE sitename ;] [PIN statement]... [OBS statement]... 8

9 Advanced VLSI Design Standard Cell Library/ CMPE 641 Defining Symmetry 9

10 Advanced VLSI Design Standard Cell Library/ CMPE 641 Macro Pin Statement PIN pinname FOREIGN foreignpinname [STRUCTURE [pt [orient] ] ] ; [DIRECTION {INPUT OUTPUT [TRISTATE] INOUT FEEDTHRU} ;] [USE { SIGNAL ANALOG POWER GROUND CLOCK } ;] [SHAPE {ABUTMENT RING FEEDTHRU} ;] [MUSTJOIN pinname ;] {PORT [CLASS {NONE CORE} ;] {layergeometries}... END}... END pinname] Macro Obstruction Statement OBS { LAYER layername [SPACING minspacing DESIGNRULEWIDTH value] ; RECT pt pt ; POLYGON pt pt pt pt... ; END 10