Shanghai R&D Vacancies August 2014 PV, PE, Intern

Transcription

1 RD Shanghai R&D Vacancies August 2014 PV, PE, Intern 1. Lead Software Engineer- Routing (Req#: 9528) Responsible for development and maintenance of signal routing in EDI platform (NanoRoute). Implementation for complicated advanced node design rule support in NanoRouter. New feature support and performance improvement in NanoRoute. MS above in CS/EE or similar level of expertise with 3+ years of working experience. Be skilled in C/C++ programming on Linux platform. Good team player with strong written and verbal communication skills. Familiar with the routing algorithm (maze routing) is preferred. Familiar with LEF/DEF is preferred. 2. Principal Software Engineer (Req#: 9143) This position is for a R&D engineer to assist in development of detailed route in flipchip design. The candidate will be responsible for designing, developing, troubleshooting and debugging software programs of routing flow and related algorithms. The candidates should have strong software programming skill with C/C++ on Linux/Unix platform. Strong desires to learn and explore new technologies and is able to demonstrate good analysis and problem solving skills EDA software development experience or IC design knowledge, especially in backend and flipchip design. Know basic routing algorithms. Good English communication skill, both oral and written. 3. Lead Software Engineer- Optimization(Req#: 9631) Work on EDI IPO function on CCR fixing, memory and performance profiling as well as new enhancements

2 Logic synthesis background MS/PHD from computer science, EE, math or related Multi-thread programming background Timing background Physical placement background or clock tree synthesis background Very solid at C programming Good English communication skill 4. Software Engineer for EM analysis Develop the electro-migration analysis tool including coding, testing, product maintain, flow and algorithm improvement etc. MS or PhD in EE/CS/Math/Physics Excellent programming skills (C/C++, script) Good written and spoken English Good communication skills and be able to work with remote team Any of the following background is preferred: Electro-migration analysis /Power analysis/ Delay calculation/timing analysis etc. PV 1. Product Validation Engineer II (Req#: 8814) Work in Encounter NanoRoute Product Validation team. The responsibilities include: Assist in Cadence EDI flow developement and validation Validate and maintain comprehensive NanoRoute unit and flow test cases for Encounter Digital Impelementation System. Develope testsuites of the new features of Cadence's EDI router. CS/EE BS degree with 3+ years or MS degree with 1+ year work experience Digital IC design knowledge is necessary, physical verification (DRC/LVS) and layout knowledge is plus 2. Product Validation Engineer II (for GPS) (Req#: 8910)

3 This engineer will work in Encounter GPS (Global Phsyscal Synthesis) product validation team. The responsibilities include: Assist in Cadence EDI developement and validation Validate and maintain comprehensive GPS unit and flow test cases for Encounter Digital Impelementation System. Develope testsuites of the new features of EDI GPS function MS of EE/CS Digital IC design knowledge is necessary, statistic timing analysis knowledge is a strong plus 3. Lead Product Validation Engineer--STA (Req#: 9336) Cadence ICD Product Validation Analysis Team mainly focus on STA and Low Power related area in digital design backend flow. This position is responsible for developing, applying and improving quality standard for Cadence Lower Power flow and Encounter common timing engine. The candidate needs to test Low Power Solution and timing analysis result in common and special usage flows. Detailed Responsibility: Identify Low Power solution and timing sign-off challenges in complex SOC designs and advacned process nodes Proactively provide Low Power & STA & Sign-off development suggestions to R&D. Build up Lower Power & STA & Sign-Off expertise and deliver support to field team and customers whenever needed. Required to acquire expertise and ownership over existing product components as well as develop brand new product features. Project leader on important Low Power or STA features. Bachelor with 6 years related experience or Master with 4 years related experience in design house, FAB or EDA company. Rich experience in IC design flow (front-end or back-end). Experience in STA and SI analyis, or experience in Low Power flow, knowledge in parasitic extraction and signoff is a strong plus. Good Unix System knowledge and script skill of TCL/TK/CSH/PERL. Excellent capability of self-learning, problem solving skills; Being proactive and self-motivated;

4 Strong leadership; Good written English and oral English is a strong plus 4. Product Validation Engineer II (STA) (Req#: 9587,9588 & 9590) Responsible for developing, applying and improving quality standard for Encounter common timing engine. Help identifying new design and timing sign-off challenges in complex SOC designs and advanced process nodes, proactively provide STA & Sign-off development suggestions to R&D. Build up STA & Sign-Off expertise and deliver support to field team and customers whenever needed. Required to acquire expertise and ownership over existing product components as well as develop brand new product features. MS with experience in IC design flow (front-end or back-end). Knowledge in STA and SI analysis are preferable, knowledge in parasitic extraction and process variation effects (AOCV, SOCV) is a strong plus. Unix System knowledge, vi/tcl/tk/csh will be plus. Excellent capability of self-learning, problem solving skills; being proactive and selfmotivated, being a good team-player. Good communication skills in both Chinese and English. PE 1. Product Engineer II (Req#: 9234) Responsibility is designing, developing, troubleshooting and debugging software programs on Unix/Linux platforms. Will be involved in developing software tools for advanced chip design platforms. The responsibilities also include engaging with customers in understanding their ASIC design requirements for nano-technology process nodes and assisting them in adopting Cadence design platform and helping them in performing successful tapeouts of their System-on-chip designs using the same. The job will also involves presenting and demonstrating relevant Cadence technologies and carrying out product evaluations, workshops, trainings and competitive replacement campaigns

5 The candidates should have strong in-depth P&R design experience in COT or ASIC area. Experience and ability to get solutions in Floor plan, Power Planning/Analysis, CTS, timing optimization/analysis, signal integrity and DFM issues (DRC & Antenna) is a MUST. Strong interest and understanding of design methodologies are required. Need to have good knowledge on VDSM (40nm and below) processes issues. Good verbal and written presentation are must. Hands-on Cadence Encounter experience is a big plus. Minimum master degrees in EE or CS. Intern 1. Product Validation Intern (Req#: 9601) This intern will work in EDI Block Implementation PV team. The responsibilities include: Assist in Cadence CCOPT product development and validation Validate and maintain CCOPT unit and flow test cases for Encounter Digital Implementation System. Develop test suites of the new features of CCOPT areas MS or excellent undergraduate Digital IC design knowledge is necessary; statistic timing analysis knowledge is a strong plus Commitment to work as intern for at least 6 months