Engineer-to-Engineer Note

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1 Engineer-to-Engineer Note EE-234 Technicl notes on using Anlog Devices DSPs, processors nd development tools Contct our technicl support t dsp.support@nlog.com nd t dsptools.support@nlog.com Or visit our on-line resources nd Interfcing T1/E1 Trnsceivers/Frmers to Blckfin Processors vi the Seril Port Contributed by K. Unterkofler nd T. Luksik Rev 1 My 11, 2004 Introduction This EE-Note describes how to interfce Blckfin processors to stndrd T1 or E1 encoded signls. The proposed templte ssumes tht Blckfin processor is functionlly locted between two T1/E1 strems to perform the required processing, such s line echo cnceling. However, the Blckfin processor cn be dpted esily to other functionl rchitectures. As shown in this EE-Note, most stndrd bckplne PCM dt strems interfce directly to the processor s seril port(s), without ny externl hrdwre. This document provides schemtics, lyout suggestions, nd softwre frmework for receiving, processing, nd trnsmitting PCM strems between two T1/E1 trnsceivers/ frmers. The chosen frming device is the PMC-Sierr PM4351 COMET. The PCM strems re connected to one of the processor s synchronous seril ports (SPORTs), which cn hndle two input strems nd two output strems. The COMET is configured vi the processor s synchronous memory interfce in the externl bus interfce unit (EBIU). The schemtics re intended to be for dughterbord tht plugs into n EZ-KIT Lite evlution system vilble from Anlog Devices, Inc. The ppliction ws implemented on nd is described herein for the ADSP-BF533 processor [1], [2]. Though it is possible to pply this sme bord to the ADSP-BF561 EZ-KIT Lite evlution system with only minor chnges, considering tht this device incorportes two cores nd two SPORTs, it mkes more sense to extend the bord to four COMET devices nd to llow it to hndle twice the number of processed chnnels [3].! The bord ws lso designed to interfce lso to ADSP-BF535 processor, lthough it requires more substntil hrdwre chnges, such s using two SPORTs insted of the one needed for the ADSP-BF533. The schemtics refer to the the required chnges. This entils significnt softwre which re beyond the scope of this EE-Note. The softwre frmework is written in C entirely. All references to execution times re tken from this code exmple. System Architecture Figure 1 shows block digrm of typicl ppliction. The bord is designed to plug into n existing T1/E1 connection vi two RJ48C connectors. This leds to two strems (strem 1 nd strem 2), both crrying incoming nd outgoing dt (R IN, R OUT, S IN, nd S OUT ). In the most bsic mode of opertion (pss-through), R IN nd S IN re copied unltered to R OUT nd S OUT, respectively, such tht the whole resembles the originl single T1/E1 connection. Copyright 2004, Anlog Devices, Inc. All rights reserved. Anlog Devices ssumes no responsibility for customer product design or the use or ppliction of customers products or for ny infringements of ptents or rights of others which my result from Anlog Devices ssistnce. All trdemrks nd logos re property of their respective holders. Informtion furnished by Anlog Devices pplictions nd development tools engineers is believed to be ccurte nd relible, however no responsibility is ssumed by Anlog Devices regrding technicl ccurcy nd topiclity of the content provided in Anlog Devices Engineer-to-Engineer Notes.

2 T1/E1 Strem 1 T1/E1 Interfce Bord T1/E1 Strem 2 Rin Sout Frming nd processing Rout Sin RS232 to Host Figure 1. System overview The softwre lso provides prser-bsed UART interfce to generic host processor for setting operting modes nd prmeters nd controlling the Blckfin processor nd the COMET frming device. Figure 2 provides detiled view of the interfce. The signls from the two RJ48C connectors re conditioned nd isolted from the digitl domin by trnsformers. Also provided re over-voltge protection diodes. The COMET frmers (PM4351) re configured to generte seril inputs in formt complint with the SPORT s multichnnel mode from the R IN nd S IN strems, nd to generte the R OUT nd S OUT strems from the SPORT s seril output dt. The two COMET frmer chips re connected to the Blckfin processor vi the Externl Bus Interfce Unit (EBIU) nd re configured vi this interfce. T1/E1 Dt Formts T1/E1 connections re well-known nd widely dopted stndrd. For the purpose of this EE- Note, it is sufficient to sy tht T1 lines encode 24 chnnels of 8-bit dt plus one frming bit (totling 193 bits) into MHz crrier wve. Similrly, E1 lines encode 32 chnnels of 8-bit dt (totling 256 bits) into MHz crrier. In both cses, this corresponds to new smple of ech chnnel every 125 µs. The 8-bit dt is obtined from liner, 14- or 13-bit dt smples by compression ccording to -lw or µ-lw, respectively. In ddition to the dt (sometimes referred to s the pylod), T1/E1 strems contin signling bits ccording to vriety of communiction stndrds. This EE-Note does not go into the detils of these stndrds, since the COMET devices functionlity is to extrct the pylod from the incoming T1/E1 strems nd to encode vlid T1/E1 outgoing strem from the pylod from the DSP, ccording to the selected stndrd. Thus, if the COMET devices re set up correctly, the processor will see the pylod only nd never hve to hndle the signling bits. If errors occur, the COMET cn be set up to generte n interrupt for the DSP s well. For more detils, refer to [4], [5] nd [7]. Interfcing T1/E1 Trnsceivers/Frmers to Blckfin Processors vi the Seril Port (EE-234) Pge 2 of 13

3 Rin Sout RJ48C Line Interfce Protection & Isoltion RS232 UART DSP EZ-KIT Lite vi Expnsion Connectors Line Interfce Protection & Isoltion RJ48C Rout Sin CLK 2.048MHz COMET1 PM4351 EBIU SPORT COMET2 PM4351 PCM dt strems Figure 2. T1/E1 Interfce Crd Block Digrm The incoming strems (R IN nd S IN ) re thus converted (mpped) into PCM dt strem, sometimes referred to s bckplne. Agin, there re vriety of stndrds, but they consist of signl contining the dt bits for ech chnnel nd, for T1 lines, the frming bit, synchronous to (T1) or MHz (E1) clock. This block of dt is clled frme. The beginning of frme is signled by seprte signl clled frme sync. For T1, the COMET lso provides the option of mpping the 24 chnnels into MHz bckplne, such tht chnnels contin dummy dt, which the processor cn then ignore. This offers the dvntge tht both T1 nd E1 settings use the sme clock, thus switching between the two formts requires only simple softwre chnge, rther thn switching between two clock sources. For the outgoing strems (R OUT nd S OUT ), similr considertions pply. The bckplne signls consist of 32 chnnels of 8-bit dt for n E1 line. Similrly, for T1 line, the COMET simply ignores chnnels Figure 3 grphiclly shows the bckplne formts. Since ech SPORT hs two trnsmit lines nd two receive lines, the ADSP-BF561 cn be used to hndle ll four PCM strems. The clock nd frme sync re shred so tht the dt flows re synchronized t ll times. With its bility to independently select driving nd smpling edges for the receiver nd the trnsmitter, clock nd frme sync, nd dely between frme sync nd first bit of the dt strems, the ADSP-BF561 cn be dpted to virtully ll common bckplne formts. Figure 3 shows the formt used in this ppliction. For the PCM dt to be vilble for processing, it must be trnsferred into the processor s memory. Similrly, outgoing dt hs to be trnsferred from memory to the SPORT. This is done vi direct memory ccess (DMA) chnnels. The so clled 2D-DMA cpbilities llow for rerrnging smples in flexible wys, s is shown in Figure 4. Incoming smples re stored in the mnner depicted in the figure s they rrive, tht is R IN [0], S IN [0], R IN [1], S IN [1], Interfcing T1/E1 Trnsceivers/Frmers to Blckfin Processors vi the Seril Port (EE-234) Pge 3 of 13

4 R IN [Number_of_chnnels-1], S IN [Number_of_chnnels-1] for frme 0, nd similrly for the other frmes. Note tht the two receive lines (R IN nd S IN ) re re-orgnized s they come in to the SPORT without ny intervention of the core. The ttched code exmple cquires block of Number_of_Smples frmes, set by defult to 40, such tht n interrupt occurs every (Number_of_Smples * 125) µs (5 ms for the provided exmple). The interrupt signls tht the cquired frmes re vilble for processing, but the DMA continues to cquire new frmes in different memory re. When this second block is cquired, nother interrupt is generted nd the DMA plces new frmes into the first memory re, overwriting the ones lredy there. This mechnism is sometimes referred to s double buffering nd llows the Blckfin processor to process hlf the incoming dt (the first Number_of_Smples frmes) while the other hlf is cquired. This is done in hrdwre, without ny code intervention, by using the descriptor chin mechnism provided by the DMA engines. Similr considertions pply for the trnsmitted strems, R OUT nd S OUT. For detils on DMA functionlity, refer to [2]. The lst step before processing the incoming dt is to convert the PCM dt into liner vlues. As previously mentioned, the incoming dt is compressed nd hs to be expnded using -lw or µ-lw. Once processed, the resulting output dt must be compressed to fit into the outgoing PCM dt strems. The SPORT does the expnding nd compressing (compnding) in hrdwre, which elimintes processing time needed by the processor. Figure 3. Bckplne signl formts Interfcing T1/E1 Trnsceivers/Frmers to Blckfin Processors vi the Seril Port (EE-234) Pge 4 of 13

5 Ordering represents incresing 16-bit word ddresses Frme [0] Frme [1] Frme [Number_of_Smples-1] Rin[0] Rin[1] Rin[Number_of_chnnels-1] Rin[0] Rin[1] Rin[Number_of_chnnels-1] Rin[0] Rin[1] Rin[Number_of_chnnels-1] Sin[0] Sin[1] Sin[Number_of_chnnels-1] Sin[0] Sin[1] Sin[Number_of_chnnels-1] Sin[0] Sin[1] Sin[Number_of_chnnels-1] Rin[0] Rin[1] Rin[Number_of_chnnels-1] Rin[0] Rin[1] Rin[Number_of_chnnels-1] Rin[0] Rin[1] Rin[Number_of_chnnels-1] Sin[0] Sin[1] Sin[Number_of_chnnels-1] Sin[0] Sin[1] Sin[Number_of_chnnels-1] Sin[0] Sin[1] Sin[Number_of_chnnels-1] Repet from beginning 1st Hlf 2nd Hlf Figure 4. PCM smples lloction in L1 Dt Memory see text on how 2D-DMA fills the buffers Note tht the hrdwre compnding does not gurntee bit ccurcy; thus, if n incoming smple is expnded nd then compressed gin, the result my differ from the originl by one bit. This my not be cceptble, depending on the ppliction. By defult, the provided exmples use softwre compnding, which provides bit ccurcy, but requires bout 75 µs or 65 µs of processing time, ech wy, for -lw or µ-lw, respectively, mesured for 40 frmes t core clock speed of 600 MHz. To put this in perspective, this is bout 3.0% (or 2.6%) of the overll vilble computtion time of 5 ms. The described double-buffer mechnism introduces n intrinsic dely. For instnce, considering single dt word tht enters R IN, it will be copied to R OUT in the next block of frmes, nd then trnsmitted with the block fter tht. Thus, the dely from R IN to R OUT is (2 * Number_of_Smples * 125) µs (10 ms for the provided exmple, but 250 µs in the best cse). Similrly, smples going into S IN will repper (unltered or in processed form) on S OUT with the sme dely. The minimum mount of dely is clerly dependent on how mny frmes the dopted processing lgorithm requires t ech itertion to produce the desired results. Reference Bord Design The design closely follows the reference design described in gret detil in [6]. In prticulr, the line interfce with its signl conditioning, overvoltge protection, nd isoltion hs not been modified. The nlog side of the COMET devices is connected to the line interfce in ccordnce with the reference design s well. The MHz clock is derived from n externl oscilltor device, which lso feeds the processor s SPORT clock. The frme sync is generted from the Blckfin processor. Since both COMET devices hve the sme externl clocks nd frme syncs, they re Interfcing T1/E1 Trnsceivers/Frmers to Blckfin Processors vi the Seril Port (EE-234) Pge 5 of 13

6 forced to synchronize ll four PCM strems. They come from, nd go to, the SPORT s primry nd secondry trnsmitter, nd primry nd secondry receiver, respectively. The COMET devices re configured vi 9-bit ddress bus nd n 8-bit dt bus. These buses re mpped onto the EBIU s externl buses. The devices re selected by the /AMS3 nd /AMS1 memory bnk select signls.! The! Be ddress decoding scheme dopted in this design is very simple. It cn be improved by using one memory bnk select signl only, nd decoding more ddress lines. This requires one or two logic gtes. creful when lying out the EBIU connection to the COMET devices. Although the interfce is tht of slow synchronous memory device, the EBIU s buses re shred with SDRAM devices, which cn operte t up to 133 MHz. If SDRAM ccesses re required (for exmple, when complex lgorithms must be executed), lyout of these buses becomes criticl. The reference design, which is configured s dughter-bord to the EZ-KIT Lite bord, buffers the EBIU buses nd uses flg pin (PF4) to optionlly disble the buffers outputs when ccess to the COMET devices is not needed. Softwre Frmework Figure 5 shows high-level flowchrt of the provided frmework. Becuse the code is modulr nd well commented, this EE-Note provides only brief outline. More importntly, this section gives n overview on the possible operting modes nd options tht re implemented. After the initiliztion of the hrdwre (Blckfin processor s PLL, SDRAM, synchronous memory controllers, SPORT, DMA nd exception hndler; COMET devices; nd the UART interfce), the min loop performs three bsic tsks: 1. Check whether messge hs been received from the UART host, nd tke the pproprite ction. 2. Check whether new block of received dt is redy for processing nd new block of outgoing dt is empty to hold new results (vi two semphores set by the DMA interrupt service routines). If it is not, repet the cycle bove, otherwise go to step Process the dt ccording to the content of globl nd per-chnnel configurtion vribles. Three modes re vilble:. Globl pss-through: for initil debugging, ll dt is pssed through unltered, nd, in cse of softwre compnding, not even expnded nd re-compressed. b. Globl Enble, Per-chnnel Enble for current chnnel is OFF: dt for tht prticulr chnnel is pssed through unltered; however, unlike the previous cse, the incoming dt is expnded, copied to the output buffer, nd then recompressed. Since it works on perchnnel bsis, this mode is intended to be used for individul pure-dt chnnels, s opposed to voice chnnels. c. Globl Enble, Per-chnnel Enble for current chnnel is ON: dt for tht prticulr chnnel (R IN nd S IN ) is fed s input to the desired lgorithm (such s line echo cnceller) nd the lgorithm plces its results into S OUT. In ddition, ech chnnel cn lso be scled individully before entering the lgorithm (seprte scling fctors for R IN nd S IN ) In ll cses, R OUT is copy of R IN. You cn switch between these three modes t run-time by setting the corresponding vribles from the UART host. The scling fctors nd the compnding lw cn be chnged t runtime vi this interfce s well. Although the bove modes nd settings re dynmic, mny settings must be determined t Interfcing T1/E1 Trnsceivers/Frmers to Blckfin Processors vi the Seril Port (EE-234) Pge 6 of 13

7 compile time. All of them re controlled by (un)commenting or ssigning vlues to #define cluses in one file system.h. The most importnt ones re:! CLKIN, CORECLK, SYSCLK, nd SPORT0CLK: set system frequencies (in Hz)! Number_of_Smples: number of frmes cquired for ech block! Number_of_Chnnels: Set to 32 for MHz bckplne; set to 24 for true T1 (1.544 MHz) bckplne! SOFTWARE_COMPANDING: if defined, enbled compnding in softwre, otherwise the SPORT s hrdwre compnding feture is enbled! COMPANDING_LAW (vilble only if hrdwre compnding is selected): sets the SPORT s compnding lw! T1_mp: defines settings for T1 (mpping 24 T1 chnnels onto MHz bckplne)! E1, T1: define settings for n E MHz or T MHz, respectively! E1 nd T1 COMET configurtion settings re not implemented t this time. If these configurtions re required, modify the or initilizecomet_t1_short_hul() initilizecomet_e1_75() functions in COMET_init.c ccording to the procedures in [4] nd [7].! Settings for bckplne clock source, frme sync source, nd driving nd smpling edge reltionships for COMET nd SPORT. Only needed if dpting to different bckplne timing stndrd thn wht is shown in Figure 3.! Assignments of Generl-Purpose Flgs for vrious functions. Flg 0 nd Flg 2 re used to reset the COMET devices nd generte interrupt requests, respectively.! DEVICE1, DEVICE2: Bse ddresses in externl synchronous memory of the two COMET devices. By defult, they re locted t the strt of bnk 3 nd bnk 1, respectively! STANDALONE: if this lbel is commented, the ppliction writes dignostic nd sttus informtion to the VisulDSP++ Output window.! DUMP_VARIABLES: sends messge with ddresses of importnt mode vribles over the UART terminl, used to control operting modes t runtime.! DEBUG_COMET: verifies every write to the COMET registers nd displys wrning if the red vlue does not mtch the originlly intended vlue. Used for debugging.! DEBUG_ALGORITHM: uses flg pins to show execution time of the lgorithm, etc. Used for debugging, see Flg Settings in system.h Interfcing T1/E1 Trnsceivers/Frmers to Blckfin Processors vi the Seril Port (EE-234) Pge 7 of 13

8 Min() ProcessDt() Set Exception Hndler Set System Frequencies SDRAM controller ASYNC memory controller Flg IO Reset COMET devices Initilize vribles Detect UART terminl nd set up connection Press (or on Terminl for AutoBud detection Clculte which hlf of dtbuffers cn be processed Copy Rin to Rout (Number_of_Smples * Number_of_chnnels) words Initilize COMET devices Initilize SPORT nd DMA Initilize Interrupts PASS through? No Strt Trnsfers Process Loop (Infinite) Expnd Rin nd Sin with -lw or u-lw Loop: For EACH chnnel (Number_of_Chnnel times) : Copy SIN to SOUT (Number_of_Smples * Number_of_chnnels) words Messge from Host? Voice Chnnel? Yes Yes Process the messge Input Scling Rin nd Sin Semphore: new Block of Smples? Semphore is set by DMA interrupt every Number_of_smples * 125usec Sout() = Algorithm(Rin, Sin) Output Scling Sout Copy expnded Sin to Sout (Number_of_Smples * Number_of_chnnels) words Yes Cler Semphore Compress Sout with -lw or u-lw ProcessDt() End Chnnel Loop return End Process Loop Figure 5. Flow Digrm of Min() routine nd Processing of PCM smples Interfcing T1/E1 Trnsceivers/Frmers to Blckfin Processors vi the Seril Port (EE-234) Pge 8 of 13

9 Memory Alloction Dt Cche The softwre frmework hs been structured knowing tht most lgorithms will work with reltively smll mounts of code but operte on lrge mounts of dt. Therefore, the code is ssumed to be smll enough to fit into L1 instruction memory thus, executing t the processor s core clock frequency. The softwre frmework enbles dt cching for eventul lrge dt buffers in externl SDRAM. This is simply done by the initil definition of the int cplb_ctrl control vrible in min.c. The dt cche orgniztion is done in the cplbtb533.s file nd excludes externl synchronous memory from being cched (such tht there re no cching effects on the COMETs configurtion nd sttus registers). The dt buffers for the incoming nd outgoing PCM dt strems re plced into (non-cched) L1 memory since they re modified by DMA trnsfers, which re independent of the cche system. In conclusion, the frmework plces instructions nd ll necessry dt into non-ccheble L1 memory nd sets up the upper hlf of L1 Dt Bnk A s cche buffer for dt plced in SDRAM. This pproch hs been tested on line echo cnceller lgorithm, where cching reduced the execution time for ech chnnel from roughly 1 ms to 100 µsec. Using the UART Host Port The UART port is used to interfce with host processor using esy-to-red string commnds. This llows the host to be n embedded microcontroller or PC with humn opertor. An interrupt-driven system is used to receive dt from the UART. Ech received chrcter is stored in temporry rry nd echoed bck to the UART s n cknowledge signl. The host must prevent buffer overruns bsed on this cknowledgment. As soon s the CR chrcter (crrige return) is received, the temporry chr rry is plced on queue of strings to be prsed. Tble 1 lists few of the generl commnds implemented in the prototype system. The READ_MEM nd WRITE_MEM commnds modify the processor s memory in generl, nd the control nd sttus vribles in prticulr. To crete system where new commnds cn esily be dded, two tools (Lex nd Ycc) were used to mke sense of the incoming string queue. Commnd Syntx COMET_READ_REG <bse ddr> <reg ddr> COMET_READ_REG <bse ddr> ALL COMET_WRITE_REG <bse ddr> <reg ddr> <vl> READ_MEM_8 <ddr> READ_MEM_16 <ddr> READ_MEM_32 <ddr> WRITE_MEM_8 <ddr> <vl> WRITE_MEM_16 <ddr> <vl> WRITE_MEM_32 <ddr> <vl> Purpose Red register from the COMET frmer Red ll registers from the COMET frmer Write register to the COMET frmer Red n 8-bit vlue from loction in Blckfin memory Red 16-bit vlue from loction in Blckfin memory Red 32-bit vlue from loction in Blckfin memory Write n 8-bit vlue to loction in Blckfin memory Write 16-bit vlue to loction in Blckfin memory Write 32-bit vlue to loction in Blckfin memory Tble 1. COMET nd DSP memory commnds Interfcing T1/E1 Trnsceivers/Frmers to Blckfin Processors vi the Seril Port (EE-234) Pge 9 of 13

10 Both tools tke configurtion file s input nd produce C code. Lex produces scnner tht tokenizes incoming strings, nd Ycc produces progrm tht prses lists of tokens to identify meningful ptterns (i.e., vlid commnds). The Lex/Ycc suite llows for utomtic filtering of incoming strings tht do not hve commnds ssocited with them. For generl informtion on Lex nd Ycc, refer to [8]. Lex nd Ycc ech hve distinct configurtion file. Below re excerpts of ech file tht show how to configure the commnd to red memorympped register in one of the COMET frmer chips. The syntx of this commnd is: COMET_READ_REG <bse ddr> <reg ddr> where <bse ddr> is the bse ddress of the COMET chip in the Blckfin nd <reg ddr> is the ddress of the MMR in the COMET memory spce Lex Configurtion File [lex_spec.txt] COMET_READ_REG { return COMET_READ_REG; // string COMET_READ_REG returns distinct token } {integer} { yylvl = toi(yytext); // yylvl is pssed to Ycc return INTEGER; // ny integer returns with this token } Ycc Configurtion File [ycc_gmr.txt] %token INTEGER %token COMET_READ_REG COMET_READ_REG INTEGER INTEGER { } unsigned chr temp; size = sprintf(str, "COMET_READ_REG 0x%x 0x%x;\n\r", $2, $3); YY_OUTPUT(str, size); // echo the commnd to cknowledge temp = COMET_redReg($2, $3); // pss the prmeters to function tht // ctully does the COMET ccess size = sprintf(str, "COMET_READ_REG (0x%x, 0x%x) -> 0x%x;\n\r", $2, $3, temp); YY_OUTPUT(str, size); // echo the output The GNU version of Lex nd Ycc were used in this system. Both Flex, the Lex lterntive, nd Bison, the Ycc lterntive, re prt of the Cygwin distribution ( The following commnd line cretes the Lex scnner nd Ycc prser. flex lex_spec.txt [cretes lex.yy.c] bison y d ycc_gmr.txt [cretes y.tb.c nd y.tb.h] The resulting C source nd heder files re incorported into the Blckfin VisulDSP++ project. Interfcing T1/E1 Trnsceivers/Frmers to Blckfin Processors vi the Seril Port (EE-234) Pge 10 of 13

11 Figure 6. Hyperterminl session Results Figure 6 shows screenshot of the implemented UART interfce protocol. Shown re the initil sttus messge with the ddresses of control vribles nd two write_mem commnds. Figure 7 shows grphicl visuliztion of the output dt in pss-through mode. Inputs re generted externlly (1 khz sine wves) on subset of the 24 T1 chnnels. R OUT is looped bck externlly to S IN, such tht ll four strems contin the sme dt, only delyed in time. Figure 8 shows n exmple of how the debugging flg pins (PF1 nd PF3) cn be used to show, for instnce, the execution time for the processing of ll chnnels, or ny other useful time in reltively strightforwrd wy. The exmple ws tken from n ppliction where the lgorithm ws line echo cnceller (128 ms til length). Ech of the 32 chnnels is processed, lthough chnnels re not used by T1 connection. This ws solely intended to demonstrte tht the processing power of the Blckfin processor is sufficient to do significnt mounts of clcultions on ll 32 chnnels, nd leving bout 27% of the totl time for other tsks, such s the UART interfce. Conclusions This EE-Note, long with schemtic drwings nd softwre frmework provides design ides for vriety of T1/E1 communiction lines. The min focus is to interfce the Blckfin processors seril ports to stndrd bckplne formts nd to show how to process the PCM dt. This is demonstrted on PCM strems from frmer device such s the PM4351. Interfcing T1/E1 Trnsceivers/Frmers to Blckfin Processors vi the Seril Port (EE-234) Pge 11 of 13

12 Figure 7. R OUT nd S OUT (chnnel 0) in pss-through mode (R IN is 1kHz sine-wve for chnnels 0,1 nd 2), S IN is looped bck externlly from R OUT. Figure 8. Execution time (signl PF1, trce 1) nd individul chnnel convergence indictor (signl PF3, trce 4) in the cse of line echo cnceller lgorithm. See RESULTS section for more detils Interfcing T1/E1 Trnsceivers/Frmers to Blckfin Processors vi the Seril Port (EE-234) Pge 12 of 13

13 References [1] ADSP-BF531/ADSP-BF532/ADSP-BF533 Blckfin Embedded Processor Dt Sheet. Rev 0, Mrch Anlog Devices, Inc. [2] ADSP-BF533 Blckfin Processor Hrdwre Reference Mnul. Revision 1.0, December Anlog Devices, Inc. [3] ADSP-BF561 Blckfin Processor Hrdwre Reference Mnul. Preliminry Revision 0.2, November Anlog Devices, Inc. [4] PM4351 COMET Combined E1/T1 Trnsceiver Dtsheet. Issue10, November PMC-Sierr, Inc. [5] PM4351 COMET Combined E1/T1/J1 Trnsceiver/Frmer Device Errt. Issue6, April PMC-Sierr, Inc. [6] PM4351 COMET Reference Design. Rev. 2.0, Issue1, November PMC-Sierr, Inc. [7] PM4351 COMET Progrmmer s Guide. Issue2, September PMC-Sierr, Inc. [8] Lex nd Ycc for Embedded Progrmmers. Embedded Systems Progrmming. Document History Revision Rev 1 My 11, 2004 by K. Unterkofler Description Initil Relese Interfcing T1/E1 Trnsceivers/Frmers to Blckfin Processors vi the Seril Port (EE-234) Pge 13 of 13