Scattering Mechanisms in Narrow Copper Lines
|
|
- Arline Booker
- 7 years ago
- Views:
Transcription
1 Scattering Mechanisms in Narrow Copper Lines G. B. Alers, J. Sukamto, S. Park, J. Blackburn, C. Chi, I. Kalinovski, W. Wu, R. Powell Novellus Systems 1
2 Purpose: Scattering Mechanisms in Copper Problem: Increased resistivity of copper in sub-100nm lines Procedure: Quantify scattering mechanisms in sub-100nm lines (1) Determine lower limit for copper resistivity in sub-100nm lines (2) Identify relative importance of each scattering mechanisms in copper (3) Prioritize critical process steps for reducing copper resistivity Goal: Critical process steps for controlling copper resistivity Line edge roughness, post-plate anneal, copper thickness, chemistry 2
3 Outstanding questions (1) What is the lower limit of copper resistivity in sub-100nm lines? (2) Does barrier interface scattering depend on material? (3) Can a thick copper overburden reduce grain boundary scattering? (4) Can a fast annealing chemistry reduce grain boundary scattering? 3
4 Experimental Outline Barrier interface scattering contribution Blanket Cu films with large grains and different barriers Resistivity vs. thickness ~ barrier interface scattering Fabrication of sub-100nm lines Minimize line edge roughness Large process window for barrier / seed / fill Impact of process on copper resistivity Anneal temperature Copper thickness Plating chemistry 4
5 Surface Scattering Contribution Small Grain Cu (800nm) + Seed (40nm) Alternate Barriers Copper Oxide Silicon Anneal 150C / 1hour Copper Oxide Silicon Large Grain Cu CMP: Cu remains in wafer center Sheet resistance 4 pt. probe Thickness XRF Oxide Silicon Oxide Silicon Resistivity vs. thickness for large grain copper Cu / barrier + Cu / oxide scattering only 5
6 Surface Scattering Component Resistivity Bulk Cu Blanket copper (annealed) Polished back to less than 100nm 100% Diffuse Scattering Ru WN ALD TaN PVD Ta 1-D model (p=0) Copper Thickness (nm) Large Grain Copper Barrier/seed 1µm Cu + Anneal Polish back to nm Thickness: XRF Resistance: sheet R Average over 8 wafers PVD Ta, WN, ALD TaN: 100% diffuse scattering Both top and bottom Ru Incomplete CMP (?) Model surface scattering with ρ = ρ 0 * (1+ /t), = (1-p)*λ Scattering for all barriers consistent with p=0 (diffuse scattering) 6
7 Narrow Line Fabrication: Requirements Minimum line edge roughness Issue: 193 photoresist = thin, rough line edges Solution: SiC hardmask + 248nm lithography Reduction in CD: 200nm lines to 50nm lines Issue: Facets with backfill of 75 90nm of PDL SiO 2 Solution: PVD + ECD with corner facets, remove at CMP Cross section determination Issue: SEM has large errors Solution: Matthiessen rule to determine area 7
8 Line Edge Roughness / 193nm lithography Alternative: 248nm lithography / TEOS Top View 193nm Litho / SiOCH 248nm litho / TEOS / Virtual Modified Image SiC hardmask Shrink Side View 140nm l/s Resist BARC Line edge roughness will be a larger fraction of final CD as features are backfilled. 193nm litho / SiOC: ~20nm line edge roughness 248nm litho / SiC hardmask / TEOS: < 10nm roughness 8
9 CD Reduction: Oxide Backfill + ECD Cu ECD Copper Oxide Backfill Underlying Trenches CMP Polish Back Thick backfill gives large facets at trench corner Larger process window for thin PVD barrier / seed Polish through backfill material for realistic features 9
10 Lines after ECD / CMP Low Aspect Ratio Structures Pt High Aspect Ratio Structures Pt Cross sectional area difficult to measure with SEM (large errors) Subtract out barrier area for copper resistivity 10
11 Matthiessen Law and Effective Line Width Avoid difficult FIB/SEM, improve statistics Resistance of copper line vs. temperature Electrical and Microstructural characterization of Narrow Cu Interconnects W. Wu, et al., IMEC. AMC, Cleave / SEM : 6.3 +/- 0.6 E-11 cm 2 Measure resistance at two temperatures, find two unknowns Area = α T L / R(T), Resistivity = R α T / R(T) Thickness from wide Cu lines with ρ = 1.8 µω -cm Matthiessen: 6.3 E-11 cm 2 11
12 Narrow Lines After Passivation Cu overburden has large impact Resistivity (µω-cm) Line Depth ~ 100nm Seed = 50nm = 50% of trench Annealing of seed is critical Line Width (nm) 2kA Overburden No anneal 2kA Overburden 400C / 30min anneal 8kA Overburden 150C / 1H anneal Thick overburden more effective than high T anneal 12
13 Partial Annealing of Seed Layer Partial anneal of blanket ECD Cu Less than 20% Resistance drop Small grain Cu seed layer visible Upper copper: Shorts out seed Seed Importance: Thin wires Seed large fraction of line 13
14 Impact of ECD Chemistry and Overburden Pure chemistry 300nm thick deposit 800nm thick deposit 130nm chemistry 300nm thick deposit 800nm thick deposit 130 Chemistry: Thick overburden required for full recrystallization Pure Chemistry Less dependent on overburden Higher Purity Cu Film faster RT anneal rate less GB scattering Fast annealing Cu film reduces need for thick overburden 14
15 Minimum Resistivity in Narrow Lines ρ (µohm-cm) nm 160nm All The Right Ingredients Pure chemistry 1.5µm of overburden, 40nm seed 300C / 90s anneal 160nm trench depth 2.5 : 1 aspect ratio at ECD Simple additive model ρ = ρ 0 * (1+ /t + /w ) obtained from blanket wafer data Only parameter: ρ 0 = Line Width (nm) ρ = 2.3 µohm-cm at 80nm, 2:1 AR Resistivity consistent with surface scattering only 15
16 Process Variations and Resistivity 3.5 Increased resistivity: Resistivity (µω-cm) Width(nm) All the right things High as plated AR (3:1) 150nm depth Thin Overburden ρ = 0.2 µω-cm Shallow depth (70nm) Thin Overburden ρ = 0.4 µω-cm Minimum resistivity: Thick overburden, low as plated AR 16
17 Cu Overburden Effect on Electromigration ln(cdf) Trench: 80nm wide 80nm deep 200nm Overburden 6x Difference 800nm Overburden PDL Oxide Cu Oxide Line Dimension: 80nm (W) x 80nm (D) 130nm generation chemistry E+03 1.E+04 1.E+05 Time to fail (s) 8kA Cu overburden shows 6X EM improvement over 2kA 17
18 Conclusions on Minimum Copper Resistivity Novellus structures designed to minimize resistivity Low effective aspect ratio Minimal edge roughness Wide margin for barrier / seed coverage and fill Lowest resistivity in narrow line Thick overburden Fast annealing chemistry Barrier material has small impact 18
19 Return to Outstanding Questions (1) What is the lower limit of copper resistivity in sub 100nm lines? Pure surface scattering = 2.3 µω-cm for 80nm x 160nm lines (2) Does barrier interface depend metal? PVD Ta(N), ALD Ta(N), ALD WN and Ru all have 100% diffuse scattering (3) Can a thick overburden (>1µm) reduce grain boundary scattering? Yes, provided optimum trench aspect ratio and profile (4) Can a fast annealing chemistry reduce grain boundary scattering? Yes, provided optimum trench aspect ratio and profile 19
DEVELOPMENTS & TRENDS IN FEOL MATERIALS FOR ADVANCED SEMICONDUCTOR DEVICES Michael Corbett mcorbett@linx-consulting.com Semicon Taiwan2015
DEVELOPMENTS & TRENDS IN FEOL MATERIALS FOR ADVANCED SEMICONDUCTOR DEVICES Michael Corbett mcorbett@linx-consulting.com Semicon Taiwan2015 LINX BACKGROUND Linx Consulting 1. We help our clients to succeed
More informationEvaluating Surface Roughness of Si Following Selected Lapping and Polishing Processes
Applications Laboratory Report 86 Evaluating Surface Roughness of Si Following Selected Processes Purpose polishing of samples is a common application and required for a variety of manufacturing and research
More informationIntroduction to VLSI Fabrication Technologies. Emanuele Baravelli
Introduction to VLSI Fabrication Technologies Emanuele Baravelli 27/09/2005 Organization Materials Used in VLSI Fabrication VLSI Fabrication Technologies Overview of Fabrication Methods Device simulation
More informationLecture 030 DSM CMOS Technology (3/24/10) Page 030-1
Lecture 030 DSM CMOS Technology (3/24/10) Page 030-1 LECTURE 030 - DEEP SUBMICRON (DSM) CMOS TECHNOLOGY LECTURE ORGANIZATION Outline Characteristics of a deep submicron CMOS technology Typical deep submicron
More informationSheet Resistance = R (L/W) = R N ------------------ L
Sheet Resistance Rewrite the resistance equation to separate (L / W), the length-to-width ratio... which is the number of squares N from R, the sheet resistance = (σ n t) - R L = -----------------------
More informationAdvanced VLSI Design CMOS Processing Technology
Isolation of transistors, i.e., their source and drains, from other transistors is needed to reduce electrical interactions between them. For technologies
More informationComparison study of FinFETs: SOI vs. Bulk Performance, Manufacturing Variability and Cost
Comparison study of FETs: SOI vs. Bulk Performance, Manufacturing Variability and Cost David Fried, IBM Thomas Hoffmann, IMEC Bich-Yen Nguyen, SOITEC Sri Samavedam, Freescale Horacio Mendez, SOI Industry
More informationImplementation Of High-k/Metal Gates In High-Volume Manufacturing
White Paper Implementation Of High-k/Metal Gates In High-Volume Manufacturing INTRODUCTION There have been significant breakthroughs in IC technology in the past decade. The upper interconnect layers of
More informationImproved Contact Formation for Large Area Solar Cells Using the Alternative Seed Layer (ASL) Process
Improved Contact Formation for Large Area Solar Cells Using the Alternative Seed Layer (ASL) Process Lynne Michaelson, Krystal Munoz, Jonathan C. Wang, Y.A. Xi*, Tom Tyson, Anthony Gallegos Technic Inc.,
More informationChapter 7-1. Definition of ALD
Chapter 7-1 Atomic Layer Deposition (ALD) Definition of ALD Brief history of ALD ALD process and equipments ALD applications 1 Definition of ALD ALD is a method of applying thin films to various substrates
More informationLecture 12. Physical Vapor Deposition: Evaporation and Sputtering Reading: Chapter 12. ECE 6450 - Dr. Alan Doolittle
Lecture 12 Physical Vapor Deposition: Evaporation and Sputtering Reading: Chapter 12 Evaporation and Sputtering (Metalization) Evaporation For all devices, there is a need to go from semiconductor to metal.
More informationResults Overview Wafer Edge Film Removal using Laser
Results Overview Wafer Edge Film Removal using Laser LEC- 300: Laser Edge Cleaning Process Apex Beam Top Beam Exhaust Flow Top Beam Scanning Top & Top Bevel Apex Beam Scanning Top Bevel, Apex, & Bo+om
More informationSputtered AlN Thin Films on Si and Electrodes for MEMS Resonators: Relationship Between Surface Quality Microstructure and Film Properties
Sputtered AlN Thin Films on and Electrodes for MEMS Resonators: Relationship Between Surface Quality Microstructure and Film Properties S. Mishin, D. R. Marx and B. Sylvia, Advanced Modular Sputtering,
More informationGraduate Student Presentations
Graduate Student Presentations Dang, Huong Chip packaging March 27 Call, Nathan Thin film transistors/ liquid crystal displays April 4 Feldman, Ari Optical computing April 11 Guerassio, Ian Self-assembly
More informationElectroplating with Photoresist Masks
Electroplating with Photoresist Masks Revised: 2014-01-17 Source: www.microchemicals.com/downloads/application_notes.html Electroplating - Basic Requirements on the Photoresist Electroplating with photoresist
More informationSemiconductor doping. Si solar Cell
Semiconductor doping Si solar Cell Two Levels of Masks - photoresist, alignment Etch and oxidation to isolate thermal oxide, deposited oxide, wet etching, dry etching, isolation schemes Doping - diffusion/ion
More informationEtching Etch Definitions Isotropic Etching: same in all direction Anisotropic Etching: direction sensitive Selectivity: etch rate difference between
Etching Etch Definitions Isotropic Etching: same in all direction Anisotropic Etching: direction sensitive Selectivity: etch rate difference between 2 materials Other layers below one being etch Masking
More informationChapter 11 PVD and Metallization
Chapter 11 PVD and Metallization 2006/5/23 1 Metallization Processes that deposit metal thin film on wafer surface. 2006/5/23 2 1 Metallization Definition Applications PVD vs. CVD Methods Vacuum Metals
More informationChapter 4 Indium Tin Oxide Films Deposited by d.c. Sputtering
Chapter 4 Indium Tin Oxide Films Deposited by d.c. Sputtering 4.1. Introduction Indium-tin-oxide (ITO) thin films are widely used in optoelectronics devices, flat panel display and electrochromic (EC)
More informationLapping and Polishing Basics
Lapping and Polishing Basics Applications Laboratory Report 54 Lapping and Polishing 1.0: Introduction Lapping and polishing is a process by which material is precisely removed from a workpiece (or specimen)
More informationOPTIMIZING OF THERMAL EVAPORATION PROCESS COMPARED TO MAGNETRON SPUTTERING FOR FABRICATION OF TITANIA QUANTUM DOTS
OPTIMIZING OF THERMAL EVAPORATION PROCESS COMPARED TO MAGNETRON SPUTTERING FOR FABRICATION OF TITANIA QUANTUM DOTS Vojtěch SVATOŠ 1, Jana DRBOHLAVOVÁ 1, Marian MÁRIK 1, Jan PEKÁREK 1, Jana CHOMOCKÁ 1,
More informationJ H Liao 1, Jianshe Tang 2,b, Ching Hwa Weng 2, Wei Lu 2, Han Wen Chen 2, John TC Lee 2
Solid State Phenomena Vol. 134 (2008) pp 359-362 Online available since 2007/Nov/20 at www.scientific.net (2008) Trans Tech Publications, Switzerland doi:10.4028/www.scientific.net/ssp.134.359 Metal Hard
More informationCoating Thickness and Composition Analysis by Micro-EDXRF
Application Note: XRF Coating Thickness and Composition Analysis by Micro-EDXRF www.edax.com Coating Thickness and Composition Analysis by Micro-EDXRF Introduction: The use of coatings in the modern manufacturing
More informationDependence of the thickness and composition of the HfO 2 /Si interface layer on annealing
Dependence of the thickness and composition of the HfO 2 /Si interface layer on annealing CINVESTAV-UNIDAD QUERETARO P.G. Mani-González and A. Herrera-Gomez gmani@qro.cinvestav.mx CINVESTAV 1 background
More informationConductivity of silicon can be changed several orders of magnitude by introducing impurity atoms in silicon crystal lattice.
CMOS Processing Technology Silicon: a semiconductor with resistance between that of conductor and an insulator. Conductivity of silicon can be changed several orders of magnitude by introducing impurity
More informationSilicon-On-Glass MEMS. Design. Handbook
Silicon-On-Glass MEMS Design Handbook A Process Module for a Multi-User Service Program A Michigan Nanofabrication Facility process at the University of Michigan March 2007 TABLE OF CONTENTS Chapter 1...
More informationISOTROPIC ETCHING OF THE SILICON NITRIDE AFTER FIELD OXIDATION.
ISOTROPIC ETCHING OF THE SILICON NITRIDE AFTER FIELD OXIDATION. A.J. BALLONI - Fundação Centro Tecnológico para Informática/ Instituto de Microeletrônica Laboratório de Litografia C.P. 6162 - Campinas/S.P.
More informationOptical Properties of Sputtered Tantalum Nitride Films Determined by Spectroscopic Ellipsometry
Optical Properties of Sputtered Tantalum Nitride Films Determined by Spectroscopic Ellipsometry Thomas Waechtler a, Bernd Gruska b, Sven Zimmermann a, Stefan E. Schulz a, Thomas Gessner a a Chemnitz University
More informationLezioni di Tecnologie e Materiali per l Elettronica
Lezioni di Tecnologie e Materiali per l Elettronica Danilo Manstretta danilo.manstretta@unipv.it microlab.unipv.it Outline Passive components Resistors Capacitors Inductors Printed circuits technologies
More informationMICROPOSIT LOL 1000 AND 2000 LIFTOFF LAYERS For Microlithography Applications
Technical Data Sheet MICROPOSIT LOL 1000 AND 2000 LIFTOFF LAYERS For Microlithography Applications Regional Product Availability Description Advantages North America Europe, Middle East and Africa Latin
More informationSupporting information
Supporting information Ultrafast room-temperature NH 3 sensing with positively-gated reduced graphene oxide field-effect transistors Ganhua Lu 1, Kehan Yu 1, Leonidas E. Ocola 2, and Junhong Chen 1 * 1
More informationLateral Resolution of EDX Analysis with Low Acceleration Voltage SEM
Original Paper Lateral Resolution of EDX Analysis with Low Acceleration Voltage SEM Satoshi Hashimoto 1, Tsuguo Sakurada 1, and Minoru Suzuki 2 1 JFE-Techno research corporation, 1-1 Minamiwatarida, Kawasaki,
More informationContamination. Cleanroom. Cleanroom for micro and nano fabrication. Particle Contamination and Yield in Semiconductors.
Fe Particles Metallic contaminants Organic contaminants Surface roughness Au Particles SiO 2 or other thin films Contamination Na Cu Photoresist Interconnect Metal N, P Damages: Oxide breakdown, metal
More informationThe atomic packing factor is defined as the ratio of sphere volume to the total unit cell volume, or APF = V S V C. = 2(sphere volume) = 2 = V C = 4R
3.5 Show that the atomic packing factor for BCC is 0.68. The atomic packing factor is defined as the ratio of sphere volume to the total unit cell volume, or APF = V S V C Since there are two spheres associated
More informationIntel Q3GM ES 32 nm CPU (from Core i5 660)
Intel Q3GM ES Structural Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor and electronics technology, please call
More informationUse of Carbon Nanoparticles for the Flexible Circuits Industry
Use of Carbon Nanoparticles for the Flexible Circuits Industry Ying (Judy) Ding, Rich Retallick MacDermid, Inc. Waterbury, Connecticut Abstract FPC (Flexible Printed Circuit) has been growing tremendously
More informationWafer Manufacturing. Reading Assignments: Plummer, Chap 3.1~3.4
Wafer Manufacturing Reading Assignments: Plummer, Chap 3.1~3.4 1 Periodic Table Roman letters give valence of the Elements 2 Why Silicon? First transistor, Shockley, Bardeen, Brattain1947 Made by Germanium
More informationWinbond W971GG6JB-25 1 Gbit DDR2 SDRAM 65 nm CMOS DRAM Process
Winbond W971GG6JB-25 1 Gbit DDR2 SDRAM 65 nm CMOS DRAM Process Process Review For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor
More informationSpecification for Electroless Nickel/ Electroless Palladium/ Immersion Gold (ENEPIG) Plating for Printed Circuit Boards
Specification for Electroless Nickel/ Electroless Palladium/ Immersion Gold (ENEPIG) Plating for Printed Circuit Boards Developed by the Plating Processes Subcommittee (4-14) of the Fabrication Processes
More informationAnodes and Misc Equipment
Anodes and Misc Equipment Application: Platinised Titanium Anodes Platinised titanium anodes are recommended for use in the following electrolytic processes:- Precious metal electroplating - e.g. Au, Pt,
More information3D NAND Technology Implications to Enterprise Storage Applications
3D NAND Technology Implications to Enterprise Storage Applications Jung H. Yoon Memory Technology IBM Systems Supply Chain Outline Memory Technology Scaling - Driving Forces Density trends & outlook Bit
More informationDemonstration of sub-4 nm nanoimprint lithography using a template fabricated by helium ion beam lithography
Demonstration of sub-4 nm nanoimprint lithography using a template fabricated by helium ion beam lithography Wen-Di Li*, Wei Wu** and R. Stanley Williams Hewlett-Packard Labs *Current address: University
More information1.Introduction. Introduction. Most of slides come from Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda.
.Introduction If the automobile had followed the same development cycle as the computer, a Rolls- Royce would today cost $00, get one million miles to the gallon and explode once a year Most of slides
More informationCOATED CARBIDE. TiN. Al 2 O 3
COATED CARBIDE GENERAL INFORMATION CVD = Chemical Vapour Deposition coated grades GC2015, GC2025, GC2135, GC235, GC3005, GC3015, GC3020, GC3025, GC3115, GC4015, GC4025, GC4035, S05F, and CD1810. PVD =
More informationSn-Cu Intermetallic Grain Morphology Related to Sn Layer Thickness
Journal of ELECTRONIC MATERIALS, Vol. 36, No. 11, 2007 DOI: 10.1007/s11664-007-0270-x Ó 2007 TMS Special Issue Paper -Cu Intermetallic Grain Morphology Related to Layer Thickness MIN-HSIEN LU 1 and KER-CHANG
More informationBasic Properties and Application Examples of PGS Graphite Sheet
Basic Properties and Application Examples of 1. Basic properties of Graphite sheet 2. Functions of Graphite sheet 3. Application Examples Presentation [Sales Liaison] Panasonic Electronic Devices Co.,
More informationINF4420. Outline. Layout and CMOS processing technology. CMOS Fabrication overview. Design rules. Layout of passive and active componets.
INF4420 Layout and CMOS processing technology Spring 2012 1 / 76 Outline CMOS Fabrication overview Design rules Layout of passive and active componets Packaging 2 / 76 Introduction As circuit designers
More informationDuPont Surfaces DUPONT TM CORIAN SOLID SURFACE 12mm GAUGE STANDARDIZATION
DuPont Surfaces DUPONT TM CORIAN SOLID SURFACE PRODUCT ADVISORY TABLE OF CONTENTS PAGE SECTION 1 A. Introduction 2 B. Bull-nose edge treatment 3 C. Ogee edge treatment on stacked edges 4 D. Coved Backsplashes
More informationEngine Bearing Materials
Engine Bearing Materials Dr. Dmitri Kopeliovich (Research & Development Manager) The durable operation of an engine bearing is achieved if its materials combine high strength (load capacity, wear resistance,
More informationTransition to 4 and 5 BB designs for Ni/Cu/Ag plated cells
6th Workshop on Metallization & nterconnection for Crystalline Silicon Solar Cells Transition to 4 and 5 BB designs for Ni/Cu/Ag plated cells Rena Technologies: Trina Solar: MacDermid Enthone: N.Bay, J.Burschik,
More informationWŝŽŶĞĞƌŝŶŐ > ĞdžƉĞƌŝĞŶĐĞ ƐŝŶĐĞ ϭϵϳϰ WŝĐŽƐƵŶ ^he > Ρ ZͲƐĞƌŝĞƐ > ƐLJƐƚĞŵƐ ƌŝěőŝŷő ƚśğ ŐĂƉ ďğƚǁğğŷ ƌğɛğăƌđś ĂŶĚ ƉƌŽĚƵĐƟŽŶ d, &hdhz K& d,/e &/>D /^, Z
The ALD Powerhouse Picosun Defining the future of ALD Picosun s history and background date back to the very beginning of the field of atomic layer deposition. ALD was invented in Finland in 1974 by Dr.
More informationNew 3-Dimensional AFM for CD Measurement and Sidewall Characterization
New 3-Dimensional AFM for CD Measurement and Sidewall Characterization ASTRACT Yueming Hua *, Cynthia uenviaje-coggins Park Systems Inc. 34 Olcott St. Santa Clara, CA 9554, USA Yong-ha Lee, Jung-min Lee,
More informationELEC 3908, Physical Electronics, Lecture 15. BJT Structure and Fabrication
ELEC 3908, Physical Electronics, Lecture 15 Lecture Outline Now move on to bipolar junction transistor (BJT) Strategy for next few lectures similar to diode: structure and processing, basic operation,
More informationWinbond W2E512/W27E257 EEPROM
Construction Analysis Winbond W2E512/W27E257 EEPROM Report Number: SCA 9703-533 Global Semiconductor Industry the Serving Since 1964 15022 N. 75th Street Scottsdale, AZ 85260-2476 Phone: 602-998-9780 Fax:
More informationDamage-free, All-dry Via Etch Resist and Residue Removal Processes
Damage-free, All-dry Via Etch Resist and Residue Removal Processes Nirmal Chaudhary Siemens Components East Fishkill, 1580 Route 52, Bldg. 630-1, Hopewell Junction, NY 12533 Tel: (914)892-9053, Fax: (914)892-9068
More informationNorth American Stainless
North American Stainless Long Products Stainless Steel Grade Sheet 2205 UNS S2205 EN 1.4462 2304 UNS S2304 EN 1.4362 INTRODUCTION Types 2205 and 2304 are duplex stainless steel grades with a microstructure,
More informationDevelopments in Photoluminescence Characterisation for Silicon PV
Developments in Photoluminescence Characterisation for Silicon PV School of Photovoltaic and Solar Energy Engineering Bernhard Mitchell 1, Thorsten Trupke 1,2, Jürgen W. Weber 2, Johannes Greulich 3, Matthias
More informationGrad Student Presentation Topics PHGN/CHEN/MLGN 435/535: Interdisciplinary Silicon Processing Laboratory
Grad Student Presentation Topics 1. Baranowski, Lauryn L. AFM nano-oxidation lithography 2. Braid, Jennifer L. Extreme UV lithography 3. Garlick, Jonathan P. 4. Lochner, Robert E. 5. Martinez, Aaron D.
More informationElectroplating aspects in 3D IC Technology
Electroplating aspects in 3D IC Technology Dr. A. Uhlig Atotech Deutschland GmbH Semiconductor R&D Atotech @ Sematech Workshop San Diego/Ca 2008-09-26 3D Advanced Packaging Miniaturization in size and
More informationh e l p s y o u C O N T R O L
contamination analysis for compound semiconductors ANALYTICAL SERVICES B u r i e d d e f e c t s, E v a n s A n a l y t i c a l g r o u p h e l p s y o u C O N T R O L C O N T A M I N A T I O N Contamination
More informationChapter Outline: Phase Transformations in Metals
Chapter Outline: Phase Transformations in Metals Heat Treatment (time and temperature) Microstructure Mechanical Properties Kinetics of phase transformations Multiphase Transformations Phase transformations
More informationDevelopment of High-Speed High-Precision Cooling Plate
Hironori Akiba Satoshi Fukuhara Ken-ichi Bandou Hidetoshi Fukuda As the thinning of semiconductor device progresses more remarkably than before, uniformity within silicon wafer comes to be strongly required
More informationPackage Trends for Mobile Device
Package Trends for Mobile Device On-package EMI Shield At CTEA Symposium Feb-10, 2015 Tatsuya Kawamura Marketing, Director TEL NEXX, Inc. Love Thinner Mobile? http://www.apple.com/ iphone is registered
More informationFollow up and checkpoints of cable properties
Follow up and checkpoints of cable properties Luc OBERLI 1 Outline Cable properties relevant for the field quality Follow up of the cable properties during the production Status and trend of the cable
More informationPhotolithography. Class: Figure 12.1. Various ways in which dust particles can interfere with photomask patterns.
Photolithography Figure 12.1. Various ways in which dust particles can interfere with photomask patterns. 19/11/2003 Ettore Vittone- Fisica dei Semiconduttori - Lectio XIII 16 Figure 12.2. Particle-size
More informationJournal bearings/sliding bearings
Journal bearings/sliding bearings Operating conditions: Advantages: - Vibration damping, impact damping, noise damping - not sensitive for vibrations, low operating noise level - dust tight (if lubricated
More informationNANOSTRUCTURED ZnO AND ZAO TRANSPARENT THIN FILMS BY SPUTTERING SURFACE CHARACTERIZATION
Rev.Adv.Mater.Sci. Nanostructured ZnO 10 and (2005) ZAO 335-340 transparent thin films by sputtering surface characterization 335 NANOSTRUCTURED ZnO AND ZAO TRANSPARENT THIN FILMS BY SPUTTERING SURFACE
More informationVOLUME AND SURFACE AREAS OF SOLIDS
VOLUME AND SURFACE AREAS OF SOLIDS Q.1. Find the total surface area and volume of a rectangular solid (cuboid) measuring 1 m by 50 cm by 0.5 m. 50 1 Ans. Length of cuboid l = 1 m, Breadth of cuboid, b
More informationThin Is In, But Not Too Thin!
Thin Is In, But Not Too Thin! K.V. Ravi Crystal Solar, Inc. Abstract The trade-off between thick (~170 microns) silicon-based PV and thin (a few microns) film non-silicon and amorphous silicon PV is addressed
More informationE F G. Overview of the activities. SAPIE ZA Università di Roma - Laboratorio di Fotonica Molecolare
SAPIE ZA Università di Roma Dipartimento di Energetica Laboratorio di Fotonica Molecolare Francesco Michelotti E-Mail: francesco.michelotti@uniroma1.it Tel: +39 06-49.91.65.62 Workshop Future Trends in
More informationAtomic Force Microscopy Observation and Characterization of a CD Stamper, Lycopodium Spores, and Step-Height Standard Diffraction Grating
Atomic Force Microscopy Observation and Characterization of a CD Stamper, Lycopodium Spores, and Step-Height Standard Diffraction Grating Michael McMearty and Frit Miot Special Thanks to Brendan Cross
More informationCoating Technology: Evaporation Vs Sputtering
Satisloh Italy S.r.l. Coating Technology: Evaporation Vs Sputtering Gianni Monaco, PhD R&D project manager, Satisloh Italy 04.04.2016 V1 The aim of this document is to provide basic technical information
More informationVLSI Fabrication Process
VLSI Fabrication Process Om prakash 5 th sem ASCT, Bhopal omprakashsony@gmail.com Manisha Kumari 5 th sem ASCT, Bhopal Manisha2686@gmail.com Abstract VLSI stands for "Very Large Scale Integration". This
More informationProblems in Welding of High Strength Aluminium Alloys
Singapore Welding Society Newsletter, September 1999 Problems in Welding of High Strength Aluminium Alloys Wei Zhou Nanyang Technological University, Singapore E-mail: WZhou@Cantab.Net Pure aluminium has
More informationLow-cost Printed Electronic Nose Gas Sensors for Distributed Environmental Monitoring
Low-cost Printed Electronic Nose Gas Sensors for Distributed Environmental Monitoring Vivek Subramanian Department of Electrical Engineering and Computer Sciences University of California, Berkeley RD83089901
More information2. Deposition process
Properties of optical thin films produced by reactive low voltage ion plating (RLVIP) Antje Hallbauer Thin Film Technology Institute of Ion Physics & Applied Physics University of Innsbruck Investigations
More informationTechnology Developments Towars Silicon Photonics Integration
Technology Developments Towars Silicon Photonics Integration Marco Romagnoli Advanced Technologies for Integrated Photonics, CNIT Venezia - November 23 th, 2012 Medium short reach interconnection Example:
More informationSolar Photovoltaic (PV) Cells
Solar Photovoltaic (PV) Cells A supplement topic to: Mi ti l S Micro-optical Sensors - A MEMS for electric power generation Science of Silicon PV Cells Scientific base for solar PV electric power generation
More informationMEMS Processes from CMP
MEMS Processes from CMP MUMPS from MEMSCAP Bulk Micromachining 1 / 19 MEMSCAP MUMPS processes PolyMUMPS SOIMUMPS MetalMUMPS 2 / 19 MEMSCAP Standard Processes PolyMUMPs 8 lithography levels, 7 physical
More informationComprehensive Analysis of Flexible Circuit Materials Performance in Frequency and Time Domains
Comprehensive Analysis of Flexible Circuit Materials Performance in Frequency and Time Domains Glenn Oliver and Deepu Nair DuPont Jim Nadolny Samtec, Inc. glenn.e.oliver@dupont.com jim.nadolny@samtec.com
More information1. PECVD in ORGANOSILICON FED PLASMAS
F. FRACASSI Department of Chemistry, University of Bari (Italy) Plasma Solution srl SURFACE MODIFICATION OF POLYMERS AND METALS WITH LOW TEMPERATURE PLASMA OUTLINE METAL TREATMENTS 1 low pressure PECVD
More informationSecondary Ion Mass Spectrometry
Secondary Ion Mass Spectrometry A PRACTICAL HANDBOOK FOR DEPTH PROFILING AND BULK IMPURITY ANALYSIS R. G. Wilson Hughes Research Laboratories Malibu, California F. A. Stevie AT&T Bell Laboratories Allentown,
More informationNatural Convection. Buoyancy force
Natural Convection In natural convection, the fluid motion occurs by natural means such as buoyancy. Since the fluid velocity associated with natural convection is relatively low, the heat transfer coefficient
More informationEXPERIMENTAL STUDY OF STRUCTURAL ZONE MODEL FOR COMPOSITE THIN FILMS IN MAGNETIC RECORDING MEDIA APPLICATION
EXPERIMENTAL STUDY OF STRUCTURAL ZONE MODEL FOR COMPOSITE THIN FILMS IN MAGNETIC RECORDING MEDIA APPLICATION Hua Yuan and David E. Laughlin Department of Materials Science and Engineering, Carnegie Mellon
More informationCVD SILICON CARBIDE. CVD SILICON CARBIDE s attributes include:
CVD SILICON CARBIDE CVD SILICON CARBIDE is the ideal performance material for design engineers. It outperforms conventional forms of silicon carbide, as well as other ceramics, quartz, and metals in chemical
More informationLecture 11. Etching Techniques Reading: Chapter 11. ECE 6450 - Dr. Alan Doolittle
Lecture 11 Etching Techniques Reading: Chapter 11 Etching Techniques Characterized by: 1.) Etch rate (A/minute) 2.) Selectivity: S=etch rate material 1 / etch rate material 2 is said to have a selectivity
More informationAUSTENITIC STAINLESS DAMASCENE STEEL
AUSTENITIC STAINLESS DAMASCENE STEEL Damasteel s austenitic stainless Damascene Steel is a mix between types 304L and 316L stainless steels which are variations of the 18 percent chromium 8 percent nickel
More informationA Plasma Doping Process for 3D FinFET Source/ Drain Extensions
A Plasma Doping Process for 3D FinFET Source/ Drain Extensions JTG 2014 Cuiyang Wang*, Shan Tang, Harold Persing, Bingxi Wood, Helen Maynard, Siamak Salimian, and Adam Brand Cuiyang_wang@amat.com Varian
More informationFor Touch Panel and LCD Sputtering/PECVD/ Wet Processing
production Systems For Touch Panel and LCD Sputtering/PECVD/ Wet Processing Pilot and Production Systems Process Solutions with over 20 Years of Know-how Process Technology at a Glance for Touch Panel,
More informationDESIGN, FABRICATION AND ELETRICAL CHARACTERIZATION OF SOI FINFET TRANSISTORS
DESIGN, FABRICATION AND ELETRICAL CHARACTERIZATION OF SOI FINFET TRANSISTORS Prof. Dr. João Antonio Martino Professor Titular Departamento de Engenharia de Sistemas Eletrônicos Escola Politécnica da Universidade
More information. Tutorial #3 Building Complex Targets
. Tutorial #3 Building Complex Targets. Mixed Gas/Solid Targets Gas Ionization Chamber Previous Tutorials have covered how to setup TRIM, determine which ion and energy to specify for a semiconductor n-well
More informationTableting Punch Performance Can Be Improved With Precision Coatings
Tableting Punch Performance Can Be Improved With Precision Coatings by Arnold H. Deutchman, Ph. D. Director of Research and Development (614) 873-4529 X 114 adeutchman@beamalloy.net Mr. Dale C. Natoli
More informationWelcome & Introduction
Welcome & Introduction Accelerating the next technology revolution Sitaram Arkalgud, PhD Director Interconnect Temporary Bond Workshop SEMICON West July 11, 2011 San Francisco CA Copyright 2008 SEMATECH,
More informationPOWER GOLD FOR 175 C Tj-max
POWER GOLD FOR 175 C Tj-max James J. Wang and Bob Baird Motorola Inc. Tempe, Arizona USA James.J.Wang@motorola.com ABSTRACT Automotive is requesting engine control IC to operate in 145 C ambient. Power
More informationOur Embedded Dream of the Invisible Future
Our Embedded Dream of the Invisible Future Since the invention of semiconductor chips, the evolution of mankind s culture, society and lifestyle has accelerated at a pace never before experienced. Information
More informationChapter Outline Dislocations and Strengthening Mechanisms
Chapter Outline Dislocations and Strengthening Mechanisms What is happening in material during plastic deformation? Dislocations and Plastic Deformation Motion of dislocations in response to stress Slip
More informationFormation of solids from solutions and melts
Formation of solids from solutions and melts Solids from a liquid phase. 1. The liquid has the same composition as the solid. Formed from the melt without any chemical transformation. Crystallization and
More informationBending, Forming and Flexing Printed Circuits
Bending, Forming and Flexing Printed Circuits John Coonrod Rogers Corporation Introduction: In the printed circuit board industry there are generally two main types of circuit boards; there are rigid printed
More informationDOE Solar Energy Technologies Program Peer Review. Denver, Colorado April 17-19, 2007
DOE Solar Energy Technologies Program Peer Review Evaluation of Nanocrystalline Silicon Thin Film by Near-Field Scanning Optical Microscopy AAT-2-31605-05 Magnus Wagener and George Rozgonyi North Carolina
More information