Welcome & Introduction

Transcription

1 Welcome & Introduction Accelerating the next technology revolution Sitaram Arkalgud, PhD Director Interconnect Temporary Bond Workshop SEMICON West July 11, 2011 San Francisco CA Copyright 2008 SEMATECH, Inc. SEMATECH, and the SEMATECH logo are registered servicemarks of SEMATECH, Inc. International SEMATECH Manufacturing Initiative, ISMI, Advanced Materials Research Center and AMRC are servicemarks of SEMATECH, Inc. All other servicemarks and trademarks are the property of their respective owners.

2 Outline SEMATECH Overview SEMATECH Assessment of key 3D detractors Temporary Bond/ Background SEMATECH s supplier landscape evaluation in 2010 Assessment from SEMATECH Workshop at SEMICON Taiwan (September 2010) Expected Workshop outcome 5 August

3 Scope of technical TSV program Integration Passive TSV daisy chains TSV DtW daisy chains Device interactions 65nm and 30 nm planar/non-planar Keep out area Thermo-mechanical modeling/simulation Electrical modeling/simulation Early reliability Materials: Liner, barrier, seed Plating chemistry Bond materials Temporary, tack Permanent Equipment Development Unit Process Development TSV Module Bond Module Thin and handle Backside processing Metrology Infrared Acoustic x-ray techniques Standard techniques Cu-Cu : Voids Cu-Cu : Void Free Force, m Micro-Chevron Strain, mm 5 August

4 SEMATECH 3D Program Organization GF, HP, Hynix, IBM, Intel, Samsung, TSMC, UMC, CNSE Unit Process TSV Module Thin Bond Metrology Atotech, Lasertec, NEXX, TEL Module Development Baseline/Yield Device Interaction Reliability Modeling/Simulation Test Vehicles Technology development Enablement Center Standards Metrology/Inspection Microbumping/bonding ADI, Altera, ASE, LSI, NIST, ON, Qualcomm Chip chip interoperability, standards and specs for the interface Enablement Center Relationship to SEMATECH s overall 3D Program 3D Enablement Center members (non SEMATECH Members) leverage core program reference flows, program tooling, test structures, etc. No outflow of unit processes, equipment development, integration and early reliability data to 3D Enablement Center 5 August

5 SEMATECH s role Members can, through SEMATECH, orchestrate major industry-wide technology transitions and minimize risk EUV, 450 mm, 3D (standards and infrastructure), disruptive materials/ devices SEMATECH is the only consortium focused on manufacturable technology solutions and critical infrastructure EUV mask infrastructure, metrology, 3D, III-V SEMATECH s R&D can complement members core development activities to quickly narrow technology options Members can benefit from cost sharing and significant government (50%) leverage 5 August

6 Major SEMATECH initiatives 5 August

7 Lack Of Industry-wide Readiness In Critical 3D Areas 5x50 Via-mid Manufacturability barrier /seed (PVD) plate CMP handle wafer bond handle wafer debond back TSV Manufacturability RIE liner grind reveal Readiness Key Process performance (vs technical requirements) ready Repeatability, uniformity, process window close but not quite Tool availability / maturity not ready Throughput / cost of ownership HVM is unrealistic unless the gaps are addressed now Temporary bond/debond is a critical gap As a neutral consortium, SEMATECH is in a position to play a critical role in this transition This workshop Followup workshop at SEMICON Taiwan September 9, Hsinchu 5 August

8 Temporary bonding/debonding Materials Material Type Bond Mechanism Bonding Conditions Mechanism Temperature Carrier Equipment Supplier Material A not specified Reflow T = ºC F = 8kN t =1-3 min Slide Off T = 220ºC Standard Si or Glass Wafer A/B Material B Acrylic UV Cure T = 25ºC F = 8kN t not specified Laser Release T = 25ºC Larger Diameter Glass Wafer B/C Material C Silicone Cure T = 180ºC F = 8kN t not specified Mechanical Release (CVD Layer) T = 25ºC Standard Si or Glass Wafer B Material D not specified Reflow T = 175ºC F = 0.7 kn t = 50sec Solvent Release T = 25ºC Perforated Larger Diameter Glass Wafer D Material E Polyimide Cure T = 350ºC F = 5kN t =10 min All T = 250ºC (thermal slide-off) Process Dependent A/B Several options identified from tool and materials evaluations, solvent, laser debond. 5 August

9 Temporary bonding/debonding Materials Material Type Bond Mechanism Bonding Conditions Mechanism Temperature Carrier Equipment Supplier Material A not specified Reflow T = ºC F = 8kN t =1-3 min Slide Off T = 220ºC Standard Si or Glass Wafer A/B Material B Acrylic UV Cure T = 25ºC Larger F = 8kN Number Laser of companies using each strategy NumDiameter for at least one integration product t not specified Release T = 25ºC Glass Wafer B/C Material C Silicone Cure T = 180ºC F = 8kN t not specified 6Mechanical Release 5(CVD Layer) T = 25ºC Standard Si or Glass Wafer B Material D Material E not specified Polyimide Reflow Cure T = 175ºC F = 0.7 kn t = 50sec T = 350ºC F = 5kN t =10 min # responses 4 3Solvent Release T = 25ºC 2 T = 250ºC 1 (thermal All slide-off) 0 Laser ablatable Thermoplastic Peelable RT debondable Perforated Larger Diameter Glass Wafer Process Dependent Chemically removable Support ring D A/B Other Unsure, DK Several options identified from tool and materials evaluations, solvent, laser debond. No industry consensus observed on best options for temporary bond/debond (SEMATECH survey) integration dependent Closing temporary bonding gap would drive critical mass and accelerate 3D technology into HVM 5 August

10 SEMATECH Survey on Gaps in the Via-Mid Ecosystem 12 companies surveyed Aug-Sep 2010: IDMs, foundries, fabless, OSATs High density via-mid applications including interposers, heterogeneous stacking, logic on logic, memory on memory; timeframe Addresses all aspects of via-mid: wafer processing, assembly, reliability, inspection/metrology, design, test Highest priorities for heterogeneous stacking (e.g., wide IO DRAM) shown below Gaps in Standards and Specifications EDA Exchange Formats Partitioning and floorplanning; Logic verification; Power/Signal integrity analysis; analysis flow; Stress analysis flow; Physical verification; Timing analysis Reliability Reliability test methods Test DFT test access architecture Inspection/metrology TSV voids, defect mapping, microbump inspection and coplanarity Chip Interface Stackable memory pin assignment; Stackable memory physical pinout TSV Keep out area, fill materials, dimensions Thin wafer handling Universal thin wafer carrier Technology Development and Cost Reduction Reliability Criteria; Test methods; ESD Temporary bond/debond cost reduction Materials and release mechanisms cost reduction; Equipment cost reduction TSV Keep out distance/area Microbumping and bonding Pad metallurgy and layer thickness; Bump metallurgy Inspection/metrology Microbump inspection and coplanarity; TSV voids; BWP voids Test Probing microbumps cost reduction 5 August

11 Expected Outcome Survey review 14 companies participated (2 fabless, 4 foundries, 3 IDM-logic, 2 IDM-memory, 3 OSATs) Landscape survey of key suppliers Conclusions 5 August