Lecture 8: PN Junctions and Diodes Circuits

Transcription

1 Lecture 8: PN Juctios ad iodes Circuits Gu-Yeo Wei ivisio of Egieerig ad Alied Scieces Harvard Uiversity Wei 1

2 Overview Readig S&S: Chater 3.1~3.5 Sulemetal Readig Backgroud Let s briefly review juctios agai. his time, we will look at it more from a circuits ersective ala Sedra/Smith. Hece, lease refer to Lecture 7 for a more detailed descritio that discusses bad diagrams. 2

3 Ideal iode Let s begi with a ideal diode ad look at its characteristics 3

4 Rectifier Oe commo use for diodes is to build rectifier circuits Oly lets through ositive voltages ad rejects egative voltages his examle assumes a ideal diode 4

5 Characteristics of Juctio iodes Give a semicoductor PN juctio we get a diode with the followig characteristics. ur o voltage based o the built-i otetial of the PN juctio Reverse bias breakdow voltage due to avalache breakdow (o the order of several volts) 5

6 iode Curret Equatios he forward bias curret is closely aroximated by i v V ( 1) I S e V k q where V is the thermal voltage (~25mV at room tem) k Boltzma s costat 1.38 x joules/kelvi absolute temerature q electro charge x coulombs costat deedet o material betwee 1 ad 2 (we will assume 1) I S scaled curret for saturatio curret that is set by dimesios Notice there is a strog deedece o temerature We ca aroximate the diode equatio for i >> I S i v I S e V I reverse bias (whe v << 0 by at least V ), the i I S I breakdow, reverse curret icreases raidly a vertical lie 6

7 Movemet of Carriers Holes ad electros move through a semicoductor by two mechaisms: iffusio radom motio due to thermal agitatio ad moves from area of higher cocetratio to area of lower cocetratio ad is a fuctio of the cocetratio gradiet d d J q J q dx dx, diffusio costat or the diffusivity of carriers (holes ad electros) rift carrier drift occurs due to a electric field alied across a iece of silico. he field accelerates the carriers (electros or holes) ad acquire a velocity, called drift velocity, deedet o a costat called mobility µ, v µ Ε or µ Ε drift J drift qµ Ε J drift qµ Ε J q( µ + µ )Ε total drift Eistei s relatioshi µ µ V 7

8 oig Itrisic semicoductor have equal cocetratio of holes ad electros. We ca doe the semicoductor to have a larger cocetratio of holes or electros Negatively doig the semicoductor with Arseic or Phoshorus (more electros) gives rise to tye hese atoms doate electros ad so are called doors Addig N cocetratio gives rise to 0 free electros ad i thermal equilibrium 0 N i thermal equilibrium, the roduct of free holes ad electros is costat i where i is the cocetratio of free carriers i itrisic silico the cocetratio of hole (due to thermal ioizatio) is Positively doig with Boro (more holes) gives rise to tye Boro accets electros ad called accetor Addig N A cocetratio gives rise to 0 free holes 0 N A 0 2 i 0 8

9 Juctio I equilibrium, diffusio curret (I ) is balaced by drift curret (I S ) eletio regio hole that diffusio across the juctio ito the regio recombie with majority carriers (electros) ad electros that diffuse across ito the regio recombie with holes. his rocess leaves boud charges to create a et electric field i the deletio regio (o free carriers). Also called the sace-charge regio. he resece of a electric field meas there is voltage dro across this regio called the barrier voltage or built-i otetial he barrier ooses diffusio util there is a balace I equilibrium, diffusio curret is balaced by drift curret that occurs due to the (thermal) geeratio of hole electro airs 9

10 Juctio Built-I Voltage With o exteral biasig, the voltage across the deletio regio is: N V 0 V l A 2 i yically, at room tem, V 0 is 0.6~0.8V Iterestig to ote that whe you measure across the juctio termials, the voltage measured will be 0. I other words, V 0 across the deletio regio does ot aear across the diode termials. his is b/c the metal-semicoductor juctio at the termials couteract ad balace V 0. Otherwise, we would be able to draw eergy from a isolated juctio, which violates coservatio of eergy. N 10

11 Width of eletio Regio he deletio regio exists o both sides of the juctio. he widths i each side is a fuctio of the resective doig levels. Charge-equality gives: qx AN A qx AN he width of the deletio regio ca be foud as a fuctio of doig ad the built-i voltage W de x + x 2ε s q 1 N A + 1 N V 0 ε s is the electrical remittivity of silico 11.7ε 0 (uits i F/cm) 11

12 Juctio i Reverse Bias Let s see how the juctio looks with a exteral curret, I (less tha I S ) electros leave the side ad holes leave the side deletio regio grows V 0 grows I decreases i equilibrium, there is a V R across the termials (greater tha V 0 ) If I > I S, the diode breaks dow As the deletio regio grows, the caacitace across the diode chages. 2ε s 1 1 W de x + x + q + N A N 0 ( V V ) reatig the deletio regio as a arallel late caacitor C j0 C j VR 1+ V 0 R 12

13 Juctio i Forward Bias Now let s look at the coditio where we ush curret through the juctio i the oosite directio. Add more majority carriers to both sides shrik the deletio regio lower V 0 diffusio curret icreases Look at the miority carrier cocetratio lower barrier allows more carriers to be ijected to the other side 13

14 Excess miority carrier cocetratio is govered by the law of the juctio (roof ca be foud i device hysics text). Let s look at holes. V V ( x ) e 0 he distributio of excess miority hole cocetratio i the -tye Si is a exoetially decayig fuctio of distace ( x) + [ ( x ) ] 0 0 ( x x ) L where L is the diffusio legth (steeess of exoetial decay) ad is set by the excess-miority-carrier lifetime, τ. he average time it takes for a hole ijected ito the regio to recombie with a majority carrier electro L he diffusio of holes leads to the followig curret desity vs. x J τ e V V ( x x ) L ( e ) e q 0 1 L 14

15 I equilibrium, as holes diffuse away, they must be met by a costat suly of electros with which they recombie. hus, the curret must be sulied at a rate that equals the cocetratio of holes at the edge of the deletio regio (x ). hus, the curret due to hole ijectio is: V V ( e ) 0 1 Curret due to electros ijected ito the regio is J J q L q L V V ( e ) 0 1 Combied I + A q L I V V ( e 1) 0 q 0 L V V ( 1) I S e 15

16 iode Circuits Look at the simle diode circuit below. We ca write two equatios: I I S e V V ad I V V R 16

17 iode Small Sigal Model Some circuit alicatios bias the diode at a C oit (V ) ad suerimose a small sigal (v d (t))o to of it. ogether, the sigal is v (t), cosistig of both C ad AC comoets Grahically, ca show that there is a traslatio of voltage to curret (i d (t)) Ca model the diode at this bias oit as a resistor with resistace as the iverse of the taget of the i-v curve at that oit ( V + vd ) V V V vd V () t I Se I Se e v ( ) d V i t I e i Ad if v d (t) is sufficietly small the we ca exad the exoetial ad get a aroximate exressio called the small-sigal aroximatio (valid for v d < 10mV) v i + V d () t I 1 I + id id vd So, the diode small-sigal resistace is V r d I I V 17

18 Perform the small sigal aalysis of the diode circuit biased with V by elimiatig the C sources ad relacig the diode with a small sigal resistace he resultig voltage divider gives: v d v s rd R + r Searatig out the C or bias aalysis ad the sigal aalysis is a techique we will use extesively d 18