FEATURES DESCRIPTIO APPLICATIO S TYPICAL APPLICATIO. LTC Channel Analog Multiplexer with Cascadable Serial Interface

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1 LTC -Channel Analog Multiplexer with Cascadable Serial Interface FEATRES Low R ON : Ω Single.V to ±V Supply Operation Low Charge Injection Serial Digital Interface Analog Inputs May Extend to Supply Rails Low Leakage: ±na Max Guaranteed Break-Before-Make TTL/CMOS Compatible for All Digital Inputs Cascadable to Allow Additional Channels Can Be sed as a Demultiplexer APPLICATIO S Data Acquisition Systems Communication Systems DESCRIPTIO The LTC is a high performance CMOS -to- analog multiplexer. It features a serial digital interface that allows several LTCs to be daisy-chained together, increasing the number of MX channels available using a single digital port. The LTC features a typical R ON of Ω, a typical switch leakage of 0pA and guaranteed break-beforemake operation. Charge injection is ±0pC maximum. All digital inputs are TTL and CMOS compatible when operated from single or dual supplies. The inputs can withstand 00mA fault current. The LTC is available in -pin PDIP, SSOP and narrow SO packages. For applications requiring -way serial data transmission, see the LTC0 data sheet. Signal Multiplexing/Demultiplexing, LTC and LT are registered trademarks of Linear Technology Corporation. TYPICAL APPLICATIO V, -Channel -Bit ADC V On-Resistance vs Analog Input Voltage INPTS S S S S S S S D OT LTC 0 0.µF OPTIONAL A/D INPT FILTER V REF V CC +IN LTC IN D OT /SHDN µf ON-RESISTANCE (Ω) T A = C V + = V = V V + =.V = 0V SERIAL INTERFACE TO MX AND ADC DATA IN DATA OT TA0 0 0 INPT VOLTAGE (V) TA0 sn fas

2 LTC ABSOLTE AXI RATI GS W W W (Note ) Total Supply Voltage (V + to )... V Input Voltage Analog Inputs/Outputs... ( 0.V) to (V V) Digital Inputs... 0.V to V Digital Outputs... 0.V to (V V) Power Dissipation... 00mW Operating Temperature Range LTCC... 0 C to 0 C LTCI... 0 C to C Storage Temperature Range... C to 0 C Lead Temperature (Soldering, 0 sec) C W PACKAGE/ORDER I FOR ATIO S S S S S S S TOP VIEW GN PACKAGE -LEAD PLASTIC SSOP N PACKAGE -LEAD PDIP S PACKAGE -LEAD PLASTIC SO V + D D OT 0 T JMAX = C, θ JA = 0 C/ W (GN) T JMAX = C, θ JA = 0 C/ W (N) T JMAX = C, θ JA = 00 C/ W (S) ORDER PART NMBER LTCCGN LTCCN LTC LTCIGN LTCIN LTCIS GN PART MARKING I Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTI The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. V + = V, = V, = 0V, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS Switch V Analog Signal Range (Note ) V R ON On-Resistance V S = ±.V, I D = ma T MIN = 0 C (LTCC) Ω T MIN = 0 C (LTCI) C Ω T MAX = 0 C (LTCC) 0 Ω T MAX = C (LTCI) R ON vs V S 0 % R ON vs Temperature 0. %/ C I S(OFF) Off Input Leakage V S = V, V D = V, V S = V, V D = V ±0.0 ± na Channel Off ±0 na I D(OFF) Off Output Leakage V S = V, V D = V, V S = V, V D = V ±0.0 ± na Channel Off ±0 na I D(ON) On Channel Leakage V S = V D = ±V ±0.0 ± na Channel On ±0 na Digital V INH High Level Input Voltage V + =.V. V V INL Low Level Input Voltage V + =.V 0. V I INL, I INH Input Current V IN = V, 0V ± µa V OH High Level Output Voltage V + =.V, I O = 0µA. V V + =.V, I O = 0µA..0 V V OL Low Level Output Voltage V + =.V, I O =.ma V sn fas

3 ELECTRICAL CHARACTERISTI The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. V + = V, = V, = 0V, unless otherwise specified. LTC SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS Dynamic f Clock Frequency (Note ) MHz t ON Enable Turn-On Time V S =.V, R L = k, C L = pf 0 00 ns t OFF Enable Turn-Off Time V S =.V, R L = k, C L = pf ns t OPEN Break-Before-Make Interval ns OIRR Off Isolation V S = V P P, R L = k, f = 00kHz 0 db Q INJ Charge Injection R S = 0, C L = 000pF, V S = V (Note ) ± ±0 pc C S(OFF) Input Off Capacitance pf C D(0FF) Output Off Capacitance 0 pf Supply I + Positive Supply Current All Logic Inputs Tied Together, V IN = 0V or V 0 µa I Negative Supply Current All Logic Inputs Tied Together, V IN = 0V or V 0 µa The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. V + =.V, = = 0V, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS Switch V Analog Signal Range (Note ) 0. V R ON On-Resistance V S =.V, I O = ma T MIN = 0 C (LTCC) 00 Ω T MIN = 0 C (LTCI) C 0 00 Ω T MAX = 0 C (LTCC) 0 Ω T MAX = C (LTCI) R ON vs V S 0 % R ON vs Temperature 0. %/ C I S(OFF) Off Input Leakage V S =.V, V D = 0.V; V S = 0.V, V D =.V (Note ) ±0.0 ± na Channel Off ±0 na I D(OFF) Off Output Leakage V S =.V, V D = 0.V; V S = 0.V, V D =.V (Note ) ±0.0 ± na Channel Off ±0 na I D(ON) On Channel Leakage V S = V D = 0.V,.V (Note ) ±0.0 ± na Channel On ±0 na Digital V INH High Level Input Voltage V + =.0V.0 V V INL Low Level Input Voltage V + =.V 0. V I INL, I INH Input Current V IN =.V, 0V ± µa V OH High Level Output Voltage V + =.V, I O = 0µA. V V + =.V, I O = 00µA.0.0 V V OL Low Level Output Voltage V + =.V, I O = 0µA 0.0 V V + =.V, I O = 00µA V sn fas

4 LTC ELECTRICAL CHARACTERISTI The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. V + =.V, = = 0V, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS Dynamic f Clock Frequency (Note ) MHz t ON Enable Turn-On Time V S =.V, R L = k, C L = pf (Note ) 0 00 ns t OFF Enable Turn-Off Time V S =.V, R L = k, C L = pf (Note ) 0 00 ns t OPEN Break-Before-Make Interval (Note ) 0 ns QIRR Off Isolation V S = V P P, R L = k, f = 00kHz 0 db Q INJ Charge Injection R S = 0, C L = 000pF, V S = V (Note ) ± ± pc C S(OFF) Input Off Capacitance pf C D(OFF) Output Off Capacitance 0 pf Supply I + Positive Supply Current All Logic Inputs Tied Together, V IN = 0V or.v 0. µa Note : Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note : Guaranteed by Design. Note : Leakage current with a single.v supply is guaranteed by correlation with the ±V leakage current specifications. Note : Timing specifications with a single.v supply are guaranteed by correlation with the ±V timing specifications. TYPICAL PERFOR A CE CHARACTERISTI W ON-RESISTANCE (Ω) On-Resistance vs Temperature V + =.V = 0V V S =.V V + = V = V V S = 0V TEMPERATRE ( C) 0 G0 OTPT VOLTAGE (V) Driver Output Low Voltage vs Output Current 0 0 T A = C V + =.V = 0V V + = V = V OTPT CRRENT (ma) G0 OTPT VOLTAGE (V) Driver Output Low Voltage vs Temperature V + = V = V I O =.ma V + =.V = 0V I O = 00µA TEMPERATRE ( C) G0 sn fas

5 LTC TYPICAL PERFOR A CE CHARACTERISTI W OTPT CRRENT (ma) Driver Output High Voltage vs Output Current.0.0. V + =.V = 0V V + = V = V T A = C OTPT VOLTAGE (V) G0 OTPT VOLTAGE (V) Driver Output High Voltage vs Temperature 0 0 V + = V = V I O =.ma V + =.V = 0V I O = 00µA TEMPERATRE ( C) G0 PIN FNCTIONS, S, S, S, S, S, S, S (Pins,,,,,,, ): Analog Multiplexer Inputs. (Pin ): Digital Ground. Connect to system ground. (Pin 0): System Clock (TTL/CMOS Compatible). The clock synchronizes the channel selection bits and the serial data transfer from to D OT. (Pin ): Channel Select Input (TTL/CMOS Compatible). A logic high on this input enables the LTC to read in the channel selection bits and allows digital data transfer from to D OT. A logic low on this input puts D OT into three-state and enables the selected channel for analog signal transmission. (Pin ): Digital Input (TTL/CMOS Compatible). Input for the channel selection bits. D OT (Pin ): Digital Output (TTL/CMOS Compatible). Output from the internal shift register. (Pin ): Negative Supply. For ±V dual supply applications, should not exceed V + by more than 0% for proper channel selection. D (Pin ): Analog Multiplexer Output. V + (Pin ): Positive Supply. sn fas

6 LTC APPLICATIONS INFORMATION Multiplexer Operation W Figure shows the block diagram of the components within the LTC required for MX operation. The LTC uses to select the active channel and the chip select input,, to switch on the selected channel as shown in Figure. When is high, the input data on the pin is latched into the -bit shift register on the rising clock edge. The input data consists of the EN bit and a string of three bits for channel selection. If EN bit is logic high as illustrated in the first input data sequence, it enables the selected channel. After the clocking in of the last channel selection bit B0, the pin must be pulled low before the next rising clock edge to ensure correct operation. Once is pulled low, the previously selected channel is switched off to ensure a break-before-make interval. After a delay of t ON, the selected channel is switched on allowing signal transmission. The selected channel remains on until the next falling edge of. After a delay of t OFF, the LTC terminates the analog signal transmission and allows the CONTROL LOGIC INPTS ( TO S) -BIT SHIFT REGISTER MX BLOCK OTPT (D) F0 Figure. Simplified Block Diagram of the MX Operation selection of next channel. If the EN bit is logic low, as illustrated in the second data sequence, it disables all channels and there will be no analog signal transmission. Table shows the various bit combinations for channel selection. Table. Logic Table for Channel Selection ACTIVE CHANNEL EN B B BO All Off 0 X X X S 0 0 S 0 0 S 0 S 0 0 S 0 S 0 S Digital Data Transfer Operation The block diagram of Figure shows the components within the LTC required for serial data transfer. When is held high, data is fed into the -bit shift register and then shifted to D OT. Data appears at D OT after the fourth rising edge of the clock as shown in Figure. The last four CONTROL LOGIC -BIT SHIFT REGISTER Figure. Simplified Block Diagram of the Digital Data Transfer Operation D OT F0 EN HIGH B B B0 EN LO B B B0 ANY INPT D t ON t OFF F0 Figure. Multiplexer Operation sn fas

7 LTC APPLICATIONS INFORMATION D OT W bits clocked into the LTC shift register before is taken low select the MX channel that is turned on. This allows a series of devices, with the D OT of one device connected to the of the next device, to be programmed with a single data stream. D D D D D D D D D D Figure. Digital Data Transfer Operation F0 To ensure that only one channel is switched on at any one time, two sets of channel selection bits are needed for DATA as shown in Figure. The first data sequence is used to switch off one MX and the second data sequence is used to select one channel from the other MX or vice versa. In other words, if bit ENA is high and bit ENB is low, one channel of MX A is switched on and all channels of MX B are switched off. If bit ENA is low and bit ENB is high, all channels at MX A are switched off and one channel of MX B is switched on. Care should be taken to ensure that only one LTC is enabled at any one time to prevent two channels from being enabled simultaneously. Multiplexer Expansion Several LTCs can be daisy-chained to expand the number of multiplexer inputs. No additional interface ports are required for the expansion. Figure shows two LTCs connected at their analog outputs to form a -to- multiplexer at the input to an LTC00 A/D converter. ENA A A A0 ENB B B B0 Figure. Data Sequence for MX Expansion F0 V 0.µF 0.µF 0.µF + 0µF V INPTS S S S S S S S LTC A D OT 0 OPTIONAL A/D INPT FILTER + 0µF 0.µF V CC V SS A IN CONV LTC00 V REF D OT + 0µF V 0.µF DATA OT INPTS S S S S S S S LTC B D OT 0 DATA IN F0 Figure. Daisy-Chaining Two LTCs for Expansion sn fas

8 LTC TYPICAL APPLICATIONS Daisy-Chaining Five LTCs INPTS 0.µF BYPASS CAPACITORS FROM V + TO FOR EACH LTC S S S S S S S V + D LTC A D OT 0 V REF V CC +IN LTC IN D OT V 0.µF DATA OT INPTS S S S S S S S LTC B D OT 0 INPTS S S S S S S S LTC C D OT 0 INPTS S S S S S S S LTC D D OT 0 INPTS S S S S S S S LTC E D OT 0 DATA IN TA0 sn fas

9 LTC PACKAGE DESCRIPTIO GN Package -Lead Plastic SSOP (Narrow.0 Inch) (Reference LTC DWG # 0-0-) 0. 0.* (.0.) (0.) REF (..) ** (.0.) (0. 0.) 0.0 ± 0.00 (0. ± 0.0) 0 TYP (..) (0.0 0.) (0.0.0) * DIMENSION DOES NOT INCLDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.00" (0.mm) PER SIDE ** DIMENSION DOES NOT INCLDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.00" (0.mm) PER SIDE ( ) 0.00 (0.) BSC GN (SSOP) 0 sn fas

10 LTC PACKAGE DESCRIPTIO N Package -Lead PDIP (Narrow.00 Inch) (Reference LTC DWG # 0-0-0) 0.0* (.) MAX 0 0. ± 0.0* (. ± 0.) (.0.) 0.0 ± 0.00 (.0 ± 0.) (..) (0. 0.) ( ) 0.00 (0.0) MIN 0. (.) MIN *THESE DIMENSIONS DO NOT INCLDE MOLD FLASH OR PROTRSIONS. MOLD FLASH OR PROTRSIONS SHALL NOT EXCEED 0.00 INCH (0.mm) 0.00 (.) BSC 0.0 (.) TYP 0.0 ± 0.00 (0. ± 0.0) N 0 0 sn fas

11 LTC PACKAGE DESCRIPTIO S Package -Lead Plastic Small Outline (Narrow.0 Inch) (Reference LTC DWG # 0-0-0) 0. 0.* ( ) (..) ** (.0.) (0.0 0.) (0. 0.0) 0 TYP (..) (0.0 0.) (0.0.0) * DIMENSION DOES NOT INCLDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.00" (0.mm) PER SIDE ** DIMENSION DOES NOT INCLDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.00" (0.mm) PER SIDE (0. 0.) TYP 0.00 (.0) BSC S 0 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. sn fas

12 LTC TYPICAL APPLICATIO Interfacing LTC with LTC for Demultiplex Operation OTPTS TTL COMPATIBLE AT V + = V S S S S S S S D OT LTC DATA 0 k OPTIONAL D/A OTPT FILTER V CC V OT LTC LOAD V REF D OT 0.µF 0.µF TA0 V V + V RELATED PARTS PART NMBER DESCRIPTION COMMENTS LTC V -Bit ADC Micropower, Auto Shutdown, SO- Package, SPI, QSPI + MICROWIRE TM Compatible LTC V -Bit ADC Micropower, Auto Shutdown, SO- Package, SPI, QSPI + MICROWIRE Compatible LTC0/LTC SMBus-Controlled Analog Multiplexer Low R ON and Low Charge Injection LTC0 Serial-Controlled -to- Analog Multiplexer Low R ON, Bidirectional Serial Interface, Low Power, -Pin SO LTC0 V, -Bit, 00ksps Serial ADC mw, Internal Reference, SO- Package LTC0 -Bit,.Msps Serial ADC 0mW with Nap and Sleep Modes, V or ±V, Internal Reference LTC0 -Bit, 00ksps Serial ADC V or ±V, Internal Reference and Shutdown LTC -Bit, 00ksps Serial ADC 0mW, Single V or ±V Supply LTC V -Bit Voltage Output DAC Complete V OT DAC, SO- Package, Daisy-Chainable, Low Power LTC V and V -Bit Voltage Output DAC Multiplying V OT DAC, SO- Package, Rail-to-Rail Output, Low Power LTC V -Bit Voltage Output DAC Complete V OT DAC, SO- Package, Daisy-Chainable, Low Power LT0-. Micropower, Precision Bandgap Reference 0µA Supply Current, 0ppm/ C, Available in SOT- LT-. Micropower, Low Dropout Reference 0µA Supply Current, 00mV Dropout, ppm/ C Drift LTC/LTCL -Bit, Voltage Output DAC, V/V SO- Package, Micropower, Serial I/O LTC -Bit, Voltage Output DAC Micropower, Multiplying V OT, Swings from to V REF MICROWIRE is a trademark of National Semiconductor. Linear Technology Corporation 0 McCarthy Blvd., Milpitas, CA 0- (0) -00 FAX: (0) sn fas LT/TP 00.K REV A PRINTE SA LINEAR TECHNOLOGY CORPORATION