DESCRIPTIO. LT1226 Low Noise Very High Speed Operational Amplifier

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1 FEATRES Gain of Stable GHz Gain Bandwidth V/µs Slew Rate.6nV/ Hz Input Noise Voltage V/mV Minimum DC Gain, R L = Ω mv Maximum Input Offset Voltage ±V Minimum Output Swing into Ω ide Supply Range ±.V to ±V 7mA Supply Current ns Settling Time to.%, V Step Drives All Capacitive Loads APPLICATI O S ideband Amplifiers Buffers Active Filters Video and RF Amplification Cable Drivers Data Acquisition Systems DESCRIPTIO Low Noise Very High Speed Operational Amplifier The is a low noise, very high speed operational amplifier with excellent DC performance. The features low input offset voltage and high DC gain. The circuit is a single gain stage with outstanding settling characteristics. The fast settling time makes the circuit an ideal choice for data acquisition systems. The output is capable of driving a Ω load to ±V with ±V supplies and a Ω load to ±3V on ±V supplies. The circuit is also capable of driving large capacitive loads which makes it useful in buffer or cable driver applications. The is a member of a family of fast, high performance amplifiers that employ Linear Technology Corporation s advanced bipolar complementary processing. TYPICAL APPLICATI O Photodiode Preamplifier, A V =.kω, B = MHz Gain of Pulse Response V Ω.k Ω TA TA

2 ABSOLTE AXI RATI GS Total Supply Voltage (V to V )... 36V Differential Input Voltage... ±6V Input Voltage...±V S Output Short Circuit Duration (Note )... Indefinite Operating Temperature Range C... C to 7 C Maximum Junction Temperature Plastic Package... C Storage Temperature Range... 6 C to C Lead Temperature (Soldering, sec.)... 3 C PACKAGE/ORDER I FOR NLL IN IN V N PACKAGE -LEAD PLASTIC DIP TOP VIE NLL V OT NC S PACKAGE -LEAD PLASTIC SOIC PO ATIO ORDER PART NMBER CN CS S PART MARKING 6 ELECTRICAL CHARA CTERISTICS,, V CM = V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS V OS Input Offset Voltage (Note ).3. mv I OS Input Offset Current na I B Input Bias Current µa e n Input Noise Voltage f = khz.6 nv/ Hz i n Input Noise Current f = khz. pa/ Hz R IN Input Resistance V CM = ±V MΩ Differential kω C IN Input Capacitance pf Input Voltage Range V Input Voltage Range 3 V CMRR Common-Mode Rejection Ratio V CM = ±V 9 3 db PSRR Power Supply Rejection Ratio to ±V 9 db A VOL Large Signal Voltage Gain V OT = ±V, R L = Ω V/mV V OT Output Swing R L = Ω. 3.3 ±V I OT Output Current V OT = ±V ma SR Slew Rate (Note 3) V/µs Full Power Bandwidth V Peak, (Note ) 6. MHz GB Gain Bandwidth f = MHz GHz t r, t f Rise Time, Fall Time A VCL =,% to 9%,.V. ns Overshoot A VCL =,.V 3 % Propagation Delay % V IN to % V OT. ns t s Settling Time V Step,.%, A V = ns Differential Gain f = 3.MHz, A V =, R L = Ω.7 % Differential Phase f = 3.MHz, A V =, R L = Ω.6 Deg R O Output Resistance A VCL =, f = MHz 3. Ω I S Supply Current 7 9 ma

3 ELECTRICAL CHARA CTERISTICS,, V CM = V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS V OS Input Offset Voltage (Note ).. mv I OS Input Offset Current na I B Input Bias Current µa Input Voltage Range. V Input Voltage Range 3. V CMRR Common-Mode Rejection Ratio V CM = ±.V 9 3 db A VOL Large Signal Voltage Gain V OT = ±.V, R L = Ω V/mV V OT = ±.V, R L = Ω 7 V/mV V OT Output Voltage R L = Ω ±V R L = Ω ±V I OT Output Current V OT = ±3V ma SR Slew Rate (Note 3) V/µs Full Power Bandwidth 3V Peak, (Note ) 3.3 MHz GB Gain Bandwidth f = MHz 7 MHz t r, t f Rise Time, Fall Time A VCL =, % to 9%,.V ns Overshoot A VCL =,.V % Propagation Delay % V IN to % V OT ns t s Settling Time.V to.v,.%, A V = 6 ns I S Supply Current 7 9 ma ELECTRICAL CHARA CTERISTICS C T A 7 C, V CM = V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS V OS Input Offset Voltage, (Note ).3.3 mv V S = ± V, (Note ).. mv Input V OS Drift 6 µv/ C I OS Input Offset Current and 6 na I B Input Bias Current and 9 µa CMRR Common-Mode Rejection Ratio, V CM = ±V and V S = ± V, V CM = ±.V 9 3 db PSRR Power Supply Rejection Ratio to ±V 9 db A VOL Large Signal Voltage Gain, V OT = ±V, R L = Ω 3 V/mV, V OT = ±.V, R L = Ω 3 V/mV V OT Output Swing, R L = Ω. 3.3 ± V, R L = Ω or Ω ±V I OT Output Current, V OT = ±V ma, V OT = ±3V ma SR Slew Rate, (Note 3) V/µs I S Supply Current and 7. ma Note : A heat sink may be required to keep the junction temperature below absolute maximum when the output is shorted indefinitely. Note : Input offset voltage is tested with automated test equipment in < second. Note 3: Slew rate is measured between ±V on an output swing of ±V on ±V supplies, and ±V on an output swing of ±3.V on ±V supplies. Note : Full power bandwidth is calculated from the slew rate measurement: FPB = SR/πVp. 3

4 TYPICAL PERFOR A CE CHARA CTERISTICS MAGNITDE OF INPT VOLTAGE (V) Input Common Mode Range vs Output Voltage Swing vs Supply Voltage Supply Current vs Supply Voltage Supply Voltage V OS < mv V CM VCM SPPLY CRRENT (ma) OTPT VOLTAGE SING (V) R L = Ω V OS = 3mV V S V S 6. SPPLY VOLTAGE (±V) TPC SPPLY VOLTAGE (±V) TPC SPPLY VOLTAGE (±V) TPC3 OTPT VOLTAGE SING (Vp-p) 3 Output Voltage Swing vs Input Bias Current vs Input Open Loop Gain vs Resistive Load Common Mode Voltage Resistive Load V OS = 3mV INPT BIAS CRRENT (µa) I B I B I B = OPEN LOOP GAIN (db) 9 k k 3. 7 k k LOAD RESISTANCE (Ω) TPC INPT COMMON MODE VOLTAGE (V) TPC LOAD RESISTANCE (Ω) TPC6 SPPLY CRRENT (ma) Output Short Circuit Current vs Supply Current vs Temperature Input Bias Current vs Temperature Temperature 7 INPT BIAS CRRENT (µa) I B I I B B = 7 OTPT SHORT CIRCIT CRRENT (ma) 3 3 SORCE SINK 7 TEMPERATRE ( C) TPC7 TEMPERATRE ( C) TPC TEMPERATRE ( C) TPC9

5 TYPICAL PERFOR A CE CHARA CTERISTICS INPT VOLTAGE NOISE (nv/ Hz) Power Supply Rejection Ratio vs Common Mode Rejection Ratio vs Input Noise Spectral Density Frequency Frequency i n e n FREQENCY (Hz) A V = R S = kω. k k k TPC.. INPT VOLTAGE NOISE (nv/ Hz) POER SPPLY REJECTION RATIO (db) 6 PSRR k k k M FREQENCY (Hz) PSRR M TPC M COMMON MODE REJECTION RATIO (db) 6 k k k M M FREQENCY (Hz) TPC M VOLTAGE GAIN (db) Voltage Gain and Phase vs Frequency Response vs Frequency Output Swing vs Settling Time Capacitive Load k k k M FREQENCY (Hz) M M 6 PHASE MARGIN (DEGREES) OTPT SING (V) 6 6 V S = ± mv SETTLING A V = A V = A V = A V = 6 SETTLING TIME (ns) VOLTAGE MAGNITDE (db) A V = M C = pf C = pf M FREQENCY (HZ) C = pf C = pf C = pf M TPC3 LTC6 TPC TPC OTPT IMPEDANCE (Ω). Closed Loop Output Impedance vs Frequency Gain Bandwidth vs Temperature Slew Rate vs Temperature A V = GAIN BANDIDTH (MHz) SLE RATE (V/µs) 3 3 A V = SR SR. k k M M FREQENCY (Hz) M. 7 TEMPERATRE ( C) 7 TEMPERATRE ( C) TPC6 TPC7 TPC

6 APPLICATI O S I FOR ATIO The may be inserted directly into HA, HA, AD7, EL and LM636 applications, provided that the amplifier configuration is a noise gain of or greater, and the nulling circuitry is removed. The suggested nulling circuit for the is shown below. Offset Nulling V Small Signal, A V = Small Signal, A V = Layout and Passive Components As with any high speed operational amplifier, care must be taken in board layout in order to obtain maximum performance. Key layout issues include: use of a ground plane, minimization of stray capacitance at the input pins, short lead lengths, RF-quality bypass capacitors located close to the device (typically.µf to.µf), and use of low ESR bypass capacitors for high drive current applications (typically µf to µf tantalum). Sockets should be avoided when maximum frequency performance is required, although low profile sockets can provide reasonable performance up to MHz. For more details see Design Note. Feedback resistors greater than kω are not recommended because a pole is formed with the input capacitance which can cause peaking. If feedback resistors greater than kω are used, a parallel capacitor of pf to pf should be used to cancel the input pole and optimize dynamic performance. Transient Response The gain bandwidth is GHz when measured at MHz. The actual frequency response in a gain of is considerably higher than MHz due to peaking caused by a second pole beyond the gain of crossover point. This is reflected in the small signal transient response. Higher noise gain configurations exhibit less overshoot as seen in the inverting gain of response. 6 3 k 7 6 V.µF.µF AI The large signal response in both inverting and noninverting gain shows symmetrical slewing characteristics. Normally the noninverting response has a much faster rising edge due to the rapid change in input common mode voltage which affects the tail current of the input differential pair. Slew enhancement circuitry has been added to the so that the falling edge slew rate is enhanced which balances the noninverting slew rate response. Large Signal, A V = Large Signal, A V = Input Considerations Resistors in series with the inputs are recommended for the in applications where the differential input voltage exceeds ±6V continuously or on a transient basis. An example would be in noninverting configurations with high input slew rates or when driving heavy capacitive loads. The use of balanced source resistance at each input is recommended for applications where DC accuracy must be maximized. Capacitive Loading AI AI3 The is stable with all capacitive loads. This is accomplished by sensing the load induced output pole and adding compensation at the amplifier gain node. As the capacitive load increases, both the bandwidth and phase margin decrease so there will be peaking in the

7 APPLICATI O S I FOR ATIO frequency domain and in the transient response. The photo of the small signal response with pf load shows % peaking. The large signal response with a,pf load shows the output slew rate being limited by the short circuit current. A V =, C L = pf A V =, C L =,pf The can drive coaxial cable directly, but for best pulse fidelity the cable should be doubly terminated with a resistor in series with the output. Compensation AI The has a typical gain bandwidth product of GHz which allows it to have wide bandwidth in high gain configurations (i.e., in a gain of it will have a bandwidth of about MHz). The amplifier is stable in a noise gain of so the ratio of the output signal to the inverting input must be / or less. Straightforward gain configurations of or are stable, but there are a few configurations that allow the amplifier to be stable for lower signal gains (the noise gain, however, remains or more). One example is the inverting amplifier shown in the typical applications sections below. The input signal has a gain of R F /R IN to the output, but it is easily seen that this configuration is equivalent to a gain of as far as the amplifier is concerned. Lag compensation can also be used to give a low frequency gain less than with a high frequency gain of or greater. The example below has a DC gain of 6, but an AC gain of 3. The break frequency of the RC combination across the amplifier inputs should be at least a factor of less than the gain bandwidth of the amplifier divided by the high frequency gain (in this case / of GHz/3 or 3MHz). TYPICAL APPLICATI V IN Ω 33pF k O Lag Compensation S V OT k A V = 6, f < MHz TA3 Compensation for Lower Closed-Loop Gains R F V IN V IN R Ω R.k Cable Driving R3 7Ω V OS Null Loop 3k 3k 7 Ω CABLE k R 7Ω V OT TA V OT V IN R IN R C V OT k k pf Ω R F A V = ; R R F (R IN R C ) IN TA pf LT97 A V = TA6 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of circuits as described herein will not infringe on existing patent rights. 7

8 SI PLII FED SCHE V 7 ATIC NLL BIAS IN 3 IN BIAS 6 OT V SS PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. N Package -Lead Plastic DIP.3.3 (7.6.)..6 (.3.6).6 (.6) TYP.3 ±. (3.3 ±.7). (.6) MAX (.9 -.3) ( ). ±. (.3 ±.3). ±. (. ±.). (3.7) MIN. (.) MIN. ±.3 (.7 ±.76) 3. ±. (6.3 ±.) N 9 T J MAX θ JA C 3 C/ S Package -Lead Plastic SOIC.9.97 (..) TYP.. (..) (.3.).3.69 (.36.73)..9 (.36.3). (.7) BSC.. (..).. ( ) (3. 3.9) T J MAX θ JA 3 S 9 C C/ LT/GP 69 K REV Linear Technology Corporation 63 McCarthy Blvd., Milpitas, CA () 3-9 FAX: () 3-7 TELEX: LINEAR TECHNOLOGY CORPORATION 99

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