Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS

Transcription

1 Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Outline NMOS inverter with resistor pull-up The inverter NMOS inverter with current-source pull-up Complementary MOS (CMOS) inverter Static analysis of CMOS inverter Reading Assignment: Howe and Sodini; Chapter 5, Section Spring 27 Lecture 12 1

2 1. NMOS inverter with resistor pull-up: Dynamics C L pull-down limited by current through transistor [shall study this issue in detail with CMOS] C L pull-up limited by resistor (t PLH RC L ) Pull-up slowest R R : LO HI C L : HI LO : HI LO C L : LO HI pull-down pull-up 6.12 Spring 27 Lecture 12 2

3 1. NMOS inverter with resistor pull-up: Inverter design issues Noise margins A v R RC L slow switching g m W big transistor (slow switching at input) Trade-off between speed and noise margin. During pull-up we need: High current for fast switching But also high incremental resistance for high noise margin. use current source as pull-up 6.12 Spring 27 Lecture 12 3

4 2. NMOS inverter with current-source pull-up I V characteristics of current source: i SUP v SUP i SUP I SUP 1 r oc _ v SUP Equivalent circuit models : i SUP v SUP I SUP roc r oc _ large-signal model small-signal model High current throughout voltage range v SUP > i SUP = for v SUP i SUP = I SUP v SUP / r oc for v SUP > High small-signal resistance r oc Spring 27 Lecture 12 4

5 NMOS inverter with current-source pull-up Static Characteristics i SUP C L Inverter characteristics : i D I SUP r oc = V GS (a) 1 v OUT = v DS (b) High r oc high noise margins 6.12 Spring 27 Lecture 12 5

6 PMOS as current-source pull-up I V characteristics of PMOS: S V SG _ V SD G B V G I Dp _ D V D 5 V I D (V SG,V SD ) (a) V SG = 3.5 V 3 I Dp (µa) (triode region) V SD = V SG V Tp = V SG 1 V V SG = 3 V (saturation region) V SG = 25 V SG =,.5, 1 V (cutoff region) V SG = 2 V V SG = 1.5 V Note: enhancement-mode PMOS has V Tp <. In saturation: (b) I Dp ( V SG V ) 2 Tp 5 V SD (V) 6.12 Spring 27 Lecture 12 6

7 PMOS as current-source pull-up: Circuit and load-line diagram of inverter with PMOS current source pull-up: -I Dp =I Dn PMOS load line for V SG = -V B V B C L Inverter characteristics: NMOS cutoff PMOS triode NMOS saturation PMOS triode NMOS saturation PMOS saturation NMOS triode PMOS saturation V Tn 6.12 Spring 27 Lecture 12 7

8 PMOS as current-source pull-up: NMOS inverter with current-source pull-up allows high noise margin with fast switching High Incremental resistance Constant charging current of load capacitance But When =, there is a direct current path between supply and ground power is consumed even if the inverter is idle. -I Dp =I Dn PMOS load line for V SG = -V B V B :HI C L :LO Ideally, we would like to have a current source that is itself switchable, i.e it shuts off when input is high CMOS! 6.12 Spring 27 Lecture 12 8

9 3. Complementary MOS (CMOS) Inverter Circuit schematic: C L Basic Operation: = = V GSn = < V Tn NMOS OFF V SGp = > - V Tp PMOS ON = = V GSn = > V Tn NMOS ON V SGp = < - V Tp PMOS OFF No power consumption while idle in any logic state! 6.12 Spring 27 Lecture 12 9

10 1 CMOS Inverter (Contd.): Output characteristics of both transistors: I Dn = I Dp I Dp = I Dn n-channel (a) p-channel 3 (b) Note: = V GSn = -V SGp V SGp = - = V DSn = -V SDp V SDp = - I Dn = -I Dp Combine into single diagram of I D vs. with as parameter 6.12 Spring 27 Lecture 12 1

11 CMOS Inverter (Contd.): I D - No current while idle in any logic state Inverter Characteristics: NMOS cutoff PMOS triode NMOS saturation PMOS triode NMOS saturation PMOS saturation NMOS triode PMOS saturation NMOS triode PMOS cutoff V Tn V Tp rail-to-rail logic: logic levels are and High A v around logic threshold good noise margins 6.12 Spring 27 Lecture 12 11

12 2. CMOS inverter: noise margins NM L V M A v (V M ) V IL V M V IH NM H Calculate V M Calculate A v (V M ) Calculate NM L and NM H Calculate V M (V M = = ) At V M both transistors are saturated: I Dn = W n µ 2L n C ox ( V M V Tn ) 2 n I Dp = W p µ 2L p C ( ox V M V ) 2 Tp p 6.12 Spring 27 Lecture 12 12

13 CMOS inverter: noise margins (contd.) Define: k n = W n L n µ n C ox ; k p = W p L p µ p C ox Since : Then: I Dn = I Dp 1 2 k n( V M V Tn ) 2 = 1 2 k ( p V M V ) 2 Tp Solve for V M : V M = V Tn k p k n ( V Tp ) 1 k p k n Usually, V Tn and V Tp fixed and V Tn = - V Tp V M engineered through k p /k n ratio Spring 27 Lecture 12 13

14 CMOS inverter: noise margins (contd..) Symmetric case: k n = k p This implies: V M = 2 k p k n =1 = W p L p µ p C ox W n L n µ n C ox W p L p µ p W n L n 2µ p W p L p 2 W n L n Since usually L p L n = L min W p 2W n Asymmetric case: k n >> k p, or W n L n >> W p L p V M V Tn NMOS turns on as soon as goes above V Tn. Asymmetric case: k n << k p, or W n L n << W p L p V M V Tp PMOS turns on as soon as goes below V Tp Spring 27 Lecture 12 14

15 CMOS inverter: noise margins (contd ) Calculate A v (V M ) Small signal model: S2 v sg2 =-v in g mp v sg2 r op - G2 D2 D1 G1 v in v gs1 g mn v gs1 r on v out S1 G1=G2 D1=D2 v in gmn v in g mp v in r on //r op v out - S1=S2 A v = ( g mn g mp )r ( on // r ) op - This can be rather large Spring 27 Lecture 12 15

16 CMOS inverter: calculate noise margins (contd.) NM L V M A v (V M ) V IL V M V IH V IN NM H Noise-margin low, NM L : V IL = V M V M A v NM L = V IL V OL = V IL = V M V M A v Noise-margin high, NM H : V IH = V M 1 1 A v NM H = V OH V IH = V M 1 1 A v 6.12 Spring 27 Lecture 12 16

17 What did we learn today? Summary of Key Concepts In NMOS inverter with resistor pull-up, there is a trade-off between noise margin and speed Trade-off resolved using current source pull-up Use PMOS as current source. In NMOS inverter with current-source pull-up: if = High, there is power consumption even if inverter is idling. Complementary MOS: NMOS and PMOS switchon alternatively. No current path between power supply and ground No power consumption while idling Calculation of CMOS V M Noise Margin 6.12 Spring 27 Lecture 12 17