Size: px
Start display at page:

Download ""

Transcription

1 VericationofAsynchronousCircuits usingtimedautomata MariusBozga,HouJianmin,OdedMalerandSergioYovine InthisworkweapplythetimingvericationtoolOpenKronos,whichis Abstract basedontimedautomata,toverifycorrectnessofnumerousasynchronouscircuits. Thedesiredbehaviorofthesecircuitsisspeciedintermsofsignal correctlyundertheassumptionthattheinputssatisfythestgconventions transitiongraphs(stg)andwecheckwhetherthesynthesizedcircuitsbehave andthatthegatedelaysareboundedbetweentwogivennumbers.ourresults demonstratetheviabilityofthetimedautomatonapproachfortiminganalysis ofcertainclassesofcircuits. 1 Introduction Todaymostofcircuitvericationandanalysisisdonewhilemaintainingaseparationbetweenthelogicalfunctionalitiesofacircuitandthedelaypropertiesofits components.forclockedsynchronouscircuits,thesizeoftheclockcyclecanbedeterminedbycomputingtheaccumulateddelaysalongthelongestpathfrominputs tolatches.assumingthatthecycletimeissucientlylarge,thefunctionalvericationofthecircuitcanproceedbyignoringgateandwiredelaysandbytreatingthe divisionoflabormakescircuitdesignandvericationamoretractableprocess,it wholecircuitattheabstractionlevelofanuntimedsequentialmachine.whilethis Thereasonisthatinrealitylogicandtiminghavecomplexmutualinteractions, makesitmorediculttosatisfytheever-growingdemandsformoreperformance. pathlengthcandiersignicantlyintheirmaximalstabilizationtimes.thepath andtwodierentrealizationsofthesamecombinationalfunction,havingthesame lengthonlygivesanupper-approximationofthepropagationdelay,takingintoaccountworst-caseswhichare,moreoftenthannot,impossiblewhenlogicistaken intoaccount(\falsepaths"). thespeed-independentparadigm.thedesiredbehaviorofacircuitisspeciedasa Alotofasynchronouscircuits[U69,KKTV93,BS94]designhasbeendonewithin kindof\protocol"betweenthecircuitanditsenvironment. notassumetwodistinctphasesineveryoperationcycle(arrivalofinputsandcomputationofnext-stateandoutput)andhencethecircuitspecicationcannotbe decomposednaturallyintoacombinationalfunctionandamemory.1 Verimag,CentreEquation,2,av.deVignate,38610Gieres,France,@imag.fr Themajor Thisprotocoldoes 1Thisisnotthecaseinburst-modecircuitswhichareoutofthescopeofthispaper. 1

2 burdeninasynchronousdesignistodetectoccurrencesofcertainsubsetsofevents inthecircuit.thisapproachrequiresalargesiliconinvestmentinevent-detection (whichmayappearinvariousorders)whicharesucientfortriggeringfurtherevents mechanismsandithasbeenobserved[ckk+98]thatbytakingdelayinformation actuallyhappenandthesizeofthecircuitcanbereducedsignicantlybyputting intoaccount,manybehaviorsanticipatedbythespeed-independentdesigncannot suchbehaviorsinthe\don't-care"category. betweenlogicanddelayscanbeexpressednaturally,andwhichcanserveasabasis Theseandotherobservationscallforaformalmodelinwhichtheinteraction fordesignandvalidationtoolsthattakeadvantageofthisexpressivepower.timed automata[ad94]constitutesuchamodel.theseareautomataaugmentedwithctitiousclockvariableswhoseroleinthemodelistomeasurethetimeelapsedsince theoccurrenceofcertainevents.usingtheseclocks,thephenomenonofuncertain manner.ofcourse,timedautomata(henceforthta)inheritfromautomatathecapabilitytomodelanycomplexdiscretedynamicsandhencetheyaremoreexpressive thanmodelsbasedontimedmarkedgraphsandthemax-plusalgebra.indeed,it wasshown[d89,l89,mp95]thatcircuitswithbi-boundedgateorwiredelayscan betransformedintonetworksoftimedautomatawhichcanserveasabasisforsimu- butboundeddelaybetweentwoormoreeventscanbeexpressedinaverynatural implemented[lpy97,doty96]andappliedtovariousproblems,includingtiming lation,vericationandautomaticdesign.severaltoolsfortavericationhavebeen tivemodelswhichareusedtoaddressthesameclassofproblemarebasedonsome analysisofcircuits[my96,bmpy97,tb97,tkb97,tky+98,bmt99].alterna- variantsoftimedpetrinets[bd91,hb95,bm98,sy95,yr99,kb99,zm00]and itwillbeinterestingtocomparethemwiththeta-basedapproachbothinterms ofmodelingandexpressivityandintermsofunderlyingcomputationaldiculty. andthetoolopenkronos[bdm+98]tothevericationofasynchronouscircuits.we ThisworkdescribestheapplicationoftheTA-basedvericationmethodology taketwodozensoftypicalasynchronouscircuitsrealizedbygateshavingbi-bounded circuitsbehaveaccordingtotheirspecications.ourperformanceresultsindicate delays. UsingstandardTAreachabilitymethodsweattempttoverifythatthese wereabletoverifycircuitswithupto17gates)andfromwhereyouneedtoaugment howfaronecangobyapplyingbrute-forcevericationtotherichtamodel(we takeadvantageofthespecialstructureofthesub-classoftathatcorrespondto vericationwithacompositionalmethodologyandwithspecializedtechniquesthat circuits. wemodelbi-boundeddelaysusingtimedautomataandhowtimingvericationis Therestofthepaperisorganizedasfollows: insection2wedescribehow appliedtothesemodels. jointbehaviorofthecircuitandofitsstgspecicationareconvertedintoatimed InSection3weillustrate,usinganexample,howthe automataandanalyzedbyopenkronos. benchmarkexamplesarereportedinsection4. Finally,thevericationresultsforthe 2

3 f1 f2 f3 [l1;u1] y1 x1 [l2;u2] y2 x2 [l3;u3] y3 x3 Figure1:Acircuitwithdelays. 2 ModelingDelayswithTimeAutomata boundeddelaysusingtimedautomata[mp95,my96,bmt99].weviewacircuit Inthissectionwesketchinformallyourapproachformodelingcircuitswithbi- asanetworkconsistingofbooleangatesand(non-deterministic)delayelementsas tosignals. infigure1.abooleangatecanbeviewedasamemorylessfunctionfromsignals upper-boundsonthepropagationtimesofeventsfromtheinputtotheoutput(wire Eachdelayelementischaracterizedbyaninterval[l;u]oflower-and Weassumethatthedelaysareinertial:changesthatdonotpersistforltimeare delayscanbemodeledasaspecialcasewherethebooleanfunctionistheidentity). lteredaway.morereneddelaymodelscanbedenedatthepriceofmorecomplex analysis. uncountably-manydierentoutputsignals,asdemonstratedinfigure2,andhence Duetouncertaintyadelayelementcantransformaninputsignalinto thecorrespondingoperatord[l;u]isnon-deterministic,i.e.set-valued.thesemantics ofthecircuitisthesetofallsolutionsofasystemofequationsandinclusionson signalsoftheform: Wetranslateeveryequationintoatimedautomatonwhosesetofbehaviors yi=fi(x1;:::;xn) xi2d[li;ui](yi) automatageneratesexactlyallthepossiblebehaviorsofthecircuitunderallpossible coincideswiththesetofsolutionsoftheequationandthecompositionofallthese aone-stateautomatonwhichgeneratesallthetuplessatisfyingtheequation.each choicesofdelays.theautomatonforabooleangateyi=fi(x1;:::;xn)issimply delayelementoftheformx2d[l;u](y)ismodeledbyonetimedautomatonwith theinputyandtheoutputxareboth0. 4statesandoneclockasdepictedinFigure3.State(0;0)isastablestatewhere atransitiontotheexcitedstate(1;0)ismadeandaclockcisresettozeroand Assoonastheinputychangesto1, signiesa\regret"oftheinputbeforethepropagationoftheeventtotheoutput. startsmeasuringthetimesincetheevent.thetransitionfrom(1;0)backto(0;0) inputbehavesaccordingtosomeprotocol,orbereplacedbyan\error"transition Suchregrettransitionscanbeavoidedincertainmodelswhichassumethatthe ifthedesignmethodologydisallowssuchphenomena.whenatstate(1;0),ifthe clockvaluecrossesthelowerboundl,theoutputcanchangeto1andtheautomaton movestothestablestate(1;1).however,aslongastheupperbounduhasnotbeen reached,theautomatonmaystayin(1;0).theabilitytoexpressandanalyzethis 3

4 Figure2:Aninputsignalandasamplef1;:::;7gofthesetD[1;3]()ofits delayedoutputs. temporaluncertaintyisthemainfeatureofta.unlikedeterministicmodelsused inspicesimulation,acircuitmodeledusingsuchbi-boundeddelayelementsand theircorrespondingtawillhavemanybehaviors,eveninthepresenceofasingle basedonthepossiblerangesofthevaluesofclockvariables.thegeneratorsofinput inputsignal.howeverallthesebehaviorscanbecapturedusinggeometricmethods inputssuchastimingboundsontheirfrequencyorsomeprotocolsofinteraction signalscanalsobemodeledastimedautomata,expressingvariousrestrictionsonthe withthecircuitthattheyfollow. modelthecircuit,itispossible,inprinciple,tosimulateallthepossiblebehaviorsof Bycombiningtheseautomatawiththosethat thecircuit,inthepresenceofalladmissibleinputsandchoicesofdelaysandhence liftformalvericationmethodologyfromuntimedtotimedcircuitmodels. Figure4.Supposethatinitiallytheyarebothinstate0andhencethereachability Asanillustrativeexampleconsiderthetwoindependentoscillatorsappearingin maystayat(0;0)aslongasnoneoftheclockshascrosseditscorrespondingupperbound.inthisexample,whereu1<u2,thesetofclockvaluesreachableviatime analysisstartsatglobalstate(0;0)withclocksat(0;0).theproductautomaton passageatstate(0;0)isf(x1;x2):x1=x2u1g.byintersectingthissetwith whichdenotesalltheclockvaluationsinwhichthetransitionfrom(0;0)to(1;0)is thetransitionguardc1l1weobtainthesetf(x1;x2):l1x1=x2u1g enabled.sincethistransitionresetsc1wemayreach(1;0)atanypointintheclock reachthesetf(x1;x2):l1x2u2^l1x2?x1u1g,andthisset,inturn,can spacebelongingtof(0;x2):l1x2u1g.fromthere,bytimepassage,wemay beintersectedwiththeconditionc2l2formovingto(1;1)etc.thereadercan ndformaldenitionsoftareachabilityanalysisin[a99,y98]. FromatheoreticalstandpointalltheinterestingproblemsconcerningTA(and 4

5 y=0 (0;0) y=1=c:=0 y=0^c<u C<u y=1^ (1;0) Cu lc^ y=1^ Cu lc^ y=0^ y=0^ y=1^c<u C<u (0;1) y=0=c:=0 y=1 (1;1) Figure3:Thetimedautomatonforadelayelement.Therunsoftheautomatonare exactlythosesatisfyingy2d[l;u](x). C1<u1 0 C1l1=C1:=0 C1<u1 1 C1l1=C1:=0 C2<u2 0 C 2l2=C2:=0 C 2<u2 1 C2l2=C2:=0 u2 l2 u2 l2 (0;0) l1(0;1) u1 u2 (1;0) l2 l1 u1 u2 (1;1) l2 l1 u1 l1 u1 Figure4:(a)TwoTArepresentingtwoindependentoscillators.(b)Therststeps (a) (b) incomputingalltheirpossiblebehaviors.dashedlinesindicatediscretetransitions. 5

6 circuitsmodeledbythem)canbesolvedalgorithmically.theseproblemsinclude absenceofhazards,boundedresponseproperties,absenceofshortcutsintransistor rentlyclassiedunderdierentsub-topicsincircuitdesign.otherproblemswhich models,conformancewithcommunicationprotocolsandmanyotherpropertiescur- automaticderivationofdelayparametersandtransitionconditionsinordertoguaranteesatisfactionofcertainproperties)andthetime-optimalcontrollersynthesis canbeformulatedandtheoreticallysolvedarethecontrollersynthesisproblem(the problem(choosingparametersandconditionsthatwillleadtheautomatonintoa tionalcircuit).however,duetothecomplexityoftaanalysis,manyresearchers setofstatesassoonaspossible,e.g.intothesetofstablestatesinacombina- inthelongrunitisbettertoseparateconsiderationsofmodelingadequacyfrom andpractitionerspreferlessexpressivebutmoretractablemodels.webelievethat morepragmaticconsiderationsrelatedtotoolperformance. bettertohaverstageneralmodelwhichdescribesthephenomenoninquestionin Inotherwords,itis vericationcomplexity.ourstrategyisthustousethefulltamodelandseewhat afaithfulmannerandonlylatertodevisevarioustechniquesinordertoovercome isthelargestchunkofcircuitrythatcanbewhollyanalyzedusingtatechnology, beforeresortingtoabstractionandapproximationtechniques. 3 ModelingandVericationofAsynchronousCircuits WehaveappliedOpenKronostoseveralbenchmarkexamplesofasynchronouscircuitstakenfrom[PCKP00].Theintendedbehaviorsofthesecircuitswerespecied usingsignaltransitiongraphs(stgs),whichareakindofpetrinetlabeledbyevents correspondingtorisingandfallingofsignals.anstgrepresentsa\protocol"of interactionbetweenacomponentanditsenvironment. thecircuithalfwhichrealizesahalfhandshakebetweentwoadjacentstagesina Asanexample,consider andao.thebehaviorisspeciedbythestgoffigure5-(b).thisspecication pipeline. ThecircuithastwoinputsignalsRiandAiandtwooutputsignalsRo denesonlyapartial-orderamongeventsandisindierent,forexample,totheorder Figure5-(c)whichacceptsallthelinearizationsofthepartial-order.Itisassumed betweenao+andai+.themarkinggraphofthisspecicationistheautomatonof up).wewanttoverifywhetherthecircuitimplementationbehavesproperly,that thattheenvironmentrespectsthespecication(e.g.aiwillnotrisebeforerogoes is,theaoandroeventstakeplacewhentheyareallowedbythestg. thestgswherefedintothesynthesistoolpetrify[ckk+97]whichproducesspeed- Thecircuitsrealizingthespecicationsweresynthesizedasfollows. Initially independentcircuitsusinggateswitharbitraryfan-in.whilesuchcircuitsarespeed- independentbyconstruction(andhencedonotneedverication)theirrealizations, usinggatestakenfromastandardcelllibrary,isnot. specicationisdepictedinfigure5-(d)andithasveinternalvariablesinaddition Thecircuitforthehalf toinputsandoutputs.thegatedelaysareassumedtobeintheinterval[27;33]. eledasaproductoftimedautomatawithaclockforeachgate{inthiscase7clocks. Accordingtotheprinciplesdescribedintheprevioussectionthecircuitismod- Thistimedautomatondescriptionisgeneratedautomaticallyfromthecircuits.The 6

7 Ri Ao Ro Ai INPUTS: Ai,Ri OUTPUTS: Ao,Ro Ro+ Ao+ Ai+ Ri- Ro- Ao- Ri+ Ai- (a) (b) 0 1 Ro+ 2 Ao+ 3 Ai+ 4 Ri- 5 Ai+ Ao+ 6 Ai+ Ri- 7 Ro- 8 Ro- Ri- 9 Ai- 10 Ao- 11 Ai- Ri- 12 Ri+ 13 Ai- Ao- Ai- Ri+ Ai Ro Ao Ri (c) (d) Figure5:Thehalfcircuit:(a)Theblockdiagram. (b)thestgspecication circuit.theboxesarepntransitionslabeledbyrisingandfallingofsignals.all thepnplaces,exceptthosewithtokensattheinitialcongurations,areomitted. (c)theequivalentautomatonforthespecication.(d)thesynthesizedcircuit. 7

8 STGspecicationistranslatedautomaticallyintoanuntimedautomatonisomorphictothemarkinggraph,witherrortransitionsaddedforeveryoutputeventand state3intheautomatonoffigure5-(c)). astateinwhichitisnotenabled(e.g.eventr0-inducesanerrortransitionfrom inter-arrivaltimesoftheinputeventsaremodeledusinganadditionalautomaton Additionaltimingconstraintsonthe andaclockforeachinputsignal. behaviorsofthecircuitcontainsabehaviornotincludedinthesemanticsofthestg. Thevericationproblemthatweposeiswhetherthesetofallthetime-constrained Technicallythisquestionisequivalenttowhetheranerrortransitionisreachable inthecompositionofalltheabovementionedautomata.forthehalfcircuit,ifwe assumenotimingrestrictionsontheinputs,wendthefollowingerrortrace: Ro-Ai Ao-Ri+Ro+Ai+2+27Ro- 27Ro+Ai Ao+Ri risingofai.thenaftermore27timetheoutputofgate3fallsandthatofgate2 Inthistrace,Rogoesupafter27timeunitsandthisisfollowedimmediatelyby rises,andsoon,untilnallyro-occursbeforebeingenabledbya0+.ontheother sometimein[900;1111],thecircuitisprovedcorrect(similarresultsunderthislast hand,ifweassumethattheanytwochangesofaninputvariableareseparatedby assumptionwereobtainedin[pckp00]). 4 ExperimentalResults Wehaveappliedtheproceduredescribedaboveto21asynchronouscircuitswhose withnvariableshasnclocksandupto2ndiscretestates(notallwhichmightbe sizesrangebetween6to24gates.atimedautomatoncorrespondingtoacircuit reachable).theanalysisisperformedontheproductofthistawiththeautomata forthestgspecicationandtheautomatathatmodelthetime-constrainedinputs tocomputethe\simulationgraph"(see[y98])whosestatesarepairsoftheform (OpenKronosgeneratestheproduct\on-the-y").Foreachcircuitwehavetried Dependingonthetemporalcomplexityoftheautomaton,thesizeofthisgraphmight (q;f)whereqisadiscretestateandfisapolyhedralsubsetoftheclockspace. besignicantlylargerthanthenumberofdiscretestates.computingthesimulation graphamountstocomputingallthereachablestatesoftheta,andthiscomputation isneededtoprovethatthecircuitiscorrect.forincorrectcircuitsbugscanusually befoundmuchbeforethecompletionofthiscomputation.astable1shows,wewere 6,wewereabletocomputearound500000symbolicstatesinabout10minutes abletoperformthisexhaustiveanalysisto15circuitsoutof21.fortheremaining withtheavailablememory(alltheresultswereobtainedonasunultrasparc10 with2gbofmemory).amongthesewefound,nevertheless,bugsintwo,namely analysisalgorithmfortimedautomata,unliketheapproachof[pckp00],which tsend-bmandmr1. Theseresultswereobtainedusingthestandardreachability untimedanalysisisapplied. inspiredourwork,whereaspecialheuristicwhichalternatesbetweentimedand asynchronouscircuitsisasourceofoptimismconcerningthefutureapplicability TheabilityofOpenKronostotreatsuchnon-trivial 8

9 no. 1 name allocoutbound gates 11 states 313 transitions 366 time(sec) 0.09 correct 2 chu converta d N 56 ebergen half mpforwardpkt nowick rcvsetup rpdft sbuframwrite sbufreadctl sbufsendctl sbufsendpkt vme mr Y tsendbm mmu N 19 mr ramreadsbuf Table1:Theperformanceresultsforthebenchmarkasynchronouscircuits. 21 trimossend ? numberofstatesandtransitionarethoseofthesimulationgraphandthetime The gurescorrespondtothedurationofcomputingthisgraph. oftaanalysistotimingverication. achievedwithoutanyheuristic,muchlargercircuitscouldbeveriedbycombining Webelievethatiftheseresultscouldbe thevericationengineofopenkronoswithgeneralandcircuit-specicabstraction andapproximationtechniques[b96,aiky95,wd94,takb96,zm00],combination ordermethods[bm98]andothertechniquesreportedintheliterature. oftimedanduntimedverication[pckp00],relativetiming[sgr99,kb99],partial- Acknowledgment: uswiththebenchmarksandformanyrelateddiscussions. WethankJordiCortadellaandMarcoPenaforproviding KishinevskiandLucianoLavagnoansweredvariousquestionsconcerningasynchronous KenStevens,Mike circuits. References [A99] R.Alur,TimedAutomata,Proc.CAV'99LNCS1633,8-22,Springer, [AD94] R.AlurandD.L.Dill,ATheoryofTimedAutomata,TheoreticalComputerScience126,183{235,

10 [AIKY95] SuccessiveApproximation,InformationandComputation118, , R.Alur,A.Itai,R.P.KurshanandM.Yanakakis,TimingVericationby [AMP98] E.Asarin,O.MalerandA.Pnueli,OntheDiscretizationofDelaysin TimedAutomataandDigitalCircuits,inR.deSimoneandD.Sangiorgi [B96] F.Balarin,ApproximateReachabilityAnalysisofTimedAutomata, (Eds),Proc.Concur'98,LNCS1466, ,Springer,1998. [BD91] Proc.RTSS'96,52-61,IEEE,1996. B.BerthomieuandM.Diaz,ModelingandVericationofTimeDependentSystemsusingTimePetriNets,IEEETrans.onSoftwareEngineering17, ,1991. [BM98] W.BelluominiandC.J.Myers,VericationofTimedSystemsUsing POSETs,inA.J.HuandM.Y.Vardi(Eds.),Proc.CAV'98, , [BDM+98] M.Bozga,C.Daws,O.Maler,A.Olivero,S.Tripakis,andS.Yovine, LNCS1427,Springer,1997. LNCS1427,Springer,1998. Kronos:aModel-CheckingToolforReal-TimeSystems,Proc.CAV'98, [BMPY97] M.Bozga,O.Maler,A.Pnueli,S.Yovine,SomeProgressintheSymbolicVericationofTimedAutomata,inO.Grumberg(Ed.)Proc. [BMT99] CAV'97, ,LNCS1254,Springer,1997. AutomatausingDenseandDiscreteTimeSemantics,inL.Pierreand M.Bozga,O.MalerandS.Tripakis,EcientVericationofTimed T.Kropf(Eds.),Proc.CHARME'99, ,LNCS1703,Springer, [BS94] J.A.BrzozowskiandC-J.H.Seger,AsynchronousCircuits,Springer, [CKK+97] J. A.Yakovlev,Petrify:atoolformanipulatingconcurrentspecications Cortadella, M. Kishinevsky, Kondratyev, L. Lavagno and andsynthesisofasynchronouscontrollers,ieicetransactionsoninformationandsystems,vol.e80-d,no.3,march1997,pages [CKK+98] J.Cortadella,M.Kishinevsky,A.Kondratyev,L.Lavagno,A.Taubin timizationofasynchronouscircuits,inproc.iccad'98, ,1998. anda.yakovlev,lazytransitionsystems:applicationtotimingop- [D89] D.L.Dill,TimingAssumptionsandVericationofFinite-StateConcurrentSystems,inJ.Sifakis(Ed.),AutomaticVericationMethodsfor [DOTY96] FiniteStateSystems,LNCS407, ,Springer,1989. "HybridSystemsIII,VericationandControl",LNCS1066,Springer, C.Daws,A.Olivero,S.Tripakis,andS.Yovine,ThetoolKronos,in

11 [HB95] H.HulgaardandS.M.Burns,EcientTimingAnalysisofaClassof [KB99] H.KimandP.A.Beerel,RelativeTimingBasedVericationofTimed PetriNets,Proc.CAV'95,1995. [KKTV93] CircuitsandSystems,Proc.IWLS'99,June1999. M.Kishinevsky,A.Kondratyev,A.TaubinandV.Varshavsky,ConcurrentHardware:TheTheoryandPracticeofSelf-TimedDesign,Wiley, [LPY97] K.G.Larsen,P.PetterssonandW.Yi,UPPAALinaNutshell,Software [L89] H.R. ToolsforTechnologyTransfer1/2,1997. BoundedTemporalUncertainty,TR15-89,HarvardUniversity,1989. Lewis, Finite-state Analysis of Asynchronous Circuits with [MP95] O.MalerandA.Pnueli,TimingAnalysisofAsynchronousCircuits CHARME'95,LNCS987, ,Springer,1995. usingtimedautomata,inp.e.camurati,h.eveking(eds.),proc. [MY96] O.MalerandS.Yovine,HardwareTimingVericationusingKRONOS, InProc.7thIsraeliConferenceonComputerSystemsandSoftwareEngineering,Herzliya,Israel,June1996. [PCKP00] M.A.Pena,J.Cortadella,A.KondratyevandE.Pastor,FormalVericationofSafetyPropertiesinTimedCircuits,Proc.Async'00,2-11, IEEEPress,2000. [RM94] T.G.RokickiandC.J.Myers,AutomaticVericationofTimedCircuits, [SY95] A.SemenovandA.Yakovlev,VericationofAsynchronousCircuits Proc.CAV'94,June,1994. [SGR99] basedontimedpetrinetunfolding,proc.tau'95, ,1995. Async'99,1999. K.S.Stevens, R.Ginosar, ands.rotem, RelativeTiming, Proc. [TAKB96] tionsoftimedsystems,inproc.concur'96, ,springer,1996. S.TasiranR.Alur,R.P.KurshanandR.Brayton,VerifyingAbstrac- [TB97] tionalandhierarchicaltimingverication,ino.grumberg(ed.)proc. S.TasiranandR.K.Brayton, STARI:ACaseStudyinComposi- [TKB97] S.Tasiran,Y.KukimotoandR.K.Brayton,ComputingDelaywith CAV'97, ,LNCS1254,Springer,1997. [TKY+98] CouplingusingTimedAutomata,Proc.TAU'97,1997. S.Tasiran,S.P.Khatri,S.Yovine,R.K.BraytonandA.SangiovannitationofCircuitDelayinthePresenceofCross-Talk,FMCAD'98,1998. Vincentelli,ATimedAutomaton-BasedMethodforAccurateCompu- 11

12 [WD94] [U69] H.Wong-ToiandD.L.Dill,ApproximationsforVerifyingTimingProperties,inT.RusandC.Rattray(Eds.),TheoriesandExperiencesfor S.H.Unger,AsynchronousSequentialSwitchingCircuits,Wiley,1969. [YR99] T.YonedaandH.Ryu,TimedTraceTheoreticVericationusingPartial Real-TimeSystemDevelopment,WorldScienticPublishing,1994. [Y98] S.Yovine, OrderReduction,Proc.Async'99, ,1999. F.Vaandrager(Eds.),LecturesonEmbeddedSystems,LNCS1494, Model-checkingtimedautomata, ing.rozenbergand [ZM00] Springer,1998. H.ZhengandC.J.Myers,AutomaticAbstractionforSynthesisandVericationofDeterministicTimedSystems,Proc.TAU'2000,December,

Genet A tool for the synthesis and mining of Petri nets. Josep Carmona jcarmonalsi.upc.edu Software Department Universitat Politcnica de Catalunya

Genet A tool for the synthesis and mining of Petri nets. Josep Carmona jcarmonalsi.upc.edu Software Department Universitat Politcnica de Catalunya Genet A tool for the synthesis and mining of Petri nets Josep Carmona jcarmonalsi.upc.edu Software Department Universitat Politcnica de Catalunya 2 Contents 1.1 Overview of the tool.......................

More information

PRESS RELEASE Sw y x e m b r a c e s En t e r p r i s e m a r k e t w i t h l a u n c h o f n e w I P t e l e p h o n y p o r t f o l i o t h r o u g h a s i n g l e c o m m o n p l a t f o r m - New offerings

More information

Modeling and Design of Asynchronous Circuits

Modeling and Design of Asynchronous Circuits Modeling and Design of Asynchronous Circuits MARK B. JOSEPHS, STEVEN M. NOWICK, AND C. H. (KEES) VAN BERKEL, MEMBER, IEEE This technology review explores the behavioral and structural design domains for

More information

Victims Compensation Claim Status of All Pending Claims and Claims Decided Within the Last Three Years

Victims Compensation Claim Status of All Pending Claims and Claims Decided Within the Last Three Years Claim#:021914-174 Initials: J.T. Last4SSN: 6996 DOB: 5/3/1970 Crime Date: 4/30/2013 Status: Claim is currently under review. Decision expected within 7 days Claim#:041715-334 Initials: M.S. Last4SSN: 2957

More information

d e f i n i c j i p o s t a w y, z w i z a n e j e s t t o m. i n. z t y m, i p o jі c i e t o

d e f i n i c j i p o s t a w y, z w i z a n e j e s t t o m. i n. z t y m, i p o jі c i e t o P o s t a w y s p o і e c z e t s t w a w o b e c o s у b n i e p e і n o s p r a w n y c h z e s z c z e g у l n y m u w z g lb d n i e n i e m o s у b z z e s p o і e m D o w n a T h e a t t i t uodf

More information

Cascaded Counters. Page 1 BYU

Cascaded Counters. Page 1 BYU Cascaded Counters Page 1 Mod-N Counters Generally we are interested in counters that count up to specific count values Not just powers of 2 A mod-n counter has N states Counts from 0 to N-1 then rolls

More information

Optimal Technology Mapping and Cell Merger for Asynchronous Threshold Networks

Optimal Technology Mapping and Cell Merger for Asynchronous Threshold Networks Optimal Technology Mapping and Cell Merger for Asynchronous Threshold Networks Cheoljoo Jeong Steven M. Nowick Department of Computer Science Columbia University Outline Introduction Background Technology

More information

End-to-endDelayofVideoconferencingoverPacket

End-to-endDelayofVideoconferencingoverPacket End-to-endDelayofVideoconferencingoverPacket POBox218,YorktownHeights,NewYork1598 T.J.WatsonResearchCenter-IBM MarioBaldiandYoramOfek SwitchedNetworks calltointeractnaturally,theend-to-enddelayshouldbebelowhumanperception-about

More information

A Delay Efficient Robust Self-Timed Full Adder

A Delay Efficient Robust Self-Timed Full Adder A Delay Efficient Robust Self-Timed Full Adder P. Balasubramanian and D.A. Edwards School of Computer Science The University of Manchester Oxford Road, Manchester M13 9PL, United Kingdom. E-mail ID: {padmanab,

More information

Design Example: Counters. Design Example: Counters. 3-Bit Binary Counter. 3-Bit Binary Counter. Other useful counters:

Design Example: Counters. Design Example: Counters. 3-Bit Binary Counter. 3-Bit Binary Counter. Other useful counters: Design Eample: ers er: a sequential circuit that repeats a specified sequence of output upon clock pulses. A,B,C,, Z. G, O, T, E, R, P, S,!.,,,,,,,7. 7,,,,,,,.,,,,,,,,,,,. Binary counter: follows the binary

More information

SmartVFD Frame 4 Wiring Diagrams and Dimensional Drawings

SmartVFD Frame 4 Wiring Diagrams and Dimensional Drawings Smart Frame Wiring Diagrams and Dimensional Drawings Smart Frame Size 60 Vac:.5-7.5 HP 08/0 Vac: 0.75- HP SPECIFICATION DATA CONTENTS Smart Frame Wiring Diagrams... Frame, Fused Disconnect Wiring Diagrams...

More information

Napier University. School of Engineering. Electronic Engineering A Module: SE42205 Digital Design

Napier University. School of Engineering. Electronic Engineering A Module: SE42205 Digital Design Napier University School of Engineering Digital Design Clock + U1 out 5V "1" "2" "4" JK-FF D JK-FF C JK-FF B U8 SN7408 signal U4 SN74107 U5 SN74107 U6 SN74107 U3 SN7408 U2 J Q J Q & J Q & K CQ K CQ K CQ

More information

Interconnection Networks

Interconnection Networks Advanced Computer Architecture (0630561) Lecture 15 Interconnection Networks Prof. Kasim M. Al-Aubidy Computer Eng. Dept. Interconnection Networks: Multiprocessors INs can be classified based on: 1. Mode

More information

Prof. Alex Yakovlev and Dr Fei Xia, School of EECE, Newcastle University

Prof. Alex Yakovlev and Dr Fei Xia, School of EECE, Newcastle University Final Report on EPSRC grant Self-Timed Event Processor (EP/E044662/1) Prof. Alex Yakovlev and Dr Fei Xia, School of EECE, Newcastle University Main areas of achievement: (1) Foundations and basic modelling

More information

1. Find the length of BC in the following triangles. It will help to first find the length of the segment marked X.

1. Find the length of BC in the following triangles. It will help to first find the length of the segment marked X. 1 Find the length of BC in the following triangles It will help to first find the length of the segment marked X a: b: Given: the diagonals of parallelogram ABCD meet at point O The altitude OE divides

More information

Hardware Implementations of RSA Using Fast Montgomery Multiplications. ECE 645 Prof. Gaj Mike Koontz and Ryon Sumner

Hardware Implementations of RSA Using Fast Montgomery Multiplications. ECE 645 Prof. Gaj Mike Koontz and Ryon Sumner Hardware Implementations of RSA Using Fast Montgomery Multiplications ECE 645 Prof. Gaj Mike Koontz and Ryon Sumner Overview Introduction Functional Specifications Implemented Design and Optimizations

More information

Supplementary Order Paper

Supplementary Order Paper No 35 House of Representatives Supplementary Order Paper Tuesday, 25 August 2009 Proposed amendments to SOP No. 34 and Taxation (International Taxation, Life Insurance, and Remedial Matters) Bill Hon Peter

More information

Demystifying Data-Driven and Pausible Clocking Schemes

Demystifying Data-Driven and Pausible Clocking Schemes Demystifying Data-Driven and Pausible Clocking Schemes Robert Mullins Computer Architecture Group Computer Laboratory, University of Cambridge ASYNC 2007, 13 th IEEE International Symposium on Asynchronous

More information

Set-Reset (SR) Latch

Set-Reset (SR) Latch et-eset () Latch Asynchronous Level sensitive cross-coupled Nor gates active high inputs (only one can be active) + + Function 0 0 0 1 0 1 eset 1 0 1 0 et 1 1 0-? 0-? Indeterminate cross-coupled Nand gates

More information

č é é č Á Ě Č Á š Á Ó Á Á ď ú ď Š ň Ý ú ď Ó č ď Ě ů ň Č Š š ď Ň ď ď Č ý Ž Ý Ý Ý ČÚ Ž é úč ž ý ž ý ý ý č ů ý é ý č ý ý čů ý ž ž ý č č ž ž ú é ž š é é é č Ž ý ú é ý š é Ž č Ž ů Ů Ť ý ý ý Á ý ý Č Ť É Ď ň

More information

System on Chip Design. Michael Nydegger

System on Chip Design. Michael Nydegger Short Questions, 26. February 2015 What is meant by the term n-well process? What does this mean for the n-type MOSFETs in your design? What is the meaning of the threshold voltage (practically)? What

More information

A Tree Arbiter Cell for High Speed Resource Sharing in Asynchronous Environments

A Tree Arbiter Cell for High Speed Resource Sharing in Asynchronous Environments A Tree Arbiter ell for High Speed Resource Sharing in Asynchronous Environments Syed Rameez Naqvi and Andreas Steininger Department of omputer Engineering, Vienna University of Technology, Austria {rnaqvi,

More information

2015 PMB SEMESTER 2 Module timetable - PADM2B0 W2 (F) Introduction to Public Sector HR Management (Wk 30, 2015/07/19)

2015 PMB SEMESTER 2 Module timetable - PADM2B0 W2 (F) Introduction to Public Sector HR Management (Wk 30, 2015/07/19) Module timetable - W2 () Introduction to Public Sector HR Management (Wk 30, 2015/07/19) Mo 2015/07/21 2015/07/20 2015/07/22 Wk 30, 2015/07/22 2015/07/24 2015/07/23 Tutorial, Wk 30, 2015/07/24 Page 1,

More information

Low latency synchronization through speculation

Low latency synchronization through speculation Low latency synchronization through speculation D.J.Kinniment, and A.V.Yakovlev School of Electrical and Electronic and Computer Engineering, University of Newcastle, NE1 7RU, UK {David.Kinniment,Alex.Yakovlev}@ncl.ac.uk

More information

PHILADELPHIA COUNTY LAND USE CODES

PHILADELPHIA COUNTY LAND USE CODES PHILADELPHIA COUNTY LAND USE S *Sorted by Code Land Use Codes classify the current use of a property in TREND s public records system. These codes are formatted numerically or in code and have a general

More information

RAID5 Scaling. extremesan Performance 1

RAID5 Scaling. extremesan Performance 1 RAID5 Scaling Objective: Show Linear Scaling of extremesan in RAID 5 sets under increasing load Config: 4 volumes of 4 drive RAID 5, 4 initiators, each with 2 connections. Sequential Read/Write test. Results:

More information

PHILADELPHIA COUNTY LAND USE CODES

PHILADELPHIA COUNTY LAND USE CODES PHILADELPHIA COUNTY LAND USE CODES *Sorted by Description Land Use s classify the current use of a property in TReND s public records system, Realty Records. These codes are formatted numerically or in

More information

ECE380 Digital Logic

ECE380 Digital Logic ECE38 igital Logic Flip-Flops, Registers and Counters: Flip-Flops r.. J. Jackson Lecture 25- Flip-flops The gated latch circuits presented are level sensitive and can change states more than once during

More information

ASYNCHRONOUS COUNTERS

ASYNCHRONOUS COUNTERS LB no.. SYNCHONOUS COUNTES. Introduction Counters are sequential logic circuits that counts the pulses applied at their clock input. They usually have 4 bits, delivering at the outputs the corresponding

More information

a a Function, Area Timing, Power, Test b seq c b par c Tangram Program Performance Analyzer Fig. 2. Handshake components: sequencer (left) and paralle

a a Function, Area Timing, Power, Test b seq c b par c Tangram Program Performance Analyzer Fig. 2. Handshake components: sequencer (left) and paralle The Tangram Framework Asynchronous Circuits for Low Power Joep Kessels Ad Peeters Philips Research Laboratories Prof. Holstlaan 4, NL 55 AA Eindhoven, The Netherlands email: fjoep.kessels,ad.peetersg@philips.com

More information

Section D..General Auto Electrical Corporation

Section D..General Auto Electrical Corporation 43 Section D..General Auto Electrical Corporation 1. LED Based Signal unit GAEC manufacture LED based signaling system for use in electrified and non electrified sections of Indian railways. The exceptional

More information

THE EFFECT OF SLOT SKEWING AND DUMMY SLOTS ON PULSATING TORQUE MINIMIZATION IN PERMANENT MAGNET BRUSHLESS DC MOTORS

THE EFFECT OF SLOT SKEWING AND DUMMY SLOTS ON PULSATING TORQUE MINIMIZATION IN PERMANENT MAGNET BRUSHLESS DC MOTORS Indian J.Sci.Res.1(2) : 404-409, 2014 ISSN : 0976-2876 (Print) ISSN:2250-0138(Online) THE EFFECT OF SLOT SKEWING AND DUMMY SLOTS ON PULSATING TORQUE MINIMIZATION IN PERMANENT MAGNET BRUSHLESS DC MOTORS

More information

TAC I/NETTM MR-AHU-HP. Application Specific Controller

TAC I/NETTM MR-AHU-HP. Application Specific Controller TAC I/NETTM MR-AHU-HP Both the MR-AHU and MR-HP controllers are application specific controllers (ASCs). The intention of the design is to reduce total install cost through pre-engineered control algorithms

More information

Automation Unit TM 1703 ACP Flexible automation and telecontrol

Automation Unit TM 1703 ACP Flexible automation and telecontrol Automation Unit Flexible automation and telecontrol Power Transmission and Distribution Outstanding performance: Automate simply with Highly complex and yet fully transparent automation solutions are not

More information

Proposed Life Cycle Logistics Certification Training Requirements for FY14 and Beyond

Proposed Life Cycle Logistics Certification Training Requirements for FY14 and Beyond roposed Life Cycle Certification Training Requirements for FY14 and Beyond Current FY13 Life Cycle DAWIA Certification Training Requirements Level I Certification 2 CL Modules: BL & Designing for Support

More information

C o a t i a n P u b l i c D e b tm a n a g e m e n t a n d C h a l l e n g e s o f M a k e t D e v e l o p m e n t Z a g e bo 8 t h A p i l 2 0 1 1 h t t pdd w w wp i j fp h D p u b l i c2 d e b td S t

More information

Digital Fundamentals. Lab 8 Asynchronous Counter Applications

Digital Fundamentals. Lab 8 Asynchronous Counter Applications Richland College Engineering Technology Rev. 0 B. Donham Rev. 1 (7/2003). Horne Rev. 2 (1/2008). Bradbury Digital Fundamentals CETT 1425 Lab 8 Asynchronous Counter Applications Name: Date: Objectives:

More information

Acceptance Page 2. Revision History 3. Introduction 14. Control Categories 15. Scope 15. General Requirements 15

Acceptance Page 2. Revision History 3. Introduction 14. Control Categories 15. Scope 15. General Requirements 15 Acceptance Page 2 Revision History 3 Introduction 14 Control Categories 15 Scope 15 General Requirements 15 Control Category: 0.0 Information Security Management Program 17 Objective Name: 0.01 Information

More information

Elements from Another Universe: Understanding the Beauty of the Periodic Table

Elements from Another Universe: Understanding the Beauty of the Periodic Table Elements from Another Universe: Understanding the Beauty of the Periodic Table Learning Objectives: The students will examine the properties of make believe elements, arrange these elements so as to create

More information

Process Mining Framework for Software Processes

Process Mining Framework for Software Processes Process Mining Framework for Software Processes Vladimir Rubin 1,2, Christian W. Günther 1, Wil M.P. van der Aalst 1, Ekkart Kindler 2, Boudewijn F. van Dongen 1, and Wilhelm Schäfer 2 1 Eindhoven University

More information

BIG DATA IN TRANSPORT RESEARCH: LEGAL AND PRIVACY CHALLENGES

BIG DATA IN TRANSPORT RESEARCH: LEGAL AND PRIVACY CHALLENGES BIG DATA IN TRANSPORT RESEARCH: LEGAL AND PRIVACY CHALLENGES P R E S ENTATION T R A F I KF DOR A GE MEETING 2 0 1 5 AALBORG 29 TH OF AUGUST NT K R I S T I A N H E G N E R R E I N A U, K R I SJ TO IHA N

More information

An Ultra-low low energy asynchronous processor for Wireless Sensor Networks

An Ultra-low low energy asynchronous processor for Wireless Sensor Networks An Ultra-low low energy asynchronous processor for Wireless Sensor Networks.Necchi,.avagno, D.Pandini,.Vanzago Politecnico di Torino ST Microelectronics Wireless Sensor Networks - Ad-hoc wireless networks

More information

SCHOOLOFCOMPUTERSTUDIES RESEARCHREPORTSERIES UniversityofLeeds Report95.4

SCHOOLOFCOMPUTERSTUDIES RESEARCHREPORTSERIES UniversityofLeeds Report95.4 SCHOOLOFCOMPUTERSTUDIES RESEARCHREPORTSERIES UniversityofLeeds Report95.4 AcquisitionsandApplications Generic3-DShapeModel: DivisionofArticialIntelligence XShen&DCHogg by February1995 sequencesandrepresentedbythecontrolpointsofab-splinesurface.the

More information

Developments toward a European Land Monitoring Framework. Geoff Smith. Seminar 2 nd December, 2015 Department of Geography, University of Cambridge

Developments toward a European Land Monitoring Framework. Geoff Smith. Seminar 2 nd December, 2015 Department of Geography, University of Cambridge Developments toward a European Land Monitoring Framework Geoff Smith Specto Natura Limited Enable clients to deliver useful, accurate and reliable environmental information from EO. Positioned at the interface

More information

CHAPTER 11 LATCHES AND FLIP-FLOPS

CHAPTER 11 LATCHES AND FLIP-FLOPS CHAPTER 11 LATCHES AND FLIP-FLOPS This chapter in the book includes: Objectives Study Guide 11.1 Introduction 11.2 Set-Reset Latch 11.3 Gated D Latch 11.4 Edge-Triggered D Flip-Flop 11.5 S-R Flip-Flop

More information

Wikipedia Survey First Results

Wikipedia Survey First Results Wikipedia Survey First Results Working Draft Current Version: 0.3 Date: 9 April 2009 Ruediger Glott (UNU-MERIT), glott@merit.unu.ed Philipp Schmidt (UNU-MERIT), schmidt@merit.unu.edu Rishab Ghosh (UNU-MERIT)

More information

Outline. Clouds of Clouds lessons learned from n years of research Miguel Correia

Outline. Clouds of Clouds lessons learned from n years of research Miguel Correia Dependability and Security with Clouds of Clouds lessons learned from n years of research Miguel Correia WORKSHOP ON DEPENDABILITY AND INTEROPERABILITY IN HETEROGENEOUS CLOUDS (DIHC13) August 27 th 2013,

More information

Master/Slave Flip Flops

Master/Slave Flip Flops Master/Slave Flip Flops Page 1 A Master/Slave Flip Flop ( Type) Gated latch(master) Gated latch (slave) 1 Gate Gate GATE Either: The master is loading (the master in on) or The slave is loading (the slave

More information

Opis przedmiotu zamówienia - zakres czynności Usługi sprzątania obiektów Gdyńskiego Centrum Sportu

Opis przedmiotu zamówienia - zakres czynności Usługi sprzątania obiektów Gdyńskiego Centrum Sportu O p i s p r z e d m i o t u z a m ó w i e n i a - z a k r e s c z y n n o c i f U s ł u i s p r z» t a n i a o b i e k t ó w G d y s k i e C eo n t r u m S p o r t us I S t a d i o n p i ł k a r s k i

More information

DHL EXPRESS CANADA E-BILL STANDARD SPECIFICATIONS

DHL EXPRESS CANADA E-BILL STANDARD SPECIFICATIONS DHL EXPRESS CANADA E-BILL STANDARD SPECIFICATIONS 1 E-Bill Standard Layout A B C D E F G Field/ DHL Account Number Billing Customer Name Billing Customer Address Billing Customer City Billing Customer

More information

Serial port interface for microcontroller embedded into integrated power meter

Serial port interface for microcontroller embedded into integrated power meter Serial port interface for microcontroller embedded into integrated power meter Mr. Borisav Jovanović, Prof. dr. Predrag Petković, Prof. dr. Milunka Damnjanović, Faculty of Electronic Engineering Nis, Serbia

More information

Data Transmission Control Line Intermodule Exchange Interface, Advantages and Disadvantages

Data Transmission Control Line Intermodule Exchange Interface, Advantages and Disadvantages IMPLEMEPITATI ON AND ANALYS IS OF THE TRIrtOSBUS SELF-CLOCKIFJG INTERFACE V. I. Varshavskii, V. B. Marakhovskii, L. Ya. Rozenblyum, and A. V. Yakovlev Avtomatika i V ichislitel 'naya Tekhnika, Vol. 19,

More information

路 論 Chapter 15 System-Level Physical Design

路 論 Chapter 15 System-Level Physical Design Introduction to VLSI Circuits and Systems 路 論 Chapter 15 System-Level Physical Design Dept. of Electronic Engineering National Chin-Yi University of Technology Fall 2007 Outline Clocked Flip-flops CMOS

More information

Sequential Circuits. Combinational Circuits Outputs depend on the current inputs

Sequential Circuits. Combinational Circuits Outputs depend on the current inputs Principles of VLSI esign Sequential Circuits Sequential Circuits Combinational Circuits Outputs depend on the current inputs Sequential Circuits Outputs depend on current and previous inputs Requires separating

More information

026-1728 Rev 0 25-AUG-2011. ipro HVAC and Lighting Installation and Operation Manual

026-1728 Rev 0 25-AUG-2011. ipro HVAC and Lighting Installation and Operation Manual 026-1728 Rev 0 25-AUG-2011 ipro HVAC and Lighting Installation and Operation Manual Retail Solutions 3240 Town Point Drive NW, Suite 100 Kennesaw, GA 30144 Phone: 770-425-2724 Fax: 770-425-9319 Table

More information

Flip-Flops and Sequential Circuit Design. ECE 152A Winter 2012

Flip-Flops and Sequential Circuit Design. ECE 152A Winter 2012 Flip-Flops and Sequential Circuit Design ECE 52 Winter 22 Reading ssignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7.5 T Flip-Flop 7.5. Configurable Flip-Flops 7.6

More information

Flip-Flops and Sequential Circuit Design

Flip-Flops and Sequential Circuit Design Flip-Flops and Sequential Circuit Design ECE 52 Winter 22 Reading ssignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7.5 T Flip-Flop 7.5. Configurable Flip-Flops 7.6

More information

recent)algorithmcalledbdm.bdmskipscharactersusinga\suxau-

recent)algorithmcalledbdm.bdmskipscharactersusinga\suxau- 1Dept.ofComputerScience,UniversityofChile.BlancoEncalada2120,Santiago, ABit-parallelApproachtoSuxAutomata: FastExtendedStringMatching Abstract.Wepresentanewalgorithmforstringmatching.Thealgorithm,calledBNDM,isthebit-parallelsimulationofaknown(butomaton"whichismadedeterministicinthepreprocessing.BNDM,in-

More information

STATE OF WASHINGTON DEPARTMENT OF FINANCIAL INSTITUTIONS DIVISION OF CONSUMER SERVICES INTRODUCTION I. FACTUAL ALLEGATIONS

STATE OF WASHINGTON DEPARTMENT OF FINANCIAL INSTITUTIONS DIVISION OF CONSUMER SERVICES INTRODUCTION I. FACTUAL ALLEGATIONS 1 2 1 1 1 IN THE MATTER OF DETERMINING Whether there has been a violation of the Consumer Loan Act of Washington by: PENSIONS, ANNUITIES AND SETTLEMENTS, LLC, STATE OF WASHINGTON DIVISION OF CONSUMER SERVICES

More information

IMPLEMENTING INTRANET/EXTRANET Estimate of cost Feasibility check

IMPLEMENTING INTRANET/EXTRANET Estimate of cost Feasibility check IMPLEMENTING INTRANET/EXTRANET Estimate of cost Feasibility check Synopsis Whether Firms/Organisations decide to install Intranet, they perceive it as appropriate stimulus to improve their production process

More information

Theory and Practice of Using Models of Concurrency in Hardware Design

Theory and Practice of Using Models of Concurrency in Hardware Design Theory and Practice of Using Models of Concurrency in Hardware Design by Alexandre Yakovlev, Professor of Computing Systems Design School of Electrical, Electronic and Computer Engineering University of

More information

FINANCIAL SERVICES BOARD INSURANCE DEPARTMENT

FINANCIAL SERVICES BOARD INSURANCE DEPARTMENT FINANCIAL SERVICES BOARD INSURANCE DEPARTMENT SPECIAL REPORT ON THE RESULTS OF THE LONG-TERM INSURANCE INDUSTRY FOR THE PERIOD ENDED MARCH 6 June 1 SPECIAL REPORT ON THE RESULTS OF THE LONG-TERM INSURANCE

More information

Notes about Small Signal Model. for EE 40 Intro to Microelectronic Circuits

Notes about Small Signal Model. for EE 40 Intro to Microelectronic Circuits Notes about Small Signal Model for EE 40 Intro to Microelectronic Circuits 1. Model the MOSFET Transistor For a MOSFET transistor, there are NMOS and PMOS. The examples shown here would be for NMOS. Figure

More information

Process Mining Based on Regions of Languages

Process Mining Based on Regions of Languages Process Mining Based on Regions of Languages Robin Bergenthum, Jörg Desel, Robert Lorenz, and Sebastian Mauser Department of Applied Computer Science, Catholic University of Eichstätt-Ingolstadt, {firstname.lastname}@ku-eichstaett.de

More information

Child Care Resource Kit celebrate relationships!

Child Care Resource Kit celebrate relationships! K u R C d C b d k f Fu w y Pd by p! u R Cd C g d g b u d yu g p m d fu g f pg m g w Tk yu C g p D Ng kd pg u bk! T y g b fm dy m d md g g p By pvdg ud d ug yu u f D Ng Cg v, yu b pg up g u d g v bf W v

More information

Supporting Information for. Redox Gated Three-terminal Organic Memory Devices: Effect of Composition and Environment on Performance

Supporting Information for. Redox Gated Three-terminal Organic Memory Devices: Effect of Composition and Environment on Performance Supporting Information for Redox Gated Three-terminal Organic Memory Devices: Effect of Composition and Environment on Performance Bikas C. Das 1,2, Rajesh G. Pillai 1,2, Yiliang Wu 3, Richard L. McCreery

More information

Excel Invoice Format. SupplierWebsite - Excel Invoice Upload. Data Element Definition UCLA Supplier website (Rev. July 9, 2013)

Excel Invoice Format. SupplierWebsite - Excel Invoice Upload. Data Element Definition UCLA Supplier website (Rev. July 9, 2013) Excel Invoice Format Excel Column Name Cell Format Notes Campus* Supplier Number* Invoice Number* Order Number* Invoice Date* Total Invoice Amount* Total Sales Tax Amount* Discount Amount Discount Percent

More information

DIGITAL ELECTRONICS. Counters. By: Electrical Engineering Department

DIGITAL ELECTRONICS. Counters. By: Electrical Engineering Department Counters By: Electrical Engineering Department 1 Counters Upon completion of the chapter, students should be able to:.1 Understand the basic concepts of asynchronous counter and synchronous counters, and

More information

Emcient Evaluation of Polynomial Forms*

Emcient Evaluation of Polynomial Forms* JOURNAL OF COMPUTER AND SYSTEM SCIENCES 6, 625--638 (1972) Emcient Evaluation of Polynomial Forms* I~ MUNRO Department of Applied Analysis and Computer Science, University of Waterloo, Waterloo, Ontario,

More information

Hazards associated with the gas system and how to mitigate them

Hazards associated with the gas system and how to mitigate them Hazards associated with the gas system and how to mitigate them Do not enter the gas shack if the rotating red light at the entrance is on. This warns of an oxygen deficiency. In General the Gas Mixing

More information

UNIK4250 Security in Distributed Systems University of Oslo Spring 2012. Part 7 Wireless Network Security

UNIK4250 Security in Distributed Systems University of Oslo Spring 2012. Part 7 Wireless Network Security UNIK4250 Security in Distributed Systems University of Oslo Spring 2012 Part 7 Wireless Network Security IEEE 802.11 IEEE 802 committee for LAN standards IEEE 802.11 formed in 1990 s charter to develop

More information

H ig h L e v e l O v e r v iew. S te p h a n M a rt in. S e n io r S y s te m A rc h i te ct

H ig h L e v e l O v e r v iew. S te p h a n M a rt in. S e n io r S y s te m A rc h i te ct H ig h L e v e l O v e r v iew S te p h a n M a rt in S e n io r S y s te m A rc h i te ct OPEN XCHANGE Architecture Overview A ge nda D es ig n G o als A rc h i te ct u re O ve rv i ew S c a l a b ili

More information

MDM192 MULTI-DROPS DIGITAL MODEM FOR PRIVATE LINE. USER GUIDE Document reference : 9010709-03

MDM192 MULTI-DROPS DIGITAL MODEM FOR PRIVATE LINE. USER GUIDE Document reference : 9010709-03 MDM192 MULTI-DROPS DIGITAL MODEM FOR PRIVATE LINE USER GUIDE Document reference : 9010709-03 If you have questions about the MDM192 or desire assistance, contact ETIC TELECOMMUNICATIONS at the following

More information

What s the Difference? 2 Pipe vs 4 Pipe Fan Coil

What s the Difference? 2 Pipe vs 4 Pipe Fan Coil Head Office Neptronic 400 Lebeau Blvd. Montreal, Quebec, Canada H4N R6 Tel.: (54) -4 Fax: (54) -6 Toll Free: -800-6-08 What s the Difference? Pipe vs 4 Pipe Coil There are many questions that arise when

More information

Elementary Logic Gates

Elementary Logic Gates Elementary Logic Gates Name Symbol Inverter (NOT Gate) ND Gate OR Gate Truth Table Logic Equation = = = = = + C. E. Stroud Combinational Logic Design (/6) Other Elementary Logic Gates NND Gate NOR Gate

More information

Power Reduction Techniques in the SoC Clock Network. Clock Power

Power Reduction Techniques in the SoC Clock Network. Clock Power Power Reduction Techniques in the SoC Network Low Power Design for SoCs ASIC Tutorial SoC.1 Power Why clock power is important/large» Generally the signal with the highest frequency» Typically drives a

More information

Pitfalls in Degree Equivalency

Pitfalls in Degree Equivalency Pitfalls in Degree Equivalency January 7, 2010 Ron Wada, San Francisco, CA Rob Cohen, Columbus, OH Major developments 2008-09 Review of the single source degree rule Other advanced degrees for EB2 the

More information

Flash Solid State. Are we there yet?

Flash Solid State. Are we there yet? Flash Solid State Storage Reliability Are we there yet? Presenter: David Flynn NAND Flash Reliability/Availability y The GOOD: No moving parts Predicable wear out The BAD: Bit error rate increases with

More information

CODES FOR PHARMACY ONLINE CLAIMS PROCESSING

CODES FOR PHARMACY ONLINE CLAIMS PROCESSING S FOR PHARMACY ONLINE CLAIMS PROCESSING The following is a list of error and warning codes that may appear when processing claims on the online system. The error codes are bolded. CODE AA AB AI AR CB CD

More information

Designing and Evaluating an Interpretable Predictive Modeling Technique for Business Processes

Designing and Evaluating an Interpretable Predictive Modeling Technique for Business Processes Designing and Evaluating an Interpretable Predictive Modeling Technique for Business Processes Dominic Breuker 1, Patrick Delfmann 1, Martin Matzner 1 and Jörg Becker 1 1 Department for Information Systems,

More information

Chapter 4 AC to AC Converters ( AC Controllers and Frequency Converters )

Chapter 4 AC to AC Converters ( AC Controllers and Frequency Converters ) Chapter 4 AC to AC Converters ( AC Controllers and Frequency Converters ) Classification of AC to AC converters Same frequency variable magnitude AC power AC controllers AC power Frequency converters (Cycloconverters)

More information

FPGA Design of Reconfigurable Binary Processor Using VLSI

FPGA Design of Reconfigurable Binary Processor Using VLSI ISSN (Online) : 2319-8753 ISSN (Print) : 2347-6710 International Journal of Innovative Research in Science, Engineering and Technology Volume 3, Special Issue 3, March 2014 2014 International Conference

More information

EXISTING MASONRY WALL TO REMAIN (TYP.). EXISTING PARTITION TO REMAIN PROVIDE 3'-3" W. X 8'-0"H. NEW PELLA WINDOWS AS INDICATED ON PLANS. (TYP.

EXISTING MASONRY WALL TO REMAIN (TYP.). EXISTING PARTITION TO REMAIN PROVIDE 3'-3 W. X 8'-0H. NEW PELLA WINDOWS AS INDICATED ON PLANS. (TYP. EXISTING MASONRY WALL TO REMAIN N EXISTING MASONRY WALL TO REMAIN (TYP.). PROVIDE COPPER THROUGH-WALL FLASHING DN EXISTING MASONRY PARTY CHIMNEY AND WALL TO REMAIN (TYP.). EXISTING MASONRY PARTY WALL TO

More information

Standard risks identified during payroll and payroll taxes review

Standard risks identified during payroll and payroll taxes review www.pwc.com Standard risks identified during payroll and payroll taxes review Global Compliance Services Mach 2014 Payroll assessment and payment 1 2 3 Taxation of severance pay upon dismissal by consent

More information

Signaling Solutions. A Complete Portfolio for Optimized Monitoring

Signaling Solutions. A Complete Portfolio for Optimized Monitoring Signaling Solutions A Complete Portfolio for Optimized Monitoring Allen-Bradley quality signaling solutions from Rockwell Automation can help you achieve your plant floor goals with efficient control and

More information

Welcome to Berkeley. Edward A. Lee Chair, Electrical Engineering and Computer Sciences (EECS) University of California, Berkeley.

Welcome to Berkeley. Edward A. Lee Chair, Electrical Engineering and Computer Sciences (EECS) University of California, Berkeley. Welcome to Berkeley Edward A. Lee Chair, Electrical Engineering and Computer Sciences (EECS) University of California, Berkeley Berkeley is a university The Context LBNL Some campus collaborations: Nanosciences

More information

Slide 1. Slide 2. Slide 3. Cable Properties. Passive flow of current. Voltage Decreases With Distance

Slide 1. Slide 2. Slide 3. Cable Properties. Passive flow of current. Voltage Decreases With Distance Slide 1 Properties of the nerve, axon, cell body and dendrite affect the distance and speed of membrane potential Passive conduction properties = cable properties Signal becomes reduced over distance depending

More information

BURST-MODE communication relies on very fast acquisition

BURST-MODE communication relies on very fast acquisition IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 52, NO. 8, AUGUST 2005 437 Instantaneous Clockless Data Recovery and Demultiplexing Behnam Analui and Ali Hajimiri Abstract An alternative

More information

Latest Power Plant Control System

Latest Power Plant Control System Hitachi Review Vol. 52 (2003), No. 2 101 Latest Power Plant Control System Takashi Kamei Takashi Tomura Yoichi Kato OVERVIEW: Along with advances in system component technologies, modern state-of-the-art

More information

COMP 303 MIPS Processor Design Project 4: MIPS Processor Due Date: 11 December 2009 23:59

COMP 303 MIPS Processor Design Project 4: MIPS Processor Due Date: 11 December 2009 23:59 COMP 303 MIPS Processor Design Project 4: MIPS Processor Due Date: 11 December 2009 23:59 Overview: In the first projects for COMP 303, you will design and implement a subset of the MIPS32 architecture

More information

DM54LS260 DM74LS260 Dual 5-Input NOR Gate

DM54LS260 DM74LS260 Dual 5-Input NOR Gate DM54LS260 DM74LS260 Dual 5-Input NOR Gate General Description This device contains two individual five input gates each of which perform the logic NOR function Connection Diagram Dual-In-Line Package TL

More information

PLC Support Software at Jefferson Lab

PLC Support Software at Jefferson Lab PLC Support Software at Jefferson Lab Presented by P. Chevtsov ( chevtsov@jlab.org ) - PLC introduction - PLCs at Jefferson Lab - New PLC support software - Conclusions Electromagnetic Relay Encyclopedia

More information

Rain Sensor "AWS" TYPE CHART and INSTALLATION INSTRUCTION

Rain Sensor AWS TYPE CHART and INSTALLATION INSTRUCTION Typ:.N. 9.N. 9 / /g / / / / / up P X 0/0/0, 9/9 0/9 y pug, 09/90/0 / / / / ( L/U 0 ) /g / / P X /09/0, fm P p, 09/9 0/00 / / / / ( D ) /p / /y P X 9/09/0, fm B / E p, p //0, 09/90/0 / / / / (C / B ) /p

More information

Internet Scale Storage Microsoft Storage Community

Internet Scale Storage Microsoft Storage Community Internet Scale Storage Microsoft Storage Community James Hamilton, 2011/11/30 VP & Distinguished Engineer, Amazon Web Services email: James@amazon.com web: mvdirona.com/jrh/work blog: perspectives.mvdirona.com

More information

CUSCINETTI MONTANTE MAST ROLLERS

CUSCINETTI MONTANTE MAST ROLLERS TIPO A - TYPE A TIPO B - TYPE B TIPO C - TYPE C TIPO BE - TYPE BE TIPO E - TYPE E TIPO AA - TYPE AA TIPO L - TYPE L TIPO F - TYPE F TIPO BT - TYPE BT TIPO BK - TYPE BK 1 TIPO N - TYPE N TIPO W- TYPE W

More information

Zlinx Wireless I/O. Peer-to-Peer and Modbus I/O B&B ELECTRONICS PRODUCT INFORMATION

Zlinx Wireless I/O. Peer-to-Peer and Modbus I/O B&B ELECTRONICS PRODUCT INFORMATION Modular, Customizable Wire Replacement 128 / 256 Bit AES Encryption Software Selectable RF Transmit Power Software Selectable Over-the-air Data Rate Modbus ASCII /RTU Compatible Wide Operating Temperature

More information

Question 6 -6-[+13)= A-7 87 cts'(i)g Question 7 5 x -4= A -1 B 1. Question 8. 1n.1_ -LL7L- A 11 Bt c-20 D 20. QuestioX9 (-+), =

Question 6 -6-[+13)= A-7 87 cts'(i)g Question 7 5 x -4= A -1 B 1. Question 8. 1n.1_ -LL7L- A 11 Bt c-20 D 20. QuestioX9 (-+), = HillSide Christian College Question 1-2+3= Part 1: Short answer: [1 mark each Question 6-6-[+13)= A-s Bs {A D-1 Question 2 2+(-3)= A-7 87 cts'(i)g Question 7 5 x -4= A- Bs c1 /6--r Question 3-2 + (-3)

More information

DATA SHEET. HEF4508B MSI Dual 4-bit latch. For a complete data sheet, please also download: INTEGRATED CIRCUITS

DATA SHEET. HEF4508B MSI Dual 4-bit latch. For a complete data sheet, please also download: INTEGRATED CIRCUITS INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF,

More information

Lecture 11: Sequential Circuit Design

Lecture 11: Sequential Circuit Design Lecture 11: Sequential Circuit esign Outline Sequencing Sequencing Element esign Max and Min-elay Clock Skew Time Borrowing Two-Phase Clocking 2 Sequencing Combinational logic output depends on current

More information