3D Interconnects 3D Enablement Center

Transcription

1 3D Interconnects 3D Enablement Center Accelerating the next technology revolution Annual SEMATECH Symposium Seoul October 27, 2011 Sitaram Arkalgud Director Interconnect/3D IC Copyright 2009 SEMATECH, Inc. SEMATECH, and the SEMATECH logo are registered servicemarks of SEMATECH, Inc. International SEMATECH Manufacturing Initiative, ISMI, Advanced Materials Research Center and AMRC are servicemarks of SEMATECH, Inc. All other servicemarks and trademarks are the property of their respective owners.

2 Outline Background SEMATECH Program SEMATECH 3D Enablement Center 3 November

3 Industry Trends System Drivers o o o o Low and ultra-low power logic with multi-core/multi-modules Dense 3D NVM RAM for Solid-State Disc (SSD) and dense DRAMs (TB) High-level of functional integration (Digital, analog, RF, NVM, DRAM, MEMS, low power displays, ) Faster data transfer needs between modules and between chips System Driven Transitions o o o o 3D FinFETs, III-V FETs, low V dd FETs 3D Flash memories, RRAM, STTRAM System on a Chip (SoC), System in Package (SiP) 3D TSV, photonic interconnects Strong infrastructural needs for all transitions 10/10/2011 3

4 3D TSV Opportunities and Challenges 3D Opportunities Reduced power Improved performance/bandwidth Reduced size New architectures, new functionality ( more than Moore ) Alternative to lithographic 2D scaling ( more Moore ) 3D Challenges TSV technology Design (floor planning, path finding, co-design) Thermal management Stress/reliability Test/yield/cost Infrastructure (supply chain, standards, interfaces, etc.) Tower of Babel 10/10/2011 4

5 Lack of industry-wide readiness in critical areas HVM is unrealistic unless the packaging gaps are addressed now SEMATECH is in a position to play a critical role in this transition 3 November

6 Technology and Supply Chain Partitioning Who will own the MEOL? Dirty tools in wafer fab? Wafer tools in packaging? New hybrid fab module? Yield, cost, interfaces, flexibility, invest? FEOL / Wafer Wafer processing (CMOS, MEMS, RF, memory, ) IDM / Wafer Foundry Device processing, TSV, wafer BEOL, test MEOL / Hybrid Wafer back-side processing, bumping, bonding, de-bonding Where? Carrier bond, thinning, TSV reveal, RDL, test? BEOL / Packaging Package processing (dicing, bonding, molding, ) Packaging house / OSAT Carrier debond, dicing, die/wafer stacking, underfill, overmold, bumping, test 10/10/2011 6

7 TSV-mid: Progressing maturity of processes, tools and materials Process / Materials / Tools Maturity Tier 1 suppliers available. Ready for HVM. Alpha tools. Basic selection of materials and processes. Wafer front-side Si etch, liner / barrier / seed / ECD, CMP Wafer back-side Temp. bonding, wafer thinning, TSV reveal, RDL Packaging De-bonding, bumping, dicing, stacking, etc. 10/10/2011 7

8 TSV-mid: Progressing maturity of processes, tools and materials Process / Materials / Tools Maturity Tier 1 suppliers available. Ready for HVM. Alpha tools. Basic selection of materials and processes. 3D Interconnect Program 3D Enablement Center Wafer front-side Si etch, liner / barrier / seed / ECD, CMP Wafer back-side Temp. bonding, wafer thinning, TSV reveal, RDL Packaging De-bonding, bumping, dicing, stacking, etc. 10/10/2011 8

9 Mission of materials and emerging technologies Develop infrastructure for industry transition from 2D to 3D Infrastructure development: Materials: Identify and down select materials for bonding and underfill Tools/Processes: Develop with suppliers and harden for HVM (Eg: bonding) Mechanisms: Fundamental understanding for manufacturability & scalability Models: Develop approaches to aid characterization and reliability assessment Key modules that enable acceleration of new technologies for manufacturing Core competencies Narrow Options: data driven consensus Standardize methods: data driven benchmarking Minimize cost, risk and avoid duplication Leverage resources from industry eco-system SEMATECH is good at developing consensus on manufacturability issues 3 November

10 Member value Develop robust technology solutions Drive critical equipment evaluations (supplier landscape) Develop critical equipment (tool hardening) Materials, unit process and characterization development Technology Program Module yield and reliability Device interaction Modeling and simulation (electrical and thermo-mechanical) Drive convergence of the materials/equipment solutions Technology roadmaps and standards, including architecture, design, test and application perspectives Work with other parties, including member companies, fabless community, SRC etc., to drive convergence 3D EC Industry consensus building through workshops and forums Assist member company implementation Equipment access Structural module builds 3 November

11 Program organization Core: GlobalFoundries, HP, IBM, Intel, Samsung, TSMC, UMC, CNSE Program Member: Hynix Unit Process TSV Module Thin Bond Metrology Associate Members Atotech, NEXX, TEL, COSAR Module Development Baseline/Yield Device Interaction Reliability Modeling/Simulation Test Vehicles Technology Program Enablement Center Standards Metrology/Inspection Microbumping/bonding Industry gaps Members ADI, Altera, ASE, LSI, NIST, ON, Qualcomm Reference Flows Standards, Specs Unit processes Equipment development Integration Test Structures Early reliability 3 November

12 Broad industry representation in 3D Technology Program Enablement Center IDMs Hynix, IBM, Intel, Samsung ADI, ON Semiconductor Foundries Global Foundries, Samsung, TSMC, UMC Fabless HP Altera, LSI, Qualcomm OSATs ASE Suppliers Atotech, COSAR, NEXX, TEL R&D Partners CNSE/FRMC NIST, SRC Growing member base including OSATs & Fabless companies Key industry sectors and players are represented in the program Big opportunity to drive industry consensus/ readiness Technical capability exists within SEMATECH 3 November

13 SEMATECH survey on gaps in the via-mid ecosystem 12 companies surveyed Aug-Sep 2010: IDMs, foundries, fabless, OSATs High density via-mid applications including interposers, heterogeneous stacking, logic on logic, memory on memory; timeframe Addresses all aspects of via-mid: wafer processing, assembly, reliability, inspection/metrology, design, test Highest priorities for heterogeneous stacking (e.g., wide IO DRAM) shown below Gaps in Standards and Specifications EDA Exchange Formats Partitioning and floorplanning; Logic verification; Power/Signal integrity analysis; Thermal analysis flow; Stress analysis flow; Physical verification; Timing analysis Reliability Reliability test methods Test DFT test access architecture Inspection/metrology TSV voids, defect mapping, microbump inspection and coplanarity Chip Interface Stackable memory pin assignment; Stackable memory physical pinout TSV Keep out area, fill materials, dimensions Thin wafer handling Universal thin wafer carrier Technology Development and Cost Reduction Reliability Criteria; Test methods; ESD Temporary bond/debond cost reduction Materials and release mechanisms cost reduction; Equipment cost reduction TSV Keep out distance/area Microbumping and bonding Pad metallurgy and layer thickness; Bump metallurgy Inspection/metrology Microbump inspection and coplanarity; TSV voids; BWP voids Test Probing microbumps cost reduction 3 November

14 Addressing the challenges Approach Drive consensus on a reference flow (Wide IO DRAM is first case) Agree on common challenges Address through Enablement Center (standards) or Technology Program (technical) Leveraging Partnerships Across SEMATECH Divisions Front End Processing for complex test vehicles and modeling/simulation ISMI for Equipment Maturity Assessments (EMA) and cost modeling Metrology for identifying 3D specific challenges & solutions University Programs SRC (Enablement Center) for 3D reliability and Design Exchange Format standardization CNSE for thermo-mechanical stress modeling, metrology and reliability National Institutes National Institute of Standards and Technology (assignee in 3D) Extensive National Laboratories network through FEP 3 November

15 Program capability Modeling/Simulation 3D, FEP Basic Reliability 3D, CNSE Test Vehicles & 300mm toolset SEMATECH, CNSE Unit Processes, Integration, Package Interactions HVM Readiness Data Models 3D Enablement Center Reference Flow, Standards, Gaps ISMI Cost Modeling Equipment Maturity Assessments 3 November

16 Interconnect Trends Pilot Production Development Bandwidth/Performance/Power Benefits 3D (Mobile) Wide IO DRAM (2013) 2.5D Si Interposer 2.5D FPGA ( ) Heat Sink and memory Logic memo TIM memory memory Si TSV interposer HP Wide IO DRAM Image courtesy: Intel Increased emphasis on power efficient performance Focus is on common process technologies and materials (Eg: wide IO) 3 November

17 Interconnect Trends Pilot Production Development Research Bandwidth/Performance/Power Benefits Bandwidth/Performance/Power + Functionality Benefits 3D (Mobile) Wide IO DRAM (2013) TSV Scaling + 3D Heterogenous integration 2.5D Si Interposer 2.5D FPGA ( ) Heat Sink and memory Logic memo TIM memory memory Si TSV interposer HP Wide IO DRAM Multifunctionality on a 3D Platform Image courtesy: Intel Increased functionality is the next step forward Optical interconnects, MEMS, etc 3 November

18 Outline Background SEMATECH Program SEMATECH 3D Enablement Center 3 November

19 Scope of technical TSV program Integration Passive TSV daisy chains TSV DtW daisy chains Device interactions 65nm and 30 nm planar/non-planar Keep out area Thermo-mechanical modeling/simulation Electrical modeling/simulation Early reliability Materials: Liner, barrier, seed Plating chemistry Bond materials Temporary, tack Permanent Equipment Development Unit Process Development TSV Module Bond Module Thin and handle Backside processing Metrology Infrared Acoustic x-ray techniques Standard techniques Cu-Cu : Voids Cu-Cu : Void Free Force, m Micro-Chevron Strain, mm 3 November

20 TSV-mid: Progressing maturity of processes, tools and materials Process / Materials / Tools Maturity Tier 1 suppliers available. Ready for HVM. Alpha tools. Basic selection of materials and processes. 3D Interconnect Program 3D Enablement Center Wafer front-side Si etch, liner / barrier / seed / ECD, CMP Wafer back-side Temp. bonding, wafer thinning, TSV reveal, RDL Packaging De-bonding, bumping, dicing, stacking, etc. 10/10/

21 TSV FEOL Technology - Example µm x 25 µm TSV Missing barrier/seed at TSV bottom Center void (conformal fill) High overburden More than 1 µm Cu protrusions after 400C ILD deposition µm x 50 µm TSV Void-free bottomup fill Less than 1.5 µm over-burden Optimized plating chemistry and anneals 10/10/

22 Temp Bond/Debond - Example Temporary bonding / de bonding materials and process landscape De-bonding temp (oc) Max Process Temp. of Materials in Bumped Flow Sn-based Solder Liquidus Start Memory User Consensus BCB thermal stability Bumped Thermal Stability of Dicing Tape (desired debond temperature is 25 C) Thermal stability (oc) Max Process Temp. of Materials in Bumpless Flow Bumpless 500 Logic User Consensus Debond Process Zone Debond Thermal Slide-off Chemical de-bond Mechanical de-bond Laser De-bond Adhesive Suppliers A B C D E F G H I 10/10/ SEMATECH Confidential

23 3D equipment capability Bonding Wafer Align/Bond (manual) EVG 540 Wafer Align/Bond (automated) EVG Gemini Die align/bond (automated) SET FC300 3D Metrology Scanning Acoustic Microscope Sonix Thickness Monitor (capacitance) MTII IR Microscope Olympus All Surface Inspection Rudolph AXi935 Access to AFM, SEM, TEM, HRP, etc via ISMI & CNSE TSV RIE TEL Telius SP UD Multicell Cu Plater NEXX Stratus Wafer backgrind Okamoto Wet hood for cleans and chemical thinning TEL Cellesta+ Spin/bake (materials characterization) Brewer Science Tabletop debonder (thermal slideoff) Brewer Science Access to CSR tooling for conventional CMOS processing and metrology 3 November

24 Overview of TSV Mid Learning Vehicles SEMATECH has access to 3 different learning vehicles Comparison of learning vehicles for TSV mid integration 403AZ FEP nm MPW Description Mask set used for 5x25um and 5x50um TSV and FEP device learning vehicle. Multi-project wafer based on licensed 65nm DtW development. Advanced FET macros. process. Ownership SEMATECH 3D division SEMATECH FEP division SEMATECH 3D division / CNSE Design layers / Process routes TSV, M1, BS metal, DtW (optional) FEOL, CA, TSV, M1, M2 (optional), BS metal FEOL, CA, TSV, M1, low-k BEOL, BS metal TSV electrical macros TSV reliability macros TSV / FET interaction macros TSV chains, combs, Kelvins Very small TSV chains, combs, Kelvins. TSV chains, combs, Kelvins, serps, varying M1/MB line widths, BEOL monitors above some TSV structures, TSV-CA chains Medium-current EM. BTS without well contact. -- Low- / high-current EM, BTS with well contact -- TSV proximity to planar FET, TSV orientation, strain gauges, biased and unbiased TSV. Limited FET process maturity. TSV proximity to planar FET, TSV orientation, biased and unbiased TSV. High FET process maturity. 3 November

25 Integration & reliability AE: 68/chain, 30um linewidth Wet reveal: Yield >>95% Typical TSV Chain Yield Conductance vs. Voltage measurements on TSV comb structure 5x25 with TSV 1472 conductances TSVs. One comb measured shows between very high conductance at comb -10V, possibly and chuck due (100KHz) to a defect in the liner. 1.0E-03 BF (w vias) 1.0E E-05 Liner Integrity Containment of Cu pumping 1.0E Voltage bias 3 November

26 Die to wafer bonding I vs V AV Yielding TSV chains and DtW/TSV chains demonstrated Mean Kelvin resistance of equals unbonded, damascene reference Established capability for evaluating tools, materials, unit processes, modules and reliability MB 10um chains DtW 10um chains 100% 1-99% 0% 3 November

27 Reliability testing capabilities Testing Electromigration, Stress Voiding and TDDB Aetrium Reliability Test Station Limited temperature due to oxidation concerns (~100C) Atmospheric Oven for testing in inert gases Inert gases and modest vacuum, 300C + Qualitau Electromigration unit Thermal Cycling Additional resources for EM, TDDB, SV and most other failure mechanisms 3 November

28 In-house simulation capabilities TSUPREM, MEDICI, and SENTAURUS Model tuned industry standard process & device simulators to support process and device design 1.4 Metal-induced Strain TiN : 10nm HfSiO : 3nm (EOT : 1.4nm) Boron TED in SiGe Process/physics-based compact model-ufpdb/spice3 for variability study Saturation V t [V] Measured SPICE Channel Length [ m] V DS = 1.2V I d,sat [ma] Matlab for general model development and calculation COMSOL for MEMS/NEMS modeling Atomistic modeling/simulation with partners WL BL PG PD LD VDD LD PD PG 1.5GPa ILD Nit Frequency Poly-Si xx : +187MPa 10nm TiN xx : +93MPa Metal/High-k <SNM> = 90 mv V th [V] SNM [V] Poly/SiO 2 Simulation <SNM> = 78 mv ATDF condition PW APT : B/25keV/1.0e13/7T PW VT : B/15keV/1.0e13/7T SIL Nit : 12.5nm & Etch back LDD : As/5keV/1e15 Halo : B/10keV/3.5e13/30T L gate [ m] 3 November

29 Understanding Cu Protrusions/Pumping in TSVs Micro Raman measurements used for thermomechanical modeling Fundamental understanding is creating the potential to modulate Cu pumping Y Position ( m) Si-Si Raman (cm -1 ) Shift of TSV (post Cu CMP) 2D Stress Map of 5 m Round TSV (post Cu CMP) Cu TSV Si X Position ( m) X Position ( m) Compressive Tensile stress stress (green/blue) (yellow/red) Y Position ( m) <110> direction Early 2010 Late 2010 Distance ( m) 15 Cu Distance ( m) 15 Cu Distance ( m) Distance ( m) Aug 2011

30 Heat dissipation is a key challenge in chip stacking Joule Heating w/o Heat Sink TSV@0.2*I EM Chip 2 Chip 1 Heat Sink Joule Heating with Heat Sink * Vdd=2.0V * Vdd=2.5V Finite elements modeling Assume I EM is 1x10 7 A/cm 2 Current though TSV is 20% of EM current No MOSFET working R tsv =2.45 m, TSV liner =50nm 3 November

31 Outline Background SEMATECH Program SEMATECH 3D Enablement Center 3 November

32 3D Enablement Center: SIA-SEMATECH-SRC SIA Technology Strategy Committee identified 3D as focus area Meet diverse needs of entire industry High performance, mobile, analog, mixed signal, MEMS, fabless, fablite, IDMs Members ASE, Altera, ADI, LSI, NIST, ON Semi, Qualcomm, Hynix, CNSE, GlobalFoundries, Hewlett Packard, IBM, Intel, Samsung, TSMC, UMC Mission: Enable industry-wide ecosystem readiness for cost effective TSV-based 3D stacked IC solutions 10/10/

33 3D EC Focus & Activities Primary focus is on Wide IO DRAM for mobile applications Provide clarity to help identify gaps in standards, specifications, technologies Also explore high performance computing, others Activities: Reference Flow development SEMI Standards and Standards Orchestration Development of Inspection/Metrology specifications Microbump/bond metallurgy specifications Near term university research (SRC) Industry gaps Future programs under consideration: Pathfinding EDA tools Test vehicles

34 SEMATECH survey on gaps in the viamid ecosystem 12 companies surveyed Aug-Sep 2010: IDMs, foundries, fabless, OSATs High density via-mid applications including interposers, heterogeneous stacking, logic on logic, memory on memory; timeframe Addresses all aspects of via-mid: wafer processing, assembly, reliability, inspection/metrology, design, test Highest priorities for heterogeneous stacking (e.g., wide IO DRAM) shown below Gaps in Standards and Specifications EDA Exchange Formats Partitioning and floorplanning; Logic verification; Power/Signal integrity analysis; Thermal analysis flow; Stress analysis flow; Physical verification; Timing analysis Reliability Reliability test methods Test DFT test access architecture Inspection/metrology TSV voids, defect mapping, microbump inspection and coplanarity Chip Interface Stackable memory pin assignment; Stackable memory physical pinout TSV Keep out area, fill materials, dimensions Thin wafer handling Universal thin wafer carrier Technology Development and Cost Reduction Reliability Criteria; Test methods; ESD Temporary bond/debond cost reduction Materials and release mechanisms cost reduction; Equipment cost reduction TSV Keep out distance/area Microbumping and bonding Pad metallurgy and layer thickness; Bump metallurgy Inspection/metrology Microbump inspection and coplanarity; TSV voids; BWP voids Test Probing microbumps cost reduction 3 November

35 Reference Product / Structure / Flow Reference product: Mobile wide I/O DRAM on logic Reference structure Tier 2 Thickness ~ 260 µm Active Face Down Underfill Gap ~ 20 µm µ-bump Pitch ~ µm Reference flow candidate Underfill Gap ~ 80 µm Flip Chip Bump Size ~ <100 um Pitch ~ um BackSide Metal Pitch ~ 5-25 µm Tier 1 Thickness ~ 50 µm Active Face Down TSV Size ~ 5-10 µm Pitch ~ µm Package Substrate Thickness ~ 180 µm Tier 1 Tier 2 to Tier 1 die attach Molding, etc. BGA Bump Pitch ~ 0.65 mm Height ~ 300 um 10/10/

36 Focus applications: Mobile and high performance wide-io applications Computing Wide IO (High Performance) Mobile Wide IO Structure Limitation Thermal Package Height Cost Dependent on design, technology and cooling technique Important Factor Data Band Width (Speed) 64 GB/s 12.8 GB/s Power W 2-20W Interposer Can be used Not Used Structure for Thermal Use Heat Sink and TIM - Structure Heat Sink and TIM memory Logic memory memory memory Si TSV interposer memory memory memory memory Logic 10/10/

37 3D Enablement Center: STANDARDS DASHBOARD One-stop location to identify ongoing standards activities 3D standards activities are currently spread across a wide range of Standards Development Organizations (SDOs) Open for public access and comment Open dialog among members of the standards community Help identify unmet standards needs Encourage participation in standards 10/10/

38 Standards Dashboard wiki 10/10/

39 SEMI 3D Standards Activities MEMS/NEMS Committee 3DS-IC Committee (NA) 3DS-IC Committee (Taiwan) Thin Wafer Carrier TF (Urmi Ray, Raghunandan Chaware) 5175: Guide for Multi- Wafer Transport and Storage Containers for Thin Wafers Carrier wafers Edge trimming (Proposed) Bonded Wafer Stack TF (Rich Allen) 5173: Specification for Parameters for Bonded Wafer Stacks 5174: Specification for Identification and Marking for Bonded Wafer Stacks SEMATECH wafers Inspection and Metrology TF (Chris Moore, Yi-Shao Lai Curt Shannon, David Read) 5269: Guide for Terminology for Measured Geometrical Parameters of Through-Silicon Vias (TSVs) in 3DS-IC Structures 5270: Guide to Measuring Voids in Bonded Wafer Stacks meeting during SEMICON/West 2011 Proposed task forces: Testing (Sam Ku, Roger Hwang, Alex Shu) Middle-end Process (Arthur Chen, Jerry Yang) 10/10/

40 SEMI 3D standards activities MEMS/NEMS Committee - 8 Published Standards Current Activities - 3 New Standards - 4 Revisions SEMI MEMS/NEMS Committee 3DS-IC Committee Wafer Bond (Win Baylies, Rich Allen) MEMS Packaging MEMS Materials Characterization MS1-0307: Guide to Specifying Wafer-Wafer Bonding Alignment Targets MEMS Reliability MS5-0310: Test Method For Wafer Bond Strength Measurements Using Micro-Chevron Test Structures MEMS Microfluidics Terminology 3 November

41 Design Exchange Formats 1 st Requirements Documents Delivered Technical area Driver Stds Body PF Exchange Formats 3D EC Partitioning info, floorplanning info Design design data base compatibility Stress Exchange Formats IMEC? I/P for stress sim + O/P Stress Map Thermal Exchange Formats 3D EC I/P power map + O/P Temp map for timing Power Delivery Network Exchange Format 3D EC Reduced order compact power model SignaI Integrity Exchange Format 3D EC Equivalent of IBIS-like mod for 3D DFT Exchange Formats IMEC To enable Scan/JTAG across tiers 10/10/

42 Industry Wide Consensus Building SEMATECH Workshops on Stress Management For 3D ICs Using Through Silicon Vias March 16, 2010 (Albany NY) July 13, 2010 (SEMICON West; San Francisco, CA); in collaboration with Fraunhofer IZFP October, 2010 (SEMICON Europa; Dresden, Germany); in collaboration with Fraunhofer IZFP March 17, 2011 (ISQED - Santa Clara, California); in collaboration with Fraunhofer IZFP July 14, 2011 (SEMICON West, San Francisco); in collaboration with Fraunhofer IZFP SEMI/SEMATECH 3D Interconnect Challenges and Need for Standards Standards Workshop July 13, 2010 (SEMICON West; San Francisco, CA) Infrastructure July 12, 2011 (SEMICON West; San Francisco, CA) Robust tooling SEMI MS5 - Test Method for Wafer Bond Strength Measurements Using Inter-operability Micro-Chevron Test Structures. Standards Technical Education Program (STEP) Cost models July 11, 2011, SEMICON West; San Francisco, CA Supply chain SEMATECH Workshop on 3D Interconnect Metrology co-ordination July 14, 2010 (SEMICON West; San Francisco, CA) July 13, 2011 (SEMICON West; San Francisco, CA) SEMATECH Workshop on Temporary Bonding and Debonding July 11, 2011 (SEMICON West; San Francisco, CA) September 9, 2011 (SEMICON Taiwan; Hsinchu, Taiwan) Joint SEMATECH/SEMI IC Technology Forum September 9, 2010 (SEMICON Taiwan; Taipei) Ecosystem needs Heterogeneous stacking of Wide IO DRAM on logic is a key application 3D is only way to support bandwidths >12.8 GB/s 2013 is benchmark year for volume production 3 November

43 Summary Interconnect is driving 3D TSV manufacturability Standards/infrastructure readiness Technology development Cost 3D program has industry-wide participation Fabless companies Foundries OSATs IDMs Suppliers Universities National Laboratories 3 November

44 Accelerating the next technology revolution Research Development Manufacturing