Simon McElrea : BiTS

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1 Interconnectology The Road to 3D Mobile Consumer Driven Market This Changes Everything 1 Simon McElrea : BiTS

2 What Is Advanced/3D Packaging? 2 This Is... But So Is This. The level of Hardware Engineering now required to build the miniaturized & wearable devices of tomorrow, is Package Engineering (what Invensas calls Interconnectology).

3 Percent of IC Package Value Add The Packaging Pizza Pie Chart ( ) 100% 90% Wire Bond (Leadframe/Module) 80% IC PACKAGE VALUE TREND Kc bp package value 19% 70% 60% Wire Bond (BGA/CSP) 32% 50% 40% 30% 20% Flip Wafer Chip Level DCA Flip Chip Package 14% 20% 10% 0% 3D TSV $6Bn 10% CAAGR $25Bn 6% CAAGR $59Bn 15% 3 PRISMARK, PIZZA HUT

4 The Value Is In The Flavor, Not The Size of The Slice UTILIZED DIE AREA BY PACKAGE TYPE 2011 Flip Chip 12% Flip Chip 16% DCA/ Wafer CSP 2% FC BGA/ LGA/CSP COF/COG 5% COB 3% DCA/ COF/COG Wafer CSP 4% 4.5% 2016 Leadframe 5% 24% FC BGA/ Leadframe LGA/CSP 22% 8% COB 2% CAAGR % Stacked CSP 24% BOC CSP 17% Wire Bond BGA/CSP 7% Discrete/LED 13% Stacked CSP 26% Kc bp-package3 BOC CSP 14% Discrete/LED 14% Wire Bond BGA/CSP 6% Total: 6.1M m 2 Total: 9.0M m 2 Although the die area per package technology (line loading) is hardly changing, the return on the advanced nodes, flip-chip, stacked-csp, WLP, is growing at 20% CAGR. 4 PRISMARK

5 As The Pie Grows, New Slices Get Added FOUNDRY MIDDLE END OSAT BGA/ CSP FEOL BEOL PKG. ASSY FT 1990s FLIP- CHIP FEOL BEOL RDL Wafer Bumping WL Test PKG. ASSY FT 2000s 3DIC FEOL Via Middle BEOL Micro- Bumping Thin & Reveal Interposer TSV Fab WL-Carrier Assembly 3D WL-Test 2.5D ASSY PKG. ASSY FT 2010s Invensas Focus 2016 $400b+ ~$10b (Largest Growth Segment) $40b+ 5

6 The Middle End Ingredients m 6

7 Long Term Advanced Packaging Roadmap This Makes OSAT Roadmaps Look Like RF Baseband Processor Sensor PMIC 2.5D TSV 20nm Partitioning Cu Pillar C-o-C Memory Cube Package Stacking C-o-C 2.5D GPU + HBM TSV Embedded Die 2.5D TSV 14nm Partitioning APU SoC Deconstruct 3D TSV Heterogeneous Die Stacking Si Photonics Market: Market: Market: Market: Market: FPGA Mobile Network Processors Network Tablet Processors Network Mobile, Tablet Processors Network Mobile, Tablet Time This is a remarkable change from when I was at Amkor (2000- For Controlled Release at the IPC Component Technology Conference 2006). AMKOR 47 Sep-13, R.Huemoeller

8 And It Makes Supply Chain Roadmaps Look Like 1 2 YIKES! Yikes! 8 YOLE

9 And That s The Key MIDDLE END RDL Wafer Bumping WL Test Micro- Bumping Thin & Reveal Interposer TSV Fab WL-Carrier Assembly 2.5D ASSY The adoption curve depends on which players the supply chain (market) permits to own the new value-added elements. History says: it s the model that provides the greatest sourcing flexibility to the end product owners. 9

10 What Are The 3D Drivers? Mobile Consumer Driven Market This Changes Everything 10

11 Mobility The Born Mobile Generation 11

12 and The Internet of Every Thing 12 IDC

13 How Many Things? 10 7 Internet infrastructure servers, networking Cars; appliances PCs; smartphones; tablets; watches; TVs; people; clocks; radios Headsets; peripherals; lights and switches; anything with a battery Tags, tickets Pills 13 GARTNER

14 Yes, Its Exponential My Dear Watson 14 DR. MORRIS CHANG

15 Speaking of Watson By the end of this decade, the equivalent of Watson will fit in our pocket. Dr. John Kelly 15 IBM

16 The New Normal: Lower Semiconductor Content/System 16 GARTNER

17 Front End vs. Back End Growth FOUNDRY BACK END ~5% ~15% 17 GARTNER

18 Your Back End Is Bigger Than You Think And Your Middle End is Huge 18

19 The Killer App That Created Advanced Packaging? Mobile Consumer Driven Market This Changes Everything 19

20 The Mobile Phone, Of Course... The Mobile Phone Drove The Creation of the Stacked-Chip CSP Package, System-in-Package, Package-on-Package, the Wafer- Level & Fan-Out Wafer Level Package, along with a host of CMOS Image & Touch Sensor Packages, MEMS Sensor Packages, and 2.5/3DIC Solutions. 20

21 Advanced 3D Packaging Now Dominates The BOM Macronix: Serial Flash CSP Elpida:LPDDR2 Stacked-CSP Apple: ACPU PoP BRCM: Touchs CSP QCOM: TRX+GPS CSP QCOM: BB Stacked-CSP TI: Touchscreen CSP ST: MEMS Acc. Back SWKS: Quad Band PA SiP SWKS: W- CDMA PA SiP QCOM: Power CSP TQNT: Switch SiP SanDisk: NAND Stacked-CSP Apple/Cirrus: Audio CSP ST: MEMS Acc. TQNT: W- CDMA PA SiP SWKS: LTE PA SiP Apple/Cirrus: Audio CSP Apple: Power Mgmt. CSP BCOM: Wifi Bluetooth SiP 21 APPLE iphone 5s

22 BOM Breakdown (By $) D Packaging (Package on Package & Stacked Die CSP) accounts for over 2/3 of the packaged-ic BOM cost (~$80). 22 TECHINSIGHTS

23 Why The PoP Love Affair? 23

24 Bandwidth (GB/s) Hence The Never-Ending Need For Advanced PoP Wide-IO 3DIC I/O Wide I/O BVA PoP 12.8 Cu-Pillar PoP BGA/TMV PoP PoP: I/O mm Pitch PoP: <400I/O mm Pitch

25 But Why 3DIC? Mobile Consumer Driven Market This Changes Everything 25

26 Why 3D?: It s Mostly About Cost Advanced Silicon Nodes Driving Higher Costs Moore s Law is a Law of Economics. 26

27 But It s Also About Cost Cost of Scaling The cost per fab, R&D cost per node, and design cost per device, grow beyond a tipping point below 20nm. 3DIC design architecture allows technologies to be built at the right node and then stacked, which is much more cost-effective overall, and not exclusive to 2-3 players. 27

28 Its Also About Power Power Efficiency CMOS + TSV Wide IO + TSV stack CMOS + Interposer DDR3 + Interposer 9.64 Hynix 16 Gb LPDDR3 + POP Micron2Gb LPDDR2 + POP 2Gb DDR 3 + DIMM CPU 91 mm DIMM (mw/gbps) Orders Of Magnitude Power Savings (Mobile Battery Life or Data Center Cost) Are Possible in 3DIC 28

29 So Are We There Yet? By ITRS definition, We Are There! Between the FPGA, Memory Cube, Wide-IO and Interposer-based products we are at this inflection point! 29 ITRS

30 30

31 So We Said The Supply Chain Was The Key Indicator INFLECTION 31 GARTNER

32 3DIC Equipment LEADING Suppliers POTENTIAL Surveyed SUPPLIERS OF TSV RELATED PROCESS EQUIPMENT Process Step Wafer Thinning/Stress Reduction Via Patterning (Lithography/Stepper) Via Etch (DRIE/Bosch) Laser Drill Stripping/Cleaning Via Fill Barrier/Seed Layers (Deposition/Coating/CVD) Via Fill Plating Stripping/UBM Etch CMP Carrier Bonding Wafer Thin to Expose Vias RDL Dicing Carrier Debonding Die to Wafer Bonding Leading Equipment Providers Disco, TOK, Accretech, Lam EVG, SUSS, ASML, Nikon, Canon, Ultratech, Tamarack, Anvik SPTS, Applied, Lam, Hitachi High Tech, ULVAC ESI, Hitachi, Mitsubishi Applied, Novellus, Lam, Applied, TEL Oerlikon, Novellus, NEXX/TEL, Applied, SPTS, EVG, Hitachi High Tech, EEJA Applied, NEXX/TEL, SPTS, Ebara, Novellus, EEJA Semitool, Lam Applied, Novellus, Ebara, Accretech EVG, SUSS, TOK, AML Disco, TOK, Accretech SUSS, Ultratech, Novellus, EVG, Novellus, NEXX/TEL ESI, Alcatel, Accretech, Disco EVG, SUSS, TOK, ASML Datacon/BESI, Palomar, K&S, PanasonicFA, EVG, ASML, Finetech, Hesse & Knipps, PacTech, Hitachi High Tech, SUSS 32

33 And There Are Now Two Main HVM Market Drivers MEMORY MOBILITY HMC Wide-IO New Enterprise/Storage Standard 1024bit wide, 20x Bandwidth, 20% Power Use, 40/50um pitch TSV. New Mobile DRAM Standard 512bit wide, 1200 I/O per chip, 40/50um pitch TSV& mbumps. 33

34 The 3DIC Market is Of Course Much Broader Than That 34

35 But Who Pays? The IDM, Foundry, Fabless or OSAT? Or Will It Be Apple, Google, Microsoft, Amazon, Facebook, etc.? 35

36 Cost Is Highly Dependent On Agreed POR Flow(s) $3.50 $3.00 $0.71 Interposer First vs. Dies First $0.45 $0.50 Mark, SB, Sing. Int To Sub CUF Int To Sub Bond Die to Int CUF Die To Int Bond $2.50 $2.00 $0.51 $0.45 Substrate-level vs. Wafer-level $0.34 $0.45 TCB vs. Reflow $0.51 $0.35 $0.24 $0.34 $0.35 $1.50 $1.04 $1.04 $1.04 $1.04 $1.00 $0.50 $0.00 $0.35 $0.25 $0.08 $0.05 $0.14 $0.66 $0.19 $0.66 $0.20 $0.08 $0.05 $0.05 $0.66 $0.09 $0.66 $0.10 $0.17 $0.17 $0.17 $0.17 $0.11 $0.11 $0.11 $0.11 TCB TCB TCB TCB Reflow Reflow Reflow Reflow COS COS COW COW COS COS COW COW 27x19 9x9 27x19 9x9 27x19 9x9 27x19 9x

37 3D Process & Cost Chokepoints Micro-Bumping & Bonding Yield Bump Design Alignment Bonding Reliability Thin Wafer Handling Alternative Flows Temp Bonding Schemes Stress Management & Rel. Low stress Alignment Bonding Reliability Thermal Management Thermal Vias Thermal Design TSV Structure Integrity Barrier & Seed Low Stress High AR Reliability Integration 37

38 Copper Transition: It s Always About Copper Bonding Method C4 FC (Contolled Collapse Chip Connect) C2 FC (Chip Connect) TC/LR (Local Reflow) FC TC FC Bond Structure Major Bump Pitch Range at Application > 130 um 140 um ~ 60 um 80 um ~ 20 um < 30 um Bonding Method Conventional Reflow Reflow with Cu pillar Thermal Compression with Cu pillar Thermal Compression Bump Metallurgy Solder (SnAg or SnAgCu) Cu + Solder (SnAg or Sn) Cu + Solder (SnAg or Sn) Cap Bump Collapse Yes No No No Underfill Method - Capillary - No flow - Capillary - No flow - Wafer Level - No flow - Wafer Level - Cu - Metal/Metal - No flow - Wafer Level 38 SEMATECH

39 Invensas: Fun With 3D 39

40 40 Thank You!

41 41

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