Semi Networking Day Packaging Key for System Integration

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1 Semi Networking Day Packaging Key for System Integration Le Quartz, 75 Cours Emile Zola Villeurbanne, France Tel : Fax : Web:

2 Semi Networking Day Christophe Fitamant Sales & Marketing Director, Yole Développement Christophe Fitamant joined Yole Développement in 2013 to lead Média and Sales activities. He holds an engineering degree of INP Grenoble - Phelma - with a major in Chemical Process Engineering. He has worked at IBM Corbeil-Essonnes, and Applied Materials. He s lived in California when he managed the Applied etch product support group for Taiwan and Japan. Back to France for Lam Research he first took the responsibility of the ST Crolles site, before taking the Sales Account Management for Europe. With the acquisition of SEZ in Austria by Lam in 2008, he led Sales and Marketing for Lam penetration in MEMS and Advanced Packaging for Clean Copyrights Yole Développement SA. All right reserved.

3 Fields of Expertise Yole Developpement is a market, technology and strategy consulting company, founded in We operate in the following areas: Photovoltaic Power Electronics Microfluidic & Med Tech Advanced Packaging Our expertise is based on research done by our in-house analysts, conducting open-ended interviews with most industry players. 30+ full time analysts with technical and marketing degrees Primary research including over 3,500 interviews per year HB LED, LED & LD Equipment and materials MEMS & image sensors

4 Yole Activities in a Nutshell MEDIA News feed / Magazines / Webcasts REPORTS Market & technology Patent Analysis Reverse costing report CONSULTING Market research Technology & Strategy Patent Analysis YOLE FINANCE M&A / Due Diligence / Fund raising services Copyrights Yole Développement SA. All right reserved.

5 Semi Networking Day Rozalia Beica Chief Technical Officer, Yole Développement Rozalia Beica is the CTO and Business Unit Manager leading Advanced / 3D Packaging and Semiconductor Manufacturing activities within Yole Développement. For more than 15 years she has been involved in research, strategic marketing and application of WLP and 3D/TSV at materials (Rohm and Haas), equipment (Semitool, Applied Materials, Lam Research) and device manufacturing (Maxim IC) organizations. Rozalia has authored over 50 papers and publications and she is actively participating in several 3D & Advanced Packaging Committees worldwide. Rozalia holds a M.Sc. in Chemical Engineering (Romania), a M. Sc. In Management of Technology (USA) and a GXMBA from IE University (Spain) Copyrights Yole Développement SA. All right reserved.

6 Business Trends in Advanced Packaging Nokia Rozalia Beica SEMI Networking Day: Packaging - Key for System Integration Porto June 27, 2013 Courtesy of Fraunhofer-IZM 2013

7 Presentation Outline Advanced Packaging Platforms Emerging Packaging Technologies FOWLP Market Forecasts Cost Considerations IP Activities Conclusions FCI NXP

8 Introduction The evolution of semiconductor packaging technologies over the past 40 years has been driven by the need to bridge the increasing I/O interconnect gap, between the fast decreasing silicon geometries (Moore s law) and the slower shrink of the Printed Circuit Board technologies Wafer-level-packaging market is gaining more and more significance in the semiconductor industry; it shows the greatest potential for significant future growth in the semiconductor industry. Historically supported by the market growth in flip-chip wafer bumping with electroplated gold, solder bumps and today copper pillars; wafer-level-packages are actually coming in many different, namely Fan-in WLCSP packages, 3D WLP, FO WLP packages, 2.5D Glass / Silicon interposers and of course 3DIC integration with TSV interconnects

9 Wafer shipments (in Munits of 300mm wafers eq.) % penetration Ratio Wafer-Level-Packaging In the semiconductor IC wafer processing industry % Ratio of WW Semiconductor IC Wafers Packaged at the Wafer-Scale (Volume in millions of 300mm wafers eq.) Yole Développement October % 45% 40% 35% 30% TOT Semiconductor IC wafers TOT Wafer-Scale-Packaged IC wafers % ratio 15% 16% 17% 19% 20% 23% 23% 25% 20% 15% 10% 5% 0% CAGR 10% 21% In 2012, ~ 16% of overall semiconductor IC wafers were manufactured with packaging features (bumping, RDL, TSV, etc ) processed at the wafer-scale

10 Advanced Packaging Platforms Wafer-level-packages have emerged in many different varieties that can be categorized into different advanced packaging technology platforms Wafer-Level Interface / Encapsulation PANEL / WLP Platforms Wafer-Level Electrical Redistribution Flip-chip & Wafer-Level Stacking / Integration 3D WLP WL CSP Glass / Silicon FOWLP Embedded die 3D IC WLOptics 2.5D For MEMS & sensors Fan-in Fan-out in PCB / laminate & TSV (also called 3D SiP sometimes) interposers LED & Sensors Flip-chip wafer bumping on BGA Historically supported by flip-chip wafer bumping with electroplated gold & solder bumps, today there are an array of solutions, such as: copper pillars, Fan-in WLCSP packages, 3D WLP, FO-WLP packages, 2.5D Glass / Silicon interposers and 3DIC with TSV interconnects

11 WLP Middle-End Technologies Wafer level packages are true Middle-end technologies, leverage similar type of process manufacturing know-how Middle end technologies are found in the overlap area between the IDMs or CMOS foundries backend of line (BEOL) wafer fabs and the the back-end wafer bumping assembly facilities of the OSATs and wafer bumping houses Middle-end vs Front-End vs Back-End FE wafer manufacturing PVD CMP implant etch inspection cleaning CVD Wafer test TSV RDL / wiring Middle-end Courtesy of Stats ChipPAC BE assembly & test dicing handling thinning BGA C2C / C2S bumping inspection W2W C2W underfill molding Final test Middle-end is a strategic area where Foundries, OSATs, WLP Houses and IDMs stepped in, an infrastructure that has emerged by itself in the last 5 years. Middle-end infrastructure is growing and is the leading driver and the fastest growing semiconductor packaging technology with more than 18% CAGR in units over the next 6 years

12 Technological Differences Packaging applications, as a function of pitch size requirements are divided in flip chip and wafer level packaging. FLIP CHIP Chip on Board COF/COG WAFER BUMPING Silicon on silicon microbumping WAFER LEVEL PACKAGING FC BGA FC CSP FAN IN FAN OUT CHIP EMBEDDIN G Bump characteristics Bump characteristics Bump characteristics Bump characteristics Bump characteristics Plating, screen printing pitch: <180µm Plating, screen printing, stud pitch: < 150µm Plating pitch: <150µm Plating pitch: < 60µm Ball dropping pitch: µm Courtesy of Statschippac Courtesy of 3M Courtesy of SPIL Courtesy of NXP and FCI While flip chip is more economically feasible to smaller size pitches (< 200um), larger pitch size requirements are addressed using embedded technologies

13 Volume (in Munits of 300mm wafer eq.) Middle-end Infrastructure is Growing «Mid-End» infrastructure the leading driver and the fastest growing semiconductor packaging technology with more than 18% CAGR in units over the next 6 years 40,0 35,0 Global Wafer-Level-Packaging Demand (in Munits of 300mm wafer eq. ) Yole Développement October DIC 3D SiP 30,0 25,0 20,0 15,0 10,0 FO WLP 3D WLP WL CSP 2.5D interposers 5,0 0, Flip-chip Significant growth of 3D Packages: 3D IC, Embedded (3D SIP and FOWLP) and Interposers

14 Sales forecasts (M$) $4 000 M $3 500 M Equipment Market Needs for WLP Global Equipment Market Forecast for 3DIC & Wafer-Level-Packaging (in M$) Yole Développement October DIC TSV stacks $3 000 M FO WLP / SiP $2 500 M $2 000 M $1 500 M $1 000 M $500 M 3D WLP Fan-in WL CSP 2.5D interposers Flip-chip wafer bumping $0 M TOT $867 M $642 M $863 M $1,204M $1,721M $2,578M $3,782M 28% In 2012, the equipment market is lower compared to the market in 2011 due to the high investment made in 2011 for 3D IC & WLP applications

15 Sales forecasts (M$) Materials Market Needs for WLP $2 500 M $2 000 M Global Materials Market Forecast Breakdown for 3DIC & Wafer-Level-Packaging (in M$) Global Materials market forecast breakdown for 3DIC & Wafer-Level-Packaging (in M$) Yole Développement October DIC TSV stacks FO WLP / SiP $1 500 M 3D WLP $1 000 M $500 M $0 M Fan-in WL CSP 2.5D interposers CAGR Flip-chip wafer bumping The material market will grow from ~$590M this year to over $2B by 2017 with a CAGR of 23%, driven mainly by the expansion of 2.5D interposers and 3D TSV& WLP platforms

16 Embedded Wafer Level Packaging FOWLP (based on electrical redistribution) PANEL / WLP Platforms Wafer-Level Interface / Encapsulation Wafer-Level Electrical Redistribution Embedded Technologies Flip-chip & Wafer-Level Stacking / Integration 3D WLP WL CSP Glass / Silicon FOWLP Embedded die 3D IC WLOptics 2.5D For MEMS & sensors Fan-in Fan-out in PCB / laminate & TSV (also called 3D SiP sometimes) interposers LED & Sensors Flip-chip wafer bumping on BGA Embedded die in PCB/laminate (based on stacking/integration approach)

17 Market Trends The move to embedded wafer-level-packages Embedded wafer-level-packaging technologies are not new Several players, such as Freescale with RCP, Infineon with ewlb, and Ibiden for die embedding into PCB laminated substrates have developed dedicated technologies and have processed IP in this area for years. Benefits of embedded package integration include: Miniaturization, electrical and thermal performance improvement, cost reduction and simplification of logistic for OEMs 1 st -generation ewlb cross-section (Courtesy of Infineon) Embedded die ibga package (Courtesy of Imbera/Daeduck) Multi-chip SiP Module based on Chip Embedding technology (Courtesy of AT&S) Integrated passive IC ready for embedding into PCB laminate (Courtesy of NXP/FCI)

18 Concepts for FOWLP/Embedded Die in Package Two types of Embedded Wafer-level-packages are emerging FOWLP is based on a reconfigured molded wafer infrastructure Embedded die in package is based on a PCB type of panel infrastructure NANIUM AT&S Courtesy of AT&S Embedded die Single chip FO MCP FO PoP Embedded MCP Embedded PoP FOWLP 1 st generation FO SiP Embedded SiP

19 Fan-out WLP NANIUM 2013

20 FOWLP Cost Motivation to Continue Die Shrinkage! Fan-in WLCSP Wireless SOC 90nm Next CMOS generation Fan-Out WLP PCB 0.5mm pitch Wireless SOC 45nm FC-CSP, WB/FC-BGA PCB 0.5mm pitch Wireless SOC 65nm Next CMOS generation PCB 0.4mm pitch Smaller die size Lower front-end cost thanks to more advanced lithography No more interposer substrate/micro-bumps/wb RDL on Fan-Out area provided are sufficient! Higher functionality when moving to Combo(s) Same or even higher pin-counts are possible PCB mother-board need to remain cheap Pitch evolution is typically limited to mm Filling the I/O gap between IC and PCB evolution Some restrictions are appearing at the package level, since global chip trends tend toward smaller chip areas with an increasing number of interconnects: so the shrinkage of the pitches and pads at the chip/package interface is happening much faster than the shrinkage at the package/board. As a result: FC-CSP, WB/FC-BGA package cost is increasing fast with I/O density (mainly due to interposer substrate cost) Fan-in WLCSP are substrate-less but face inherent limitations due to available die area for re-routing Fan-out WLP has the potential to realize any number of interconnects with standard pitches at any shrink stage of the wafer node technology

21 FOWLP Thickness Motivation WB-BGA 0.8mm PMU chip Fan-Out WLP PMU chip 0.55mm PCB 0.5mm pitch PCB 0.5mm pitch I/O pads are all located at the center of the die Front-end IC design constraint! Issues are: package height (necessary for Wire- Bonds) and thermal dissipation (flip-chip packages would be better) No Wire-Bond Lower package height Better heat dissipation FC configuration No more interposer substrate/micro-bumps/wb RDL on Fan-Out area provided are sufficient! Meeting with new form factor and package performance Some specific Power Management Units (PMU) have > 120 I/Os pads, all located at the center of the PMU chip due to specific IC design reasons. Using Wire Bonds takes a lot of height to connect the chip to the UFBGA substrate Move to FC-BGA/FOWLP First simulations show that electrical performance and heat dissipation are expected to be better than WB-BGA/FC-BGA configurations (please see next slides)

22 Expected Fan-Out WLP Technology Benefits Fan-out Wafer Level Packages like ewlb offer the following differentiated advantages Over flip-chip BGA: Slightly smaller footprint (clearance distances to the edges are smaller) Thinner package Substrate-less package (shorter interconnections meaning higher electrical performance and cheaper in the long run) Future potential for SiP and 3D integration Lower thermal resistance Simplified supply chain infrastructure Over fan-in WLCSP: Higher board-level reliability Fan-out area to counter the pad limitation issue, adaptable to customer needs Only confirmed good dice are packaged Potential for SiP integration Lower thermal resistance Built-in back-side protection No restriction in bump pitch Fan-Out WLP IC FC BGA IC Fan-in WLCSP IC

23 First ewlb Package in High-Volume Production! First design win for ewlb In early 2009, Infineon (GE) was the first company to commercialize its own ewlb packaging technology in an LGE cell-phone ASE and STATSChipPAC are qualified as subcontractors for ewlb manufacturing Infineon s chip is a wireless baseband SOC with multiple integrated functions (GPS, FM radio, BT) The same ewlb product is in production in some Nokia handsets since 2010 The first ewlb package with Infineon s wireless Baseband SOC was found in an LG cellphone (Reverse Engineering pictures courtesy of SystemPlus Consulting and Binghamton University )

24 BGA vs. FOWLP Cost Structure* * For a reference scenario of 64 I/Os, 0.4mm pitch, same IC application Depreciation of equipments 25% WB BGA package WB BGA Package - Cost structure scenario in Test 25% Test 15% FO WLP package FOWLP Package - Cost structure scenario in Assembly Process + Materials (wire bonds, die attach, molding ) 20% Substrate 30% Depreciation of equipments 30% Materials Direct / Indirect (mold compound, passivation resists, chemistries and cleaners) 55% BGA packaging technology has today reached a maturation point where it is difficult to scale the cost down further. On the other hand, FOWLP platform has a new value proposal because: Substrate, Wire bonds, underfill and µ-bumps are removed Reduced cost and no more substrate inventories! The BOM Bill Of Materials is likely to aggressively scale down in cost with time, thanks to Standardization of new material selection (mold compound, passivation resists, chemistries & cleaners, etc.) Amortization of the infrastructures (linked to new equipment introduced) Combinations and synergy between Wafer Test/Final Test procedures

25 Price per pin (c$) FOWLP Cost Model (2012 Data Update) FC BGA QFN WL CSP 300mm FOWLP double RDL 300mm FOWLP single RDL WB-BGA Pin count # FOWLP is now a lower-cost package platform than any competing flip-chip solution The FOWLP cost position ( $/IO) is a clear advantage compared to flip-chip packages today However, the application window is still quite narrow (between IOs only) and there s strong restriction in terms of chip to package IC co-design environment only a few companies are mature enough to design their chip/package for FOWLP at this early stage

26 FOWLP Cost Analysis Conclusion There is no barrier to entry for FOWLP from the end-user perspective, as it is estimated that FOWLP manufacturing cost will be reduced by 2-2.5x in a five-year time frame between , thanks to several different factors: FOWLP Cost/die* $0.5 $ mm FOWLP Yield, test and productivity of FOWLP lines will rapidly increase with time Production volume will increase dramatically with time Depreciation of the infrastructure with time New infrastructure will emerge for PANEL 300mm FOWLP * for a reference scenario FOWLP manufacturing using Gen2 LCD display old fabs $0.20 $ x Cost reduction! PANEL FOWLP 470mmx370mm

27 FO-WLP Revenues (M $) FOWLP Activity Market Evolution & Forecast FOWLP activity revenues (M$) Overall evolution since ewlb technology introduction $700M $600M Yole Developpement October 2012 Ramp-up with fab-less wireless IC players and wide FOWLP infrastructure/supply-chain $500M $400M $300M $200M Intel Mobile/ IFX ewlb driven Transition phase CAGR ~ 0% $100M $0M F 2013F 2014F 2015F 2016F 2017F 2018F 2019F 2020F TOT FOWLP (M$) $13M $48M $75M $107M $114M $107M $118M $195M $280M $374M $477M $571M $641M

28 Device count (Munits) FOWLP Unit Forecast Shipment by Industry FOWLP Forecast Shipment (Munits): Breakdown by industry Yole Developpement October D Stacked DRAM D Stacked NAND Flash MEMS / Sensors Logic 3D SiP / SoC RF, Power, Analog & Mixed signal Beyond digital wireless SOC applications (APE/BB, BB, ASICs, FPGA, etc.), FOWLP market demand will be driven by very different application fields, such as RF, Analog, MEMS and stacked memory markets

29 No. of Patent Families Overall Trend of Patent Filing in the Domain Preliminary remark: for all of the evolution charts, the data corresponding to the years 2010 and 2011 may not be complete, since a significant number of patent applications filed during those years might not have been published yet Patent filing trends for FOWLP technologies Yole Developpement July Priority Years The FOWLP technological area has picked up significantly only in recent years, coinciding with the need to meet future device packaging requirements

30 Evolution of Top 10 Assignees for FOWLP Patents Evolution of top 10 assignees for FOWLP patents (includes related and relevant) ACE (TW) Yole Developpement July INFINEON (GE) SAMSUNG (KR) STATS CHIPPAC (SG) TESSERA (USA) Priority Years Up to Bubble size represent number of Patent Families ASE (TW) FREESCALE (USA) MICRON (USA) MEGICA (TW) QIMONDA (GE) In recent years (i.e. from 2005), most players have increased their focus on innovation Exceptions: Tessera and Micron, whose filings in the last few years have decreased

31 Most Patented FOWLP Steps and Most Active Assignees Yole Developpement, July 2012 RDL (multiple) 14 Bump 11 Singulation KGD 1 Contact pad 3 Die placement - Carrier 47 Basic step RDL (single) Most active assignee ACE, Tessera Die placement - Carrier ACE Encapsulation Infineon, Tessera RDL (multiple) Freescale Bump Infineon RDL (single) 58 Bonding 10 Bonding Passivation Contact pad Amkor Infineon, ST, ACE Infineon Passivation 3 Carrier Debonding 1 Encapsulation 29 Singulation, KGD Carrier Debonding Samsung Infineon Most efforts are dedicated to RDL (to improve signal redistribution), die placement (to limit die shift issue) and encapsulation (to reduce CTE mismatch)

32 FOWLP Conclusions FOWLP is a new packaging platform offering new solutions towards integration and miniaturization (10um line/space, reduced package thickness < 0.5mm, etc.) FOWLP technology basically extends the concept of wafer scale packaging to many new applications that are today packaged in BGA and WL CSP packages. Key applications driving initial FOWLP volume demand will be wireless basebands, RF transceivers and power management units. Other applications include stacked memories and analog-specific ICs such as audio codec, MEMS & Sensors, network switches, etc. A new production infrastructure and opportunity to scale packaging cost down by: Increasing wafer diameter (300mm) and moving to PANEL size Decreasing importance of material volume in general (as substrate is removed) Simplifying the manufacturing infrastructure Optimizing supply chain, inventory and cycle times Value chain consolidation Main challenges facing FOWLP are: CTE mismatch on bigger package dimensions > 8x8mm (target are 10x10mm, 12x12mm) Cost and market acceptance Co-design tool implementation Manufacturing yield improvements (70% 80% 95-98%) Testing approach is yet to be defined (the ultimate goal being to realize the Wafer Test and Final Test in the same infrastructure) Development of 2 nd -generation FOWLP with multi-die and double-side RDL to enter in the 3D SiP dimension

33 Thank you! 2013

34 Yole Activities in a Nutshell MEDIA News feed / Magazines / Webcasts REPORTS Market & technology Patent Analysis Reverse costing report CONSULTING Market research Technology & Strategy Patent Analysis YOLE FINANCE M&A / Due Diligence / Fund raising services Copyrights Yole Développement SA. All right reserved.

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