A New Voltage Control Method for Single-Phase PWM Inverters

Transcription

1 ITB J. Eng. Sci., Vl. 43, N. 2, 2011, A New Vltage Cntl Methd f Single-Phase PWM Invetes Pekik Ag Dahn 1 & Een Tayana 2 1 Schl f Electical Engineeing and Infmatics, Institute f Technlgy Bandung, Bandung, Indnesia 2 Depatment f Electical Engineeing, Univesity f Jendeal Achmad Yani, Bandung, Indnesia Abstact. A new vltage cntl methd f single-phase full-bidge PWM invetes that having an utput C filte is ppsed in this pape. The ppsed vltage cntlle has a capability t ealize a ze steadystate utput vltage e with fast espnse. The ze steady-state utput vltage e is achieved by using a cntlle that is deived by using the vitual C esnant cicuit. Fast espnse is btained by using a vitual esistance that is cnnected in paallel with the filte capacit. The validity f the ppsed methd is veified by expeimental esults. Keywds: PWM invete; vitual C; vitual esist. 1 Intductin A single-phase full-bidge PWM invete is cmmnly used in lw and medium pwe uninteuptible pwe supplies (UPS). In such applicatins, a fast and accuate utput vltage cntl unde vaius cnditins is desiable. Vaius cntl techniques wee develped f this pupse [1-6]. Mst f these techniques, hweve, ae difficult t implement and sensitive t paamete vaiatins. At pesent, a ze steady-state utput vltage e is usually btained by using a cmplicated tansfmatin f the phase vaiables int the nes in synchnus tating efeence fame. Such efeence fame, hweve, is nt available in the case f single-phase PWM invetes. A new vltage cntl methd f single-phase full-bidge PWM invetes is ppsed in this pape. The ppsed vltage cntlle has capability t ealize a ze steady-state utput vltage e with fast espnse withut cmplicated tansfmatin. T cntl the utput vltage, a vltage cntl based n new vitual C esnant cicuit is ppsed. By using the ppsed cntl technique, a ze steady-state e can be achieved. In de t impve the utput vltage espnse, a vitual esist is cnnected in paallel with the utput filte capacit. Tw types f vitual esistance ae discussed in this Received Septembe 21 st, 2010, Revised Apil 24 th, 2011, Accepted f publicatin Apil 25 th, 2011

2 140 Pekik Ag Dahn & Een Tayana pape. Expeimental esults shw that the utput vltage f single-phase PWM invete can be cntlled faste and accuately even unde nnlinea lads. 2 Vitual C Resnant Cicuit Figue 1 shws the scheme f single-phase full-bidge PWM invete that is used in this investigatin. An utput C filte is used t minimize the utput hamnics. A standad duble-lps cntlle is used t cntl the invete. An inne cuent lp cntlle is used t cntl the filte induct cuent. The inne cuent cntlle must be much faste than the ute vltage cntlle. A fast cuent cntlle using duble-band hysteesis such as the ne that was ppsed by the auth in [7] is used in this investigatin. It is assumed hee that the cuent cntlle is wking ppely: S that the actual filte induct cuent can be assumed t be the same as the cuent efeence. The ute vltage lp cntlle geneates the cuent efeence f the filte induct cuent. S1 S3 i i E d C i c ad v S2 S4 S1 S2 S3 S4 Gate signal geneat v Vltage cntlle i Cuent cntlle Figue 1 The scheme f PWM invete with the assciated cntlle.

3 A New Vltage Cntl Methd f Single-Phase PWM Invetes141 Figue 2(a) shws the utput side equivalent cicuit f the invete when the filte induct cuent is assumed equal t the efeence cuent. Figue 2(b) shws the blck diagam f the system. Based n the blck diagam in Figue 2(b), the utput vltage espnse can be witten as 1 1 V ( s) I( s) I( s) sc sc (1) whee s is the aplace peat. Based n the filte capacit cicuit in Figue 2(a), the capacit cuent can be btained as belw: I I I (2) c The capacit cuent can be sepaated int tw cmpnents, that is, Ic Ic I c (3) whee I c is the capacit cuent cmpnent that geneates the desied utput vltage and I ~ c is the capacit cuent cmpnent that geneates the utput vltage e. i i C i c ad v I (s) (a) I (s) (b) 1 sc V (s) Figue 2 ad side equivalent cicuit and its blck diagam.

4 142 Pekik Ag Dahn & Een Tayana Figue 3(a) shws the equivalent cicuit that shwing hw the utput vltage e is geneated by the cuent I ~ c. In de t eliminate the steady-state utput vltage e, the cuent I ~ c shuld nt be allwed t flw thugh the filte capacit. The cuent I ~ c will be nt flwing thugh the capacit if a vey lw impedance path is available in paallel with the filte capacit. A vey lw impedance path can be ceated by using a tuned seies C esnant cicuit as shwn in Figue 3(b). Figue 3(c) shws the blck diagam that epesents the system in Figue 3(b). If the C esnant cicuit is tuned at the desied fundamental utput vltage fequency (e.g., 50 Hz) then n 50 Hz cmpnent f I ~ c will flw thugh the filte capacit. Unde this cnditin, n utput vltage e at 50 Hz is geneated. Thus, we need a tuned seies C esnant cicuit that gives espnse nly t the undesied capacit cuent undesied utput vltage cmpnents. The tuned seies C esnant cicuit shuld nt give espnse t the desied capacit cuent desied utput vltage. Such tuned seies C esnant cicuit cannt be ealized by using eal C cmpnents. The equied seies C esnant cicuit can be implemented vitually by using sftwae analg electnic cmpnents. As shwn in Figue 3(c), the input f the vitual C esnant cicuit is the undesied utput vltage cmpnent. This vltage can be btained as the actual utput vltage minus the efeence vltage as shwn in Figue 3(d). Based n Figue 3(d), the utput vltage espnse can be btained as 1 V ( s) C V ( s) - s I ( s) s sc s C C and the e espnse is s s V ( s) V ( s) V ( s) I ( s) (5) s sc s C C whee 1/ C is the esnant fequency f the C cicuit. If the C esnant cicuit is tuned at 50 Hz ( =100 ad/s) then the utput vltage and the e signal at this fequency can be btained fm Eqs. (4)-(5) as belw: (4)

5 A New Vltage Cntl Methd f Single-Phase PWM Invetes143 I ~ c C (a) V V I ~ c C (b) C sc s 2 1 C ~ Ic ( s ) 1 sc V ( s) V ( s) (c) E d S 1 S 3 I C I I c ad V S 2 S 4 S1 S2 S3 S4 Cuent Cntlle V sc s 2 C 1 I I (d) Figue 3 Develpment f vltage cntlle based n vitual C esnant cicuit.

6 144 Pekik Ag Dahn & Een Tayana V j V j (6) V ( j ) V ( j ) 0 (7) Thus, the 50 Hz cmpnent f the utput vltage is equal t the 50 Hz cmpnent f the efeence vltage. The e cmpnent f the utput vltage at 50 Hz is equal t ze. A simila cntlle was develped t cntl the input cuent f PWM ectifies [8-11]. The diffeence is the existence f a diffeentiat in the numeat f cntlle in Figue 3(d). 3 Vitual Resist Thugh a vltage cntlle that is deived by using a vitual seies C esnant cicuit can ealize a ze steady-state utput vltage e at the desied fequency, the cntlle has scillaty espnse as indicated by Eq. (4). A simple way t damp the scillatin is by using a esistance that is cnnected in paallel with the filte capacit. This appach, hweve, cannt be used in because the system efficiency will be sacificed. Figue 4(a) shws the lad side equivalent cicuit when a esist is cnnected in paallel with the filte capacit. Figue 4(b) shws the assciated blck diagam. As it is shwn in this figue, the esist educes the cuent that is flwing int the capacit by a value that is pptinal t the capacit vltage and invesely pptinal t the esistance f the esist. Thus, instead f using a eal esist, the le f esist can be eplaced by a vitual esist. The vitual esist is implemented by using a vltage sens (that is aleady available) and an amplifie with a gain that is invesely pptinal t the esistance. The utput f the amplifie is then used t educe the filte induct cuent as shwn in Figue 4(c). By using this vitual esist, the utput vltage espnse can be witten as V 2 2 sr/ R s s CR s sr C s CR s sr C s V s - I s As it is shwn by Eq. (8), the utput vltage at the desied fequency is still equal t the desied utput vltage but the vitual esistance damps the scillatin. (8)

7 A New Vltage Cntl Methd f Single-Phase PWM Invetes145 I I c I C R ad V I (s) (a) (s) I 1 sc 1 R V (s) (b) E d S 1 S 3 I C I I c ad V S 2 S 4 S1 S2 S3 S4 Cuent Cntlle V sc s 2 C 1 I 1 R I (c) Figue 4 Develpment f vitual esistance t damp the scillatins.

8 146 Pekik Ag Dahn & Een Tayana In Figue 4(c), the vitual esistance espnds t the ttal utput vltage. Thus, the vitual esistance espnds t bth the desied and undesied cmpnents f the utput vltage. We can design a vitual esistance that espnds nly t the undesied (e) cmpnent f the utput vltage. Such vitual esistance is implemented as shwn in Figue 5. By using this vitual esistance, the utput vltage espnse can be btained as s R sc R s V V s s - I s C s R s C C R s C s R s C C R 2 (9) The cntl scheme as shwn in Figue 5 is the ne that will be implemented in the expeimental system. Bth vitual C esnant cicuit and vitual esist can be implemented eithe using analg digital cicuits. s E d S 1 S 3 I C I I c ad V S 2 S 4 S1 S2 S3 S4 Cuent Cntlle V sc s 2 C 1 I I 1 R Figue 5 Scheme f the implemented system.

9 A New Vltage Cntl Methd f Single-Phase PWM Invetes147 4 Expeimental Results In de t veify the ppsed methd, a single-phase PWM invete with the scheme as shwn in Figue 5 was cnstucted. Bipla junctin tansist mdules wee used as the invete switching devices. The dc vltage suce is btained fm a single-phase ac vltage suce by using a single-phase dide bidge ectifie. The dc vltage suce is maintained cnstant at 120 Vdc. The utput vltage f the ectifie is smthed by using a dc filte capacit f 2200 F. The utput filte inductance is 5 mh and filte capacitance is 200 F. The width f the smalle hysteesis band is 0.8 A and the lage hysteesis band is 1.2 A. Thugh the vitual C cicuit can be implemented by using analg cmpnents, a digital implementatin is chsen in this expeimental system. The vitual C is implemented by using a DSP f TMS320C542. The vitual C esnant cicuit is tuned at 50 Hz. The inductance and capacitance f the C esnant cicuit ae 1 mh and 32 μf, espectively. N attempt has been made t ptimize the paametes. The vitual esist is implemented by using analg electnic cmpnents. A vitual esistance f 1 hm was used in this expeiment. A vitual esistance that espnds nly t the utput vltage e signal was used in this expeiment. Figue 6(a) shws the expeimental esult unde esistive lad when the vitual esistance is nt used. The lad esistance was 10 hm. The esult shws that a ze steady-state utput vltage e can be btained by the ppsed vitual C esnant cicuit. As the damping fact is small, scillatins n the utput vltage and cuent and als n the vltage e signal can be clealy bseved. The THD (ttal hamnic disttin) f the utput vltage is 5.3%. Figue 6(b) shws the esult when the vitual esistance is cnnected. The scillatins n the utput vltage and vltage e signal ae suppessed. The THD f the utput vltage is significantly educed t 1.1%. Figue 7 shws the expeimental esults when the efeence vltage is suddenly changed. Withut using the vitual esistance, the actual utput vltage takes me than ne cycle t fllw the efeence ne. When the vitual esistance is used, the utput vltage is able t fllw quickly the efeence vltage. The utput vltage tansient is damped significantly by using the ppsed vitual esistance.

10 148 Pekik Ag Dahn & Een Tayana (a) (b) Uppe: Output vltage (50 V/div: 5 ms/div) Middle: Output cuent (7 A/div: 5 ms/div) we: E signal (50 mv/div: 5 ms/div) Figue 6 Expeimental esults unde esistive lad (a) withut and (b) with vitual esistance.

11 A New Vltage Cntl Methd f Single-Phase PWM Invetes149 (a) (b) Uppe : Refeence vltage (50 V/div : 20 ms/div) we : Actual vltage ( 50 V/div : 20 ms/div) Figue 7 Expeimental esults when the efeence vltage is suddenly changed (a) withut and (b) with vitual esistance.

12 150 Pekik Ag Dahn & Een Tayana Figue 8 shws the expeimental esults unde nnlinea lad. A capacitive dide bidge ectifie was used as the lad. With this nnlinea lad, the lad peidically geneates tansient cnditin. Withut using the vitual esistance, the utput vltage is badly distted because a cntinuus scillatin is geneated. The measued utput vltage THD was 19.4%. When the vitual esistance is used, the scillatin is effectively suppessed. The THD n the utput vltage is significantly educed int 4.2%. (a) (b) Uppe : Output vltage ( 50 V/div : 5 ms/div ) Middle : Output cuent ( 7 A/div : 5 ms/div ) we : E signal (50 mv/div : 5 ms/div ) Figue 8 Expeimental esults unde nnlinea lad (a) withut and (b) with vitual esistance.

13 A New Vltage Cntl Methd f Single-Phase PWM Invetes151 5 Cnclusins A new vltage cntl methd f single-phase PWM invete has been ppsed in this pape. The ppsed utput vltage cntlle is deived based n vitual C esnant cicuit and vitual esist. Vitual C esnant cicuit is used t achieve a ze steady-state e and vitual esist is used t damp the scillatin. Expeimental esults have shwn the validity f the ppsed methd. Extensins f the ppsed cntlle t the applicatins ae unde investigatin. Refeences [1] Haneyshi, T., Kawamua, A. & Hft, R.G., Wavefm Cmpensatin f PWM Invete with Cyclic Fluctuating ads, IEEE Tans. Ind. Appl., 24(4), , July/August [2] Juanne, A.V., Enjeti, P.N. & ucas, D.J., DSP Cntl f High-Pwe UPS Systems Feeding Nnlinea ads, IEEE Tans. Ind. Elect., 41(1), , Feb [3] Rech, C., Pinhei, H., Gundling, H.A., Hey, H.. & Pinhei, J.R., Cmpaisn f Discete Cntl Techniques f UPS Applicatins, IEEE Pwe Elect. Spec. Cnf. Rec., X/00, [4] ee, T.S., Tzeng, K.S. & Chng, M.S., Rbust Cntlle Design f a Single-Phase UPS Invete Using μ-synthesis, IEE Pc. Elect. Pwe Appl., 151(3), , May [5] Deng, H., Ouganti, R. & Sinivasan, D., A Simple Cntl Methd f High-Pefmance UPS Invetes Thugh Output-Impedance Reductin, IEEE Tans. Ind. Elect., 55(2), , Feb [6] Ctes, P., Otiz, G., Yus, J.I., Rdiguez, J., Vazquez, S. & Fanquel,.G., Mdel Pedictive Cntl f an Invete With Output C Filte f UPS Applicatins, IEEE Tans. Ind. Elect., 56(6), , June [7] Dahn, P.A., New Hysteesis Cuent Cntlle f Single-Phase Full- Bidge Invetes, IET Pwe Electnics, 2(5), , [8] Sat, Y. & Kataka, T., A New Cntl Stategy f Vltage-Type PWM Rectifies t Realize Ze Steady-State Cntl E in Input Cuent, IEEE Tans. Ind. Appl., 34(3), , May/June [9] Yda, T. & Fukuda, S., Applicatin f Intenal Mdel Pinciple t Cuent Cntl f Active Pwe Filtes, Cnf. Rec. IPEC-Tky, pp , [10] h, P.C. & Pang, G.H.H., High-Pefmance Flux-Based Tw-Degeesf-Feedm Uninteuptible Pwe Supply, IEE Pc. Elect. Pwe Appl., 152(4), pp , July 2005.

14 152 Pekik Ag Dahn & Een Tayana [11] Escba, G., Valdez, A.A., Ramz, J.. & Mattavelli, P., Repetitive- Based Cntlle f a UPS Invete t Cmpensate Unbalance and Hamnic Disttin, IEEE Tans. Ind. Elect., 54(1), , Feb