ELEC 204 Digital System Design LABORATORY MANUAL

Transcription

1 ELEC 204 Digital System Design LABORATORY MANUAL : Design and Implementatin f a 3-bit Up/Dwn Jhnsn Cunter Cllege f Engineering Kç University Imprtant Nte: In rder t effectively utilize the labratry sessins, yu shuld read the manual and prepare the experiments befre the sessins.

2 1. Objectives: The purpse f this lab is: 1. T get familiar with the flip-flps 2. T design an up/dwn Jhnsn cunter using D flip-flps 3. T implement the cunter using Xilinx FPGA bard 4. T experimentally check the peratin f the cunter The gal is t design a Jhnsn cunter that can cunt up r dwn, depending n the setting f a cntrl input UP/DOWN. The cunter has an asynchrnus reset (r clear) input which brings the utputs t 0 as sn as the RESET signal is asserted. The cunter cunts at the negative edge f the clck. When the UP input is high, the cunter cunts in ne directin and when UP is lw, it cunts in the ther directin, as shwn in the state transitin diagram. Figure 1: State transitin diagram fr up/dwn cunter. 2. Equipments: Spartan Bard Pentium PC Cables/wires t cnnect them Adapter t supply pwer t Spartan bard

3 2. Preliminary Wrk 1. Review the design prcedure in yur class ntes r the textbk fr cunters. 2. Use the standard cunter design prcess t design this up/dwn cunter with D flip-flps. Ntice that the asynchrnus reset will bring the cunter in a knwn and allwed state (000). a. Give the state transitin table (cnsider the UP signal as an input tgether with the three present states). b. Draw the K-maps fr the three D inputs: D A, D B and D C. c. Give the lgic expressin and lgic diagram f each functin D A, D B and D C. Can yu see similarities between these three functins? d. This state machine will have unused states. In case yu get stuck int ne f these unused states, e.g. state (010), what will the next tw states be, assuming that yu d nt use the reset switch t get back int the starting state: (010) -> (???) -> (???). Is this a self-starting cunter? e. Based n the similarities (r symmetries) f the three functins D A, D B and D C, can yu extend the design t mre bits? Give the expressins f D A, D B, D C, and D D fr a 4-bit Jhnsn cunter. Als draw the schematic in yur ntebk. 3. Sketch the full diagram f the 4-bit Jhnsn cunter (lgic and FF) using negative edge triggered D flip-flps with an asynchrnus reset. Assume that the D flipflps are available as building blcks (yu d nt have t design yur wn flipflp). 3 Experimental Wrk The gal is t enter the schematic f the Jhnsn cunter, t simulate, implement and test the cunter n the FPGA dembard. The clck f the FPGA is very high, therefre yu shuld give the clck by hand. Yu shuld use switches fr this. But there is a prblem abut switches. Due t the mechanical restrictins when yu push the switch, sme glitching effect ccurs as shwn belw figure 2. It is called debuncing. Yu have t use a circuit fr aviding the debunce effect f the switches. Figure 2. Debunce Effect f the switches.

4 In rder t avid thse glitches yu have t implement the circuitry as in figure 3 and use the utput f this circuitry. The circuit wrks like that when yu push the push buttn it utputs a narrw pulse (smaller than 2 pulses f the FPGA clck) withut glitches. Figure 3. Circuit t avid debuncing (glitch effects) In this circuit we will use the 30 MHz clck f the FPGA fr the clck. And a push buttn fr the btn input. The utput f the OR2 is the clck that will be used in the remaining circuit. Create the schematic f the Jhnsn cunter accrding t the design f the pre-lab. Keep the schematic as simple as pssible. If yu can use a macr fr the lgic fr the D inputs, yu shuld d s t keep the schematic frm being cluttered with t many gates and wires. Fr the D flip-flp, use ne f the flip-flps which are available in the Xilinx library (SC Symbls windw). The name f D flip-flps starts with FD. Fr instance, FD is a Lw t High edge triggered (psitive edge triggered) flip flp withut clear (reset) input, FDC is a psitive edge triggered D flip-flp with a clear (reset) input; FDC_1 is a negative edge triggered D flip-flp with a clear input. If yu are nt sure, select the flipflp and a brief descriptin f the flip-flp will appear at the bttm f the SC Symbl windw.

5 Yu will need a clck t advance the cunter. There is a clck inside the PEGASUS bard. But it is t fast yu will use it by adjusting the ucf file f the Xilinx prject fr building Figure 3 and then yur clck will be the utput f OR2 gate in the figure 3. The state f the cunter will be displayed n the 7-segment LED display. Design the decder fr the display r yu may use yur ld design as a macr. Yu may use f the lgic switches as UP/DOWN cntrl and the RESET signal. 4 Assessment Yu have t hand in a lab reprt that cntains the fllwing: Curse Title, Lab title, yur names and date Sectin n the preliminary explaining the design f each blck and giving the answers t each task. Sectin n the lab experiment: a. Brief descriptin f the gals. b. Brief explanatin f the design apprach and the verall schematic. c. Cpy f the schematics (as a screen capture). Label the schematics and cmment n the surce cde. d. Lgic simulatin (screen capture f the wavefrms; label the utputs t prve that the circuit functins prperly). e. Discussin f the results indicating that the circuit functins prperly. Cnclusin and discussin.