Compact Modeling of Non-volatile Memory Devices. M. Sadd, R. Muralidhar and R. Rao 20 September 2004

Transcription

1 Compact Modeling of Non-volatile Memory Devices M. Sadd, R. Muralidhar and R. Rao 20 September 2004

2 Outline Introduction to flash Capacitor sub-circuit and sense model Challenges in Thin film storage model Program/Erase and Endurance 2-bit per cell Reliability Slide 2

3 NVM operates with processes that normally cause failure Example Fe-RAM NVM Process Ferro-Electric Hysteresis Failure Mode V t instability in High-k dielectrics SONOS Charge Trapping in gate stack Fixed Charge instability Flash HCI Programming/ Tunnel Erase Stress-induced trap creation and charging Need to model effects that are minimized in most other devices! Slide 3

4 Flash Cell Over-view Flash Cell most common type of NVM: ONO Layer Tunnel Oxide Control Gate Floating Gate NOR Array: The memory becomes Flash when organized in an array with block erase Slide 4

5 Flash Cell Operations Operation: Sense Model Needs to describe: Variable Threshold voltage Program HCI or Tunneling Erase Tunneling Retention/Disturb Charge loss with bias Slide 5

6 Flash Sense Operation Memory senses the V t shift from stored charge Basic sense circuit Slide 6

7 Flash Sense Model Simple Approach Separate models for program/erase V t More flexible sub-circuit Slide 7

8 Floating Gate Capacitance Model CONTROL GATE V CG V FG C cg FLOATING GATE C fs C mos C fd SOURCE V S V B V D DRAIN V FG = α V + α V + α V + α α g g CG s S = C / C ; C = C + C + C + cg T T cg d fs D fd b V C B mos + Q FG / C T Coupling ratio, α g is critical for tunnel program/erase As α g increases, V FG emulates more the control gate potential Slide 8

9 Flash Sense Model Charge stored on floating node: Q FG ~ C mos V fg + C fs V fg + C fd (V fg -V d ) + C cg (V fg -V cg ) Define coupling ratios: α g = C cg / (C cg + C mos + C fd + C fs ) α d = C fd / (C cg + C mos + C fd + C fs ) Then, V T ~ -Q FG /C cg + (1/ α g ) V T,FG + (α d / α g ) V d Charge of floating node shifts V t Drain coupling to floating gate introduces DIBL Typically α g = and α d ~ 0.1 Slide 9

10 Sense Model: Extraction Extract base MOSFET model by accessing floating gate V g Compare to bit-cell to obtain coupling capacitances V d Requires comparison of two devices subject to mis-match errors V g Extraction with bit-cell alone (e.g. ref) = requires erase or program model V d Slide 10

11 Flash Sense Model: Use Model may only be used for transient simulation Example: Generating an Id-Vg curve 1. Ramp Drain from 0 to Vd 2. Ramp Gate from 0 to Vg 3. Compute Idrain 4. Idrain vs. Vgate Ramp slow enough that transient currents (C dv/dt) ~ 0 Not restrictive: Model used mainly for timing Slide 11

12 Flash Sense Model: DC Model May build a DC Flash model: Control Gate Floating Node Solve for Floating node potential for capacitor subcircuit model Drain See: Y. Tat-Kwan, et. al. IEDM Tech Dig. p. 157 (1994) L. Larcher, et. al. IEEE Trans. Elec. Dev., 49 p. 301(2002) Voltage source sets V fg such that charge Q FG is conserved Slide 12

13 Flash Program/Erase Model Time scales: Read ~ 10 ns Program ~ 1 µs Erase ~ 100 ms Retention/Read Disturb ~ 10 Years Read tightest timing, so most need for circuit simulation Program/Erase May need a circuit model (multi-level storage) Control Gate Floating Node Drain Most models add non-linear resistor or current source Slide 13

14 Floating Gate and Discrete Trapping NVM ONO Interpoly Dielectric Polysilicon Charge Storage Medium (Conductor) Control Gate Nitride Charge Storage Medium (Insulator) Discrete Trapping Memories Silicon Nanocrystal Charge Storage Medium (Isolated Conductors) Silicon Nanocrystal Charge Storage Medium (Isolated Conductors in an Insulator) Floating Gate Gate Poly Gate Poly Gate Poly Source Drain Source Drain Source Drain Source Drain Charges are mobile "Immobile" Charges Si Nanocrystal "Immobile" Charges Si Nanocrystal ~ 100Å Tunnel Oxide Leakage path due to SILC, etc Å Oxide Immobile Charges Nitride 18-70Å Oxide 50-90Å Oxide 40-50Å Oxide 50-90Å Oxide Nitride 40-50Å Oxide Substrate Substrate Substrate Substrate Floating Gate SONOS Nanocrystal NVM Hybrid Slide 14

15 4Mb Memory Array Poly-Si Gate Oxide Nanocrystal Si substrate Number of Bits Erase Program 1.2V 1.8V V (V) g 4Mb Nanocrystal Memory arrays fabricated using 90nm CMOS process technology Slide 15

16 Nanocrystal Memory: Programing 4 3 Vg=6V, Vd=3.5V, Vb=-2V Density = 8e11/cm2 Ave size = 6.2nm Coverage = 23.4% Vt (V) 2 1 Density = 2e11/cm2 Ave size = 12nm Coverage = 25% Time (sec) Density = 1.1e12/cm2 Ave size = 3.6nm Coverage = 11.6% Model needs to account for Nanocrystal characteristics Slide 16

17 FN Erase Model 20 Tunnel Oxide Control Oxide 6 5 ev Vg= -15V NC Sub Vt (V) Vg= -10V Vg= -12V Vg= -14V Vg= -16V Vg= -18V Position (Angstrom) 0 Vg= -18V 1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00 Time (s) WKB Tunneling current from nanocrystal, field dependent gate injection current and Coulomb blockade Model matches experimental results Slide 17

18 Endurance: Floating gate Flash 7 6 Threshold Voltage (V) L09P-D60291 wf14; 6/1.5/6/POX40 P2B; 0.24x0.24 G = 9.3/D = 4.5/ 4.5V = 1us G = -18/ time = 100ms G/D/t AMD : 9.3/4.5/1us G/t AMD: -18V/100ms Number of cycles All injected charge is captured by the Floating gate. No charge transfer through top oxide GC 03/13/03 Vt drift insignificant over life of device Slide 18

19 Endurance: Nanocrystal Memory 7 6 Prog: Vg=6V, Vd=3.5V, Vb=-2V, tp=25µs e- Vt (V) 5 4 Coverage ~ 12% # of P-E cycles Slide 19 Erase: Vg=14V, te=10ms Coverage ~ 23% Vt drift > 1V over life of device due to trapping in top oxide e- e- trap e- e- e- oxide Model needs to keep track of no of P-E cycles and account for charge trapping in stack

20 Nanocrystal Memory: Read disturb of Program State Additive temperature activated component: Eenrgy(eV) x Position (Å) Temp Accessible Defects Possible extrinsic effects Model matches experimental results Slide 20

21 Charge-Trapping NVM: 2 Bit Storage Two bits may be stored: One each above source or drain For large V d, charge over source barrier affects V t more than charge over drain Slide 21

22 Charge-Trapping NVM: 2 Bit Storage A simple circuit model: Forward V t Reverse V t State High High Low Low High Low High Low Two reads (forward & reverse) can store 4 states Slide 22

23 Reliability Model: For Retention and Read Disturb Non-linear current source model charge loss: Integrate in log(t) dq/d(log(t)) = t dq/dt = t I tunnel (V) May calculate long-time loss: Physics of charge loss (tunneling) is lumped into the non-linear current source Slide 23

24 Summary Capacitor sub-circuit foundation for flash model Appropriate for timing simulation May be augmented to model: Program and erase Vt drift due to P-E cycling Reliability (charge loss or gain) Device asymmetry (2-bit storage) Slide 24

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