FLASH memories are the most important of nowadays nonvolatile

Size: px
Start display at page:

Download "FLASH memories are the most important of nowadays nonvolatile"

Transcription

1 2912 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 51, NO. 5, OCTOBER 2004 Charge Loss After 60 Co Irradiation of Flash Arrays G. Cellere, Member, IEEE, A. Paccagnella, Member, IEEE, S. Lora, A. Pozza, G. Tao, Member, IEEE, and A. Scarpa Abstract Flash memories are the most important among modern nonvolatile memory technologies. We are showing new results on the threshold voltage shifts in Flash memory arrays after 60 Co irradiation. A (relatively) high total dose, exceeding 100 krad (SiO 2 ), is needed to induce errors in the array, but threshold voltage shifts are all but negligible even at lower doses. These shifts can be accurately described by using a model which considers the charges generated by irradiation in all the oxides surrounding the floating gate. We are also showing that cycling (endurance) and total ionizing dose effects mutually add. Index Terms Flash memories, radiation effects, semiconductor devices radiation effects, total ionizing dose. I. INTRODUCTION FLASH memories are the most important of nowadays nonvolatile memory technologies [1], [2], featuring extremely high density, good retention properties, and letting the user to electrically write or erase the single bit inside the array [1], [3]. Finally, read and write operations are quite fast, even if not as good as in competing but less mature technologies [1]. All these reasons make Flash memories of great interest for the space and satellite industry. Unfortunately, Flash memories are also a very complex technology, featuring complicated control circuitry [1]. The latter has been demonstrated to be the most vulnerable part of commercial devices during both total ionizing dose (TID) [4] [7] and single event effect (SEE) [7] [10] experiments. In particular, the most radiation sensitive part of commercial Flash memories are the finite state machine used to control the circuit, the output buffers, and the charge pumps used to obtain the high voltages needed for programming and erasing. Because of these results and of the device complexity, the memory array itself has seldom received the attention of the scientific community. In particular, a model was developed by Snyder, et al. [11] to account for charge loss from charged floating gates (FGs) after Co irradiation. The model considers three contributions. The first one is the charge escaping form the FG because of the photoelectric effect (electrons gain enough energy from impinging radiation to jump over the oxide barrier). The other contributions derive from the charge generated in the oxides and surviving recombination. While electrons are quickly swept away, holes will drift toward the FG: part of them will reach it, thus recombining stored electrons (second contribution), while part Manuscript received September 15, 2003; revised February 20, G. Cellere, A. Paccagnella, and A. Pozza are with the Department of Information Engineering (DEI), Padova University, Italy ( giorgio. cellere@ieee.org, paccag@dei.unipd.it). G. Cellere and A. Paccagnella are also with Istituto Nazionale di Fisica Nucleare (INFN), Padova, Italy. S. Lora is with ISOF-CNR, Legnaro, Padova, Italy ( lora@lnl.infn.it). G. Tao and A. Scarpa are with Philips Semiconductor, Nijmegen, The Netherlands ( gioqiao.tao@philips.com; andrea.scarpa@philips.com). Digital Object Identifier /TNS will be trapped in the oxide, resulting in a reduction of threshold voltage (third contribution). Being developed to describe Co irradiation effects, this model did not work to describe the effect of heavy ion irradiation on charged FGs [9], [10]. Its usefulness to describe TID effects in modern technologies is not straightforward. For example, border effects negligible in 47.5-nm-thick gate oxides, such as those used in [11], can be of primary importance in modern technologies, featuring 10 nm (or less) thick tunnel oxides. Further, lateral dimensions of the FG cannot be neglected for a modern technology (but this approximation was acceptable in [11]), and newer devices feature complex sandwiches of SiO and nitride and interpoly (floating gate-to-control gate, FG-to-CG) dielectric. In this paper, we are showing for the first time results of Co irradiation on a modern Flash technology, featuring 8.3 nm tunnel oxide. We are showing that the basic ides beyond Snyder s model are still good for these devices, and we are discussing the mutual effect of irradiation and electrical stress on memories. Thanks to the large statistical set (millions of cells are comprised in a Flash device), we are also giving new insights on the generation and recombination kinetics in oxide-nitride-oxide (ONO) multilayers. II. EXPERIMENTAL AND DEVICES Used devices are 10 Flash memory arrays (2.7 Mbit) manufactured by Philips (Nijmegen, NL), each divided into six blocks. These test (e.g., noncommercial) devices have on-chip decoders, but no sense amplifiers. Therefore, the address selection is on the chip, but no 0/1 output is available. The analog measurements of current and voltages (as well as programming and erasing) are done off-chip with a 1-mV error by using proprietary external equipment at the Philips site. In detail, the of a cell is determined by keeping constant the drain voltage, and sweeping the control gate voltage, until the bit line current reaches a chosen value. In this technology, each Flash memory cell consists of two transistors; one is used to access the cell while the other is a FG transistor, used to store the data. The tunnel oxide thickness is 8.3 nm, while the oxide used as interpoly (that is, separating the FG from the Control Gate, CG) is a sandwich of SiO /Si N /SiO, each 6 nm thick. The total cell area is about 0.6 m and the gate area is about 0.04 m. The cell can be programmed and erased by forcing electrons or holes into the FG, by means of Fowler-Nordheim tunneling through the tunnel oxide. In the 0 state there is an excess of electrons in the FG, so the transistor is high, above 1.7 V. In the 1 state there are holes in the FG, therefore, is lower than 1 V. Irradiations were performed at the ISOF-CNR Co source at LNL-INFN, Padova. Dose rate was kept constant at about /04$ IEEE

2 CELLERE et al.: CHARGE LOSS AFTER Co IRRADIATION 2913 Fig. 1. V cumulative probability plots for 0 and 1 programmed sectors after TID [fresh, 9 krad (SiO ), 27 krad (SiO ), 90 krad (SiO ), 270 krad (SiO ), 900 krad (SiO )]. Fig. 2. Average value of V distribution as a function of total dose, for 0 and 1 programmed sectors. Lines are exponential fits. 12 rad (Si)/s for all irradiations. Devices were kept unbiased during irradiation; nevertheless, a non null electric field was applied across the tunnel oxide because of the charged FG. They were measured a couple of days after irradiation. III. CHARGE LOSS FROM FG: DESCRIPTION AND MODELING In Fig. 1, we show the cumulative probability distributions of before and after irradiation for sectors programmed in the 0 and 1 state after different total ionizing dose (TID) levels (fresh, 9 krad (SiO ), 27 krad (SiO ), 90 krad (SiO ), 270 krad (SiO ), 900 krad (SiO )). Let us consider at first data for devices in the 0 state (high ). As expected, with increasing dose the distributions shift to the left. In fact, electrons and holes are generated in the tunnel and in the interpoly oxide because of irradiation. Part of them will recombine quickly [12], [13]. The remaining electrons will be swept away toward the substrate or the CG, while surviving holes will either reach the FG, where they will recombine part of the stored charge, or will be trapped in the oxide [11]. The net result is the reduction of FG, moving toward the intrinsic (that is, of the FG transistor with no charge trapped in either the tunnel oxide or the FG). A further reduction can be determined by electrons escaping the FG because of energy loss by photons (as happens for UV irradiation used to erase EPROM) [11], but this mechanism has been neglected in the current version of the model. This same description holds true for the devices in the 1 state, apart from reversed oxide field and carrier role (electrons reach the FG, not holes), since in this technology the two logical states are almost symmetrical with respect to the intrinsic FG condition. This is confirmed by Fig. 1, since after 900 krad (SiO ) charge accumulated in the FG is almost null for both logical states. Note that the lower part of the 0 distribution approaches the 1.7 V limit after 90 krad (SiO ), that is, failures in the array are possible (even if not sure) after this dose has been exceeded. For the upper part of the 1 distribution, a larger dose [exceeding 1 Mrad (SiO )] is needed to reach the upper limit (1 V). However, the reduction in the size of the window separating the 1 from the 0 cells leads to reduced noise margin, enhancing the probability of errors during operation, the effect of anomalous SILC [14], and so on. Also note that the slope of the distribution increases for irradiated samples (and with TID). This was Fig. 3. Calculated (lines) and experimental (point) number of electrons (holes) lost from FG as a function of dose. Closed symbols: 0, open symbols = 1, error bars = distributions 0.1 and 99.9% values. See text for details on calculations. expected since in FGs with larger (either positive or negative) the electric field in the oxide is larger, leading to enhanced charge yield, hence to enhanced charge loss [12], [15]. In Fig. 2, we report the average (50%) value of the distributions as a function of total dose. For both 1 and 0 programmed devices, the shift is fitted very well by an exponential law. This fact is important since it is in full agreement with what expected after the model by Snyder [11]. This model can be verified by comparing the number of generated carriers to the charge loss from experimental data, as a function of total dose. This is the subject of Fig. 3, where points are the average values of distributions reported in Fig. 1, and error bars corresponds to the 0.1% and 99.9% extent of distributions. Closed symbols are for 1 programmed sectors, and open symbols are for 0 programmed sectors. All lines reported in this figure are from rather complex calculations, which will be briefly described in the following. A schematic view of a basic FG transistor is reported in Fig. 4 to help the reader. The first characteristic to focus on is the thin continuous line, corresponding to charge loss from electrons or holes generated in the tunnel oxide only.asafirst step, we calculated the energy deposed by radiation in the tunnel oxide. An electron/hole pair is then generated for each ev deposited in the oxide [21]. At our oxide field (evaluated around 1.5 MV/cm in the tunnel oxide, for both 0 and 1 ) about 85% of these carriers will survive and

3 2914 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 51, NO. 5, OCTOBER 2004 Fig. 4. Schematic view of a Flash cell (out of scale). STI = Shallow Trench Isolation. See text for details. reach the FG [13], as depicted by the characteristic (we will discuss later the charge trapped in the oxide). It is evident from Fig. 3 that the charge loss derived from this calculation is by far lower than that found experimentally. Consider also that this plot is by itself an overestimation of the actual number of holes surviving recombination, since, as soon as the first holes reach the FG, the oxide field becomes lower (the oxide field was kept constant in our calculations). The remaining charge loss should derive from electron/hole pairs generated in the ONO multilayer. Charge generation happens only in the two SiO layers, since in the nitride layer the yield is almost zero, thanks to a very high recombination rate [16], [17]. Therefore, we should account for two contributions. The first one is the charge generated in the bottom SiO layer. About 75% of carriers generated in his region will survive and will be injected in the FG. This contribution is depicted by the dotted line in Fig. 3, and is larger than that from the tunnel oxide. The second contribution is the charge generated in the top SiO layer. Thanks to the reduced barrier height of the nitride in comparison to SiO, almost all carriers surviving the recombination (either holes in the 1 state or electrons in the 0 state), will be injected in the nitride and trapped at the SiO /Si N interface ( in Figs. 3 4) [17], [18]. However, if a given number of holes (electrons) are injected from top SiO, that same number of electrons (holes) will be injected from the bottom SiO (in fact, the two layers feature the same thickness and electric field). These carriers can either recombine or be trapped. In both cases, their effect will obviously be negligible. We can evaluate a worst-case scenario: all holes (electrons) generated in the top oxide are injected in the nitride and trapped at the bottom SiO /Si N interface, while no hole (electron) is injected from the bottom oxide. The effect of this sheet charge distribution on apparent charge loss from FG is depicted by the characteristic in Fig. 3, and is negligible in comparison to and (the Y-axis scale in logarithmic). The fourth and most important characteristic reported in Fig. 3 is the thick continuous line, corresponding to the sum of and contributions described earlier. This curve is in extremely good accordance with experimental data for low doses, while it slightly overestimates the charge loss at high doses. This can be the effect of several phenomena, very difficult to accurately model. Among them: Fig. 5. cumulative probability distribution of threshold voltage after 2.7 Mrad (SiO ) as a function of the number of W/E cycles done before irradiation. i) The oxide field decreases during irradiation, thanks to the reduced stored charge. Therefore, charge yield will decrease too: by considering it constant, we are overestimating charge yield (especially at high doses). ii) Border effects, negligible in thick oxides [11], [16] can play an important role in thinner oxides, such as the ones we are dealing with [19]. iii) Some charge loss may locally happen in the high fringing field regions in the shallow trench isolation (STI). iv) Holes and electrons behavior in the oxide is all but equal: both mobility and trapping properties strongly differ. However, no evidence of any asymmetry between the 0 state (holes trapped in the FG, electrons across the oxide) and the 1 (electrons trapped in the FG, holes across the oxide) case can be seen from our data. v) Charge loss because of interaction between stored carriers and photons (which is probably a secondary effect in these conditions) has been neglected. IV. MUTUAL EFFECTS OF CYCLING AND IRRADIATION Among these problems, the effect of holes and electron trapping in the oxide can be discussed looking at the mutual effect of endurance test, that is, performance during write/erase (W/E) cycling, and irradiation. In Fig. 5, we report the distributions of six different sectors from one device. Three couples of sectors were subjected to 20, , and W/E cycles before irradiation. After this step and before irradiation, a sector from each couple was programmed at 0, and the other was programmed at 1. Prerad distributions are shown for two sectors only for clarity (distributions were almost identical among sectors programmed in the same state). The distributions after 2.7 Mrad (SiO ) are also reported. Total dose is in this case quite high; this allows us to fully discharge the FG. As expected, the distributions for the erased and programmed sectors of each couple are very similar (practically superimposed for two couples, and very close for the third). Interestingly, after irradiation the distributions shift toward right when increasing the number of W/E cycles before irradiation. This is related to buildup of defects in the oxide because of the electrical stress. These defects, likely E centers,

4 CELLERE et al.: CHARGE LOSS AFTER Co IRRADIATION 2915 for the 0 state overlap is once again around cycles. This seemingly allows saying that endurance performances are not strongly degraded by irradiation. However, the effect of negative charge trapping is evident in the growing (which rises more steeply for the irradiated sample). This fact may result in more probable error when reading 1 programmed cells, which can exceed the 1-V threshold after a lower W/E cycle count. As previously discussed, this effect can be explained by considering E centers generated by the radiation, which adds to those generated by the electrical stress during W/E cycles, resulting in increased negative charge trapping after cycling in irradiated samples. Fig. 6. Endurance performance for 0 and 1 programmed sectors, nonirradiated device. Values corresponding to the 0.01, 50, 99.99% are reported for both the 1 and 0 programmed sectors. Fig. 7. Endurance performance for 0 and 1 programmed sectors, after 2.7 Mrad (SiO ). Values corresponding to the 0.01, 50, 99.99% are reported for both the 1 and 0 programmed sectors. are then occupied by electrons generated during irradiation [20]. The larger the number of W/E cycles, the larger the number of electrically active defects, and finally, the larger the distribution shift. Also note that from these data the effect of charge trapping is by far lower that than of charge generation. In Figs. 6 and 7, we face the same problem from a different perspective, that is, what happens during endurance experiments in irradiated devices. Fig. 6 reports the typical endurance performance for an unirradiated sample. The evolution of the average (50%) value of the threshold voltage distribution is reported as a function of the number of cycles, for a sector programmed at 0 and for a sector programmed to 1. Further, we also show the values corresponding to the and 0.01% of the distribution; these extreme values represent respectively the low- and high- tails of the distribution, and are of primary importance when applied to a large array (0.01% of cells means more than 3000 cells in a 32 Mbit commercial device!). The 99.99% curve for the 1 state overlap the 0.01% curve of the 0 state after about cycles, that is, almost 100 times more than required for typical reliability projection ( W/E cycles are usually guaranteed for Flash memories). The same graph is reported after 270 krad (SiO ) irradiation in Fig. 7. By comparing the two figures, it is evident that the distributions are not broader for the irradiated sample and that the number of cycles after which the 99.99% curve for the 1 state and the 0.01% curve V. DISCUSSION AND CONCLUSION We have shown, for the very first time, results on the threshold voltage shifts in modern Flash memory arrays after Co irradiation. A total dose in excess of 100 krad (SiO ) is needed to induce errors in the array. Note that this appears somewhat larger than doses typically found for malfunctioning or errors in the control circuitry of similar devices [4], [5] thus explaining why the control circuitry is usually considered the most radiation sensitive part of nonvolatile memories. While this is for sure true, our data show that it is only a partial view of the picture. In fact, corruption of the stored information may endanger the actual reliability of the device under operating conditions well before an error in actually detected. For example, the reduction of the 0 -to- 1 window leads to a reduction of the noise margin. Further, we have shown that cycling (endurance) and TID effects mutually add: irradiation on cycled devices result in enhanced charge trapping, and irradiation leads to a latent damage which is put in evidence by cycling (that is, by electrical stress). In other words, a device subjected to ionizing radiation will be more prone to effects such as the erratic SILC [14]. All these considerations prove that hardening the control circuitry alone might not be enough to ensure proper operation of Flash devices in a radiation environment. The shifts can be accurately described by using an improved model based on that proposed in [11]. The validity of the previous model was not to be taken for granted, due to the technological evolutions of last 20 yr. Among the differences between modern technologies and that used in [11], we underline the reduced FG size, which leads to a lateral dimension of the FG comparable to the planar one. Vertical FG dimension was neglected in [11], where the FGs were some micrometer wide. Further, we have proved that the use of the oxide-nitride-oxide as interpoly dielectric has important implications on the array reliability under ionizing radiation. In fact, only charge generated in the bottom SiO layer of the ONO, that is, in the one closer to the FG, leads to actual charge loss from FG. This could turn into a design issue: once established a good retention performance, a designer could keep as thin as possible the bottom ONO SiO layer (increasing the thickness of the top SiO ), thus increasing the radiation hardness of the device. Two effects considered of primary importance in [11] were neglected in present paper. The first one is charge trapping in tunnel oxide. Given the small thickness of our oxides, this effect appears negligible, and we do not expect it to play a major role

5 2916 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 51, NO. 5, OCTOBER 2004 in future FG technologies. The second and more important one is the direct interactions between charge stored in the FG and impinging radiation. From our data, this phenomenon appears negligible in comparison to phenomena taking place in the oxides. However, further experiments involving other technologies and a larger set of experimental data are needed to definitely assess this point. The electron emission mechanism could, therefore, be an important issue to be added to our model in future. REFERENCES [1] P. Cappelletti, C. Golla, P. Olivo, and E. Zanoni, Flash Memories. Boston, MA: Kluver Academic, [2] S. Lai, Flash memories: Where we were and where we are going, in IEDM Tech. Dig., 1998, p [3] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, Flash memory cells An overview, Proc. IEEE, vol. 85, pp , Aug [4] D. N. Nguyen, C. I. Lee, and A. H. Johnston, Total ionizing dose effects on flash memories, in 1998 IEEE Radiation Effect Data Workshop, pp [5] D. R. Roth, J. D. Kinninson, B. G. Karlhuff, L. R. Lander, G. S. Bognaski, K. Chao, and G. M. Swift, SEU and TID testing of the Samsung 128 Mbit and the Toshiba 256 Mbit flash memory, in 2000 IEEE Radiation Effect Data Workshop, pp [6] S. Bertazzoni, G. C. Cardarilli, M. Salmeri, A. Salsano, G. Bacis, C. Golla, M. L. Longo, F. Desideri, D. Di Giovenale, G. C. Grande, S. Sperandei, M. Ricci, and P. G. Picozza, TID on 16 Mb flash memories in radiation environment, in Proc. RADECS2000, pp [7] D. N. Nguyen, S. M. Guertin, G. M. Swift, and A. H. Johnston, Radiation effects on advanced flash memories, IEEE Trans. Nucl. Sci., vol. 46, pp , Dec [8] H. R. Schwartz, D. K. Nichols, and A. H. Johnston, Single-event upset in flash memories, IEEE Trans. Nucl. Sci., vol. 44, pp , Dec [9] G. Cellere, P. Pellati, A. Chimenton, A. Modelli, L. Larcher, J. Wyss, and A. Paccagnella, Radiation effects on floating-gate memory cells, IEEE Trans. Nucl. Sci., vol. 48, pp , Dec [10] G. Cellere, A. Paccagnella, L. Larcher, A. Chimenton, J. Wyss, A. Candelori, and A. Modelli, Anomalous charge loss from floating-gate memory cells due to heavy ions irradiation, IEEE Trans. Nucl. Sci., pp , Dec [11] E. S. Snyder, P. J. McWhirter, T. A. Dellin, and J. D. Sweetman, Radiation response of floating gate EEPROM memory cells, IEEE Trans. Nucl. Sci., vol. 36, pp , Dec [12] T. P. Ma and P. V. Dressendorfer, Ionizing Radiation Effects in MOS Devices and Circuits. New York: Wiley, [13] G. A. Ausman, Field Dependence of Geminate Recombination in a Dielectric Medium, Adelphi, Harry Diamond Lab. Rep. No. 2097, [14] D. Ielmini, A. S. Spinelli, A. L. Lacaita, and A. Modelli, Statistical modeling of reliability and scaling projections for flash memories, in IEDM Tech. Dig., [15] L. Osanger, Initial recombination of ions, Phys. Rev., vol. 54, p. 554, [16] N. S. Saks, Response of MNOS capacitors to ionizing radiation at 80 K, IEEE Trans. Nucl. Sci., pp , Dec [17] V. A. K. Raparla, S. C. Lee, R. D. Scrimpf, D. M. Fleetwood, and K. F. Galloway, A model of radiation effects on nitride-oxide films for power MOSFET applications, Solid State Electr., vol. 47, pp , [18] H. Aozasa, I. Fujiwara, A. Nakamura, and Y. Komatsu, Analysis of carrier traps in Si N in oxide/nitride/oxide for metal/oxide/nitride/oxide/silicon nonvolatile memories, Jpn. J. Appl. Phys., vol. 38, pp , [19] N. S. Saks, M. G. Ancona, and J. A. Modolo, Radiation effects in MOS capacitors with very thin oxides at 80 K, IEEE Trans. Nucl. Sci., vol. 31, pp , Dec [20] A. J. Lelis, T. R. Oldham, H. E. Boesch Jr., and F. B. McLean, The nature of the trapped hole annealing process, IEEE Trans. Nucl. Sci., vol. 36, pp , Dec [21] J. M. Benedetto and H. E. Boesch, The relationship between Co and 10 kev x-ray damage in MOS devices, IEEE Trans. Nucl. Sci., vol. 33, 1986.

Data retention in irradiated FG memories

Data retention in irradiated FG memories Data retention in irradiated FG memories G. Cellere 1,2, L. Larcher 3,4, A. Paccagnella 1,2, A. Modelli 5, A. Candelori 4 1 DEI, Università di Padova, Padova, Italy 2 INFN, Padova, Italy 3 Università di

More information

Flash Memories. João Pela (52270), João Santos (55295) December 22, 2008 IST

Flash Memories. João Pela (52270), João Santos (55295) December 22, 2008 IST Flash Memories João Pela (52270), João Santos (55295) IST December 22, 2008 João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, 2008 1 / 41 Layout 1 Introduction 2 How they work 3

More information

DUE to their potentially superior electrical and mechanical

DUE to their potentially superior electrical and mechanical 2974 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 59, NO. 6, DECEMBER 2012 Electrical Stress and Total Ionizing Dose Effects on Graphene-Based Non-Volatile Memory Devices Cher Xuan Zhang, Student Member,

More information

Introduction to Flash Memory

Introduction to Flash Memory Introduction to Flash Memory ROBERTO BEZ, EMILIO CAMERLENGHI, ALBERTO MODELLI, AND ANGELO VISCONTI Invited Paper The most relevant phenomenon of this past decade in the field of semiconductor memories

More information

Yaffs NAND Flash Failure Mitigation

Yaffs NAND Flash Failure Mitigation Yaffs NAND Flash Failure Mitigation Charles Manning 2012-03-07 NAND flash is one of very few types of electronic device which are knowingly shipped with errors and are expected to generate further errors

More information

Charge-Trapping (CT) Flash and 3D NAND Flash Hang-Ting Lue

Charge-Trapping (CT) Flash and 3D NAND Flash Hang-Ting Lue Charge-Trapping (CT) Flash and 3D NAND Flash Hang-Ting Lue Macronix International Co., Ltd. Hsinchu,, Taiwan Email: htlue@mxic.com.tw 1 Outline Introduction 2D Charge-Trapping (CT) NAND 3D CT NAND Summary

More information

SLC vs MLC: Proper Flash Selection for SSDs in Industrial, Military and Avionic Applications. A TCS Space & Component Technology White Paper

SLC vs MLC: Proper Flash Selection for SSDs in Industrial, Military and Avionic Applications. A TCS Space & Component Technology White Paper SLC vs MLC: Proper Flash Selection for SSDs in Industrial, Military and Avionic Applications A TCS Space & Component Technology White Paper Introduction As with most storage technologies, NAND Flash vendors

More information

SLC vs MLC: Which is best for high-reliability apps?

SLC vs MLC: Which is best for high-reliability apps? SLC vs MLC: Which is best for high-reliability apps? Here's an examination of trade-offs, with an emphasis on how they affect the reliability of storage targeted at industrial, military and avionic applications.

More information

Lecture 030 DSM CMOS Technology (3/24/10) Page 030-1

Lecture 030 DSM CMOS Technology (3/24/10) Page 030-1 Lecture 030 DSM CMOS Technology (3/24/10) Page 030-1 LECTURE 030 - DEEP SUBMICRON (DSM) CMOS TECHNOLOGY LECTURE ORGANIZATION Outline Characteristics of a deep submicron CMOS technology Typical deep submicron

More information

Flash Memory Jan Genoe KHLim Universitaire Campus, Gebouw B 3590 Diepenbeek Belgium

Flash Memory Jan Genoe KHLim Universitaire Campus, Gebouw B 3590 Diepenbeek Belgium Flash Memory Jan Genoe KHLim Universitaire Campus, Gebouw B 3590 Diepenbeek Belgium http://www.khlim.be/~jgenoe [1] http://en.wikipedia.org/wiki/flash_memory Geheugen 1 Product evolution Jan Genoe: Geheugen

More information

AN1837. Non-Volatile Memory Technology Overview By Stephen Ledford Non-Volatile Memory Technology Center Austin, Texas.

AN1837. Non-Volatile Memory Technology Overview By Stephen Ledford Non-Volatile Memory Technology Center Austin, Texas. Order this document by /D Non-Volatile Memory Technology Overview By Stephen Ledford Non-Volatile Memory Technology Center Austin, Texas Introduction Today s microcontroller applications are more sophisticated

More information

Evaluating Embedded Non-Volatile Memory for 65nm and Beyond

Evaluating Embedded Non-Volatile Memory for 65nm and Beyond Evaluating Embedded Non-Volatile Memory for 65nm and Beyond Wlodek Kurjanowicz DesignCon 2008 Sidense Corp 2008 Agenda Introduction: Why Embedded NVM? Embedded Memory Landscape Antifuse Memory evolution

More information

Long Term Data Retention of Flash Cells Used in Critical Applications

Long Term Data Retention of Flash Cells Used in Critical Applications Office of the Secretary of Defense National Aeronautics and Space Administration Long Term Data Retention of Flash Cells Used in Critical Applications Keith Bergevin (DMEA) Rich Katz (NASA) David Flowers

More information

Advanced VLSI Design CMOS Processing Technology

Advanced VLSI Design CMOS Processing Technology Isolation of transistors, i.e., their source and drains, from other transistors is needed to reduce electrical interactions between them. For technologies

More information

Highly Scalable NAND Flash Memory Cell Design Embracing Backside Charge Storage

Highly Scalable NAND Flash Memory Cell Design Embracing Backside Charge Storage JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.15, NO.2, APRIL, 2015 ISSN(Print) 1598-1657 http://dx.doi.org/10.5573/jsts.2015.15.2.286 ISSN(Online) 2233-4866 Highly Scalable NAND Flash Memory Cell

More information

ISTITUTO NAZIONALE DI FISICA NUCLEARE

ISTITUTO NAZIONALE DI FISICA NUCLEARE ISTITUTO NAZIONALE DI FISICA NUCLEARE Sezione di Trieste INFN/TC-2/7 1 aprile 22 A novel scheme for the integrated voltage divider of Silicon Drift Detectors P. Burger 1, C. Piemonte 2, A. Rashevsky 3,

More information

3D NAND Technology Implications to Enterprise Storage Applications

3D NAND Technology Implications to Enterprise Storage Applications 3D NAND Technology Implications to Enterprise Storage Applications Jung H. Yoon Memory Technology IBM Systems Supply Chain Outline Memory Technology Scaling - Driving Forces Density trends & outlook Bit

More information

Handout 17. by Dr Sheikh Sharif Iqbal. Memory Unit and Read Only Memories

Handout 17. by Dr Sheikh Sharif Iqbal. Memory Unit and Read Only Memories Handout 17 by Dr Sheikh Sharif Iqbal Memory Unit and Read Only Memories Objective: - To discuss different types of memories used in 80x86 systems for storing digital information. - To learn the electronic

More information

IEEE Milestone Proposal: Creating the Foundation of the Data Storage Flash Memory Industry

IEEE Milestone Proposal: Creating the Foundation of the Data Storage Flash Memory Industry Abstract Flash memory used for mass data storage has supplanted the photographic film and floppy disk markets. It has also largely replaced the use of magnetic tape, CD, DVD and magnetic hard disk drives

More information

Preliminary Evaluation of Data Retention Characteristics for Ferroelectric Random Access Memories (FRAMs).

Preliminary Evaluation of Data Retention Characteristics for Ferroelectric Random Access Memories (FRAMs). 1 Preliminary Evaluation of Data Retention Characteristics for Ferroelectric Random Access Memories (FRAMs). 1.0 Introduction 1.1 FRAM Technology Background Ashok K. Sharma/NASA Ashok.k.Sharma.1@gsfc.nasa.gov

More information

Local Heating Attacks on Flash Memory Devices. Dr Sergei Skorobogatov

Local Heating Attacks on Flash Memory Devices. Dr Sergei Skorobogatov Local Heating Attacks on Flash Memory Devices Dr Sergei Skorobogatov http://www.cl.cam.ac.uk/~sps32 email: sps32@cam.ac.uk Introduction Semi-invasive attacks were introduced in 2002 ( Optical fault induction

More information

FLASH TECHNOLOGY DRAM/EPROM. Flash. 1980 1982 1984 1986 1988 1990 1992 1994 1996 Year Source: Intel/ICE, "Memory 1996"

FLASH TECHNOLOGY DRAM/EPROM. Flash. 1980 1982 1984 1986 1988 1990 1992 1994 1996 Year Source: Intel/ICE, Memory 1996 10 FLASH TECHNOLOGY Overview Flash memory technology is a mix of EPROM and EEPROM technologies. The term flash was chosen because a large chunk of memory could be erased at one time. The name, therefore,

More information

DESIGN CHALLENGES OF TECHNOLOGY SCALING

DESIGN CHALLENGES OF TECHNOLOGY SCALING DESIGN CHALLENGES OF TECHNOLOGY SCALING IS PROCESS TECHNOLOGY MEETING THE GOALS PREDICTED BY SCALING THEORY? AN ANALYSIS OF MICROPROCESSOR PERFORMANCE, TRANSISTOR DENSITY, AND POWER TRENDS THROUGH SUCCESSIVE

More information

Overview of Radiation Test Activities on Memories at ESA

Overview of Radiation Test Activities on Memories at ESA Overview of Radiation Test Activities on Memories at ESA Dr. Véronique Ferlet-Cavrois IEEE Fellow ESA ESTEC, TEC-QEC 30/04/2015 Contact for information: Veronique.Ferlet-Cavrois@esa.int Outline o Memories

More information

Chapter 9 Semiconductor Memories. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan

Chapter 9 Semiconductor Memories. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Chapter 9 Semiconductor Memories Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2 Outline Introduction

More information

CHARGE pumps are the circuits that used to generate dc

CHARGE pumps are the circuits that used to generate dc INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR CIRCUITS AND SYSTEMS, VOL. 1, NO. 1, JUNE 2011 27 A Charge Pump Circuit by using Voltage-Doubler as Clock Scheme Wen Chang Huang, Jin Chang Cheng,

More information

90nm e-page Flash for Machine to Machine Applications

90nm e-page Flash for Machine to Machine Applications 90nm e-page Flash for Machine to Machine Applications François Maugain, Jean Devin Microcontrollers, Memories & Secure MCUs Group 90nm e-page Flash for M2M applications Outline M2M Market Cycling Endurance

More information

NAND Basics Understanding the Technology Behind Your SSD

NAND Basics Understanding the Technology Behind Your SSD 03 Basics Understanding the Technology Behind Your SSD Although it may all look the same, all is not created equal: SLC, 2-bit MLC, 3-bit MLC (also called TLC), synchronous, asynchronous, ONFI 1.0, ONFI

More information

Semiconductor Memories

Semiconductor Memories Semiconductor Memories Semiconductor memories array capable of storing large quantities of digital information are essential to all digital systems Maximum realizable data storage capacity of a single

More information

CONTENTS. Preface. 1.1.2. Energy bands of a crystal (intuitive approach)

CONTENTS. Preface. 1.1.2. Energy bands of a crystal (intuitive approach) CONTENTS Preface. Energy Band Theory.. Electron in a crystal... Two examples of electron behavior... Free electron...2. The particle-in-a-box approach..2. Energy bands of a crystal (intuitive approach)..3.

More information

Statistical Models for Hot Electron Degradation in Nano-Scaled MOSFET Devices

Statistical Models for Hot Electron Degradation in Nano-Scaled MOSFET Devices 2006, 대한 산업공학회 추계학술대회 Session C3 : Statistical models Statistical Models for Hot Electron Degradation in Nano-Scaled MOSFET Devices Seong-joon Kim, Suk Joo Bae Dept. of Industrial Engineering, Hanyang

More information

Module 2. Embedded Processors and Memory. Version 2 EE IIT, Kharagpur 1

Module 2. Embedded Processors and Memory. Version 2 EE IIT, Kharagpur 1 Module 2 Embedded Processors and Memory Version 2 EE IIT, Kharagpur 1 Lesson 5 Memory-I Version 2 EE IIT, Kharagpur 2 Instructional Objectives After going through this lesson the student would Pre-Requisite

More information

Evaluation of the Surface State Using Charge Pumping Methods

Evaluation of the Surface State Using Charge Pumping Methods Evaluation of the Surface State Using Charge Pumping Methods Application Note 4156-9 Agilent 4155C/4156C Semiconductor Parameter Analyzer Introduction As device features get smaller, hot carrier induced

More information

Optical Link ASICs for LHC Upgrades

Optical Link ASICs for LHC Upgrades Optical Link ASICs for LHC Upgrades K.K. Gan, H.P. Kagan, R.D. Kass, J. Moore, S. Smith The Ohio State University July 30, 2009 K.K. Gan DPF2009 1 Outline Introduction VCSEL driver chip PIN receiver/decoder

More information

1 / 25. CS 137: File Systems. Persistent Solid-State Storage

1 / 25. CS 137: File Systems. Persistent Solid-State Storage 1 / 25 CS 137: File Systems Persistent Solid-State Storage Technology Change is Coming Introduction Disks are cheaper than any solid-state memory Likely to be true for many years But SSDs are now cheap

More information

High Open Circuit Voltage of MQW Amorphous Silicon Photovoltaic Structures

High Open Circuit Voltage of MQW Amorphous Silicon Photovoltaic Structures High Open Circuit Voltage of MQW Amorphous Silicon Photovoltaic Structures ARGYRIOS C. VARONIDES Physics and EE Department University of Scranton 800 Linden Street, Scranton PA, 18510 United States Abstract:

More information

CHAPTER 10 Fundamentals of the Metal Oxide Semiconductor Field Effect Transistor

CHAPTER 10 Fundamentals of the Metal Oxide Semiconductor Field Effect Transistor CHAPTER 10 Fundamentals of the Metal Oxide Semiconductor Field Effect Transistor Study the characteristics of energy bands as a function of applied voltage in the metal oxide semiconductor structure known

More information

SLC vs MLC NAND and The Impact of Technology Scaling. White paper CTWP010

SLC vs MLC NAND and The Impact of Technology Scaling. White paper CTWP010 SLC vs MLC NAND and The mpact of Technology Scaling White paper CTWP010 Cactus Technologies Limited Suite C, 15/F, Capital Trade Center 62 Tsun Yip Street, Kwun Tong Kowloon, Hong Kong Tel: +852-2797-2277

More information

SLC vs. MLC: An Analysis of Flash Memory

SLC vs. MLC: An Analysis of Flash Memory SLC vs. MLC: An Analysis of Flash Memory Examining the Quality of Memory: Understanding the Differences between Flash Grades Table of Contents Abstract... 3 Introduction... 4 Flash Memory Explained...

More information

Static-Noise-Margin Analysis of Conventional 6T SRAM Cell at 45nm Technology

Static-Noise-Margin Analysis of Conventional 6T SRAM Cell at 45nm Technology Static-Noise-Margin Analysis of Conventional 6T SRAM Cell at 45nm Technology Nahid Rahman Department of electronics and communication FET-MITS (Deemed university), Lakshmangarh, India B. P. Singh Department

More information

Error Patterns in MLC NAND Flash Memory: Measurement, Characterization, and Analysis

Error Patterns in MLC NAND Flash Memory: Measurement, Characterization, and Analysis Error Patterns in MLC NAND Flash Memory: Measurement, Characterization, and Analysis Yu Cai 1, Erich F. Haratsch 2, Onur Mutlu 1 and Ken Mai 1 1 Department of Electrical and Computer Engineering, Carnegie

More information

Module 7 : I/O PADs Lecture 33 : I/O PADs

Module 7 : I/O PADs Lecture 33 : I/O PADs Module 7 : I/O PADs Lecture 33 : I/O PADs Objectives In this lecture you will learn the following Introduction Electrostatic Discharge Output Buffer Tri-state Output Circuit Latch-Up Prevention of Latch-Up

More information

Activitity (of a radioisotope): The number of nuclei in a sample undergoing radioactive decay in each second. It is commonly expressed in curies

Activitity (of a radioisotope): The number of nuclei in a sample undergoing radioactive decay in each second. It is commonly expressed in curies Activitity (of a radioisotope): The number of nuclei in a sample undergoing radioactive decay in each second. It is commonly expressed in curies (Ci), where 1 Ci = 3.7x10 10 disintegrations per second.

More information

Simulation and Design of Printed Circuit Boards Utilizing Novel Embedded Capacitance Material

Simulation and Design of Printed Circuit Boards Utilizing Novel Embedded Capacitance Material Simulation and Design of Printed Circuit Boards Utilizing Novel Embedded Capacitance Material Yu Xuequan, Yan Hang, Zhang Gezi, Wang Haisan Huawei Technologies Co., Ltd Lujiazui Subpark, Pudong Software

More information

Implementation Of High-k/Metal Gates In High-Volume Manufacturing

Implementation Of High-k/Metal Gates In High-Volume Manufacturing White Paper Implementation Of High-k/Metal Gates In High-Volume Manufacturing INTRODUCTION There have been significant breakthroughs in IC technology in the past decade. The upper interconnect layers of

More information

Radiation effects on space electronics. Jan Kenneth Bekkeng, University of Oslo - Department of Physics

Radiation effects on space electronics. Jan Kenneth Bekkeng, University of Oslo - Department of Physics Radiation effects on space electronics Jan Kenneth Bekkeng, University of Oslo - Department of Physics Background The presence of radiation in space causes effects in electronic devices. The effects range

More information

MRF175GU MRF175GV The RF MOSFET Line 200/150W, 500MHz, 28V

MRF175GU MRF175GV The RF MOSFET Line 200/150W, 500MHz, 28V Designed for broadband commercial and military applications using push pull circuits at frequencies to 500 MHz. The high power, high gain and broadband performance of these devices makes possible solid

More information

New Ferroelectric Material for Embedded FRAM LSIs

New Ferroelectric Material for Embedded FRAM LSIs New Ferroelectric Material for Embedded FRAM LSIs V Kenji Maruyama V Masao Kondo V Sushil K. Singh V Hiroshi Ishiwara (Manuscript received April 5, 2007) The strong growth of information network infrastructures

More information

StarRC Custom: Next-Generation Modeling and Extraction Solution for Custom IC Designs

StarRC Custom: Next-Generation Modeling and Extraction Solution for Custom IC Designs White Paper StarRC Custom: Next-Generation Modeling and Extraction Solution for Custom IC Designs May 2010 Krishnakumar Sundaresan Principal Engineer and CAE Manager, Synopsys Inc Executive Summary IC

More information

Modification of Pd-H 2 and Pd-D 2 thin films processed by He-Ne laser

Modification of Pd-H 2 and Pd-D 2 thin films processed by He-Ne laser Modification of Pd-H 2 and Pd-D 2 thin films processed by He-Ne laser V.Nassisi #, G.Caretto #, A. Lorusso #, D.Manno %, L.Famà %, G.Buccolieri %, A.Buccolieri %, U.Mastromatteo* # Laboratory of Applied

More information

Application Note AN-940

Application Note AN-940 Application Note AN-940 How P-Channel MOSFETs Can Simplify Your Circuit Table of Contents Page 1. Basic Characteristics of P-Channel HEXFET Power MOSFETs...1 2. Grounded Loads...1 3. Totem Pole Switching

More information

Micron MT29F2G08AAB 2 Gbit NAND Flash Memory Structural Analysis

Micron MT29F2G08AAB 2 Gbit NAND Flash Memory Structural Analysis August 17, 2006 Micron MT29F2G08AAB 2 Gbit NAND Flash Memory Structural Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor

More information

Solid-State Physics: The Theory of Semiconductors (Ch. 10.6-10.8) SteveSekula, 30 March 2010 (created 29 March 2010)

Solid-State Physics: The Theory of Semiconductors (Ch. 10.6-10.8) SteveSekula, 30 March 2010 (created 29 March 2010) Modern Physics (PHY 3305) Lecture Notes Modern Physics (PHY 3305) Lecture Notes Solid-State Physics: The Theory of Semiconductors (Ch. 10.6-10.8) SteveSekula, 30 March 2010 (created 29 March 2010) Review

More information

A Novel Low Power Fault Tolerant Full Adder for Deep Submicron Technology

A Novel Low Power Fault Tolerant Full Adder for Deep Submicron Technology International Journal of Computer Sciences and Engineering Open Access Research Paper Volume-4, Issue-1 E-ISSN: 2347-2693 A Novel Low Power Fault Tolerant Full Adder for Deep Submicron Technology Zahra

More information

RAM & ROM Based Digital Design. ECE 152A Winter 2012

RAM & ROM Based Digital Design. ECE 152A Winter 2012 RAM & ROM Based Digital Design ECE 152A Winter 212 Reading Assignment Brown and Vranesic 1 Digital System Design 1.1 Building Block Circuits 1.1.3 Static Random Access Memory (SRAM) 1.1.4 SRAM Blocks in

More information

Automotive MOSFETs in Linear Applications: Thermal Instability

Automotive MOSFETs in Linear Applications: Thermal Instability Application Note, V1.0, May 2005 Automotive MOSFETs in Linear Applications: Thermal Instability by Peter H. Wilson Automotive Power N e v e r s t o p t h i n k i n g. - 1 - Table of Content 1. Introduction...

More information

Samsung 2bit 3D V-NAND technology

Samsung 2bit 3D V-NAND technology Samsung 2bit 3D V-NAND technology Gain more capacity, speed, endurance and power efficiency Traditional NAND technology cannot keep pace with growing data demands Introduction Data traffic continues to

More information

Crossbar Resistive Memory:

Crossbar Resistive Memory: White Paper Crossbar Resistive Memory: The Future Technology for NAND Flash By Hagop Nazarian, Vice President of Engineering and Co-Founder Abstract NAND Flash technology has been serving the storage memory

More information

Algorithms and Methods for Distributed Storage Networks 3. Solid State Disks Christian Schindelhauer

Algorithms and Methods for Distributed Storage Networks 3. Solid State Disks Christian Schindelhauer Algorithms and Methods for Distributed Storage Networks 3. Solid State Disks Institut für Informatik Wintersemester 2007/08 Solid State Disks Motivation 2 10 5 1980 1985 1990 1995 2000 2005 2010 PRODUCTION

More information

Analyzing Electrical Effects of RTA-driven Local Anneal Temperature Variation

Analyzing Electrical Effects of RTA-driven Local Anneal Temperature Variation 1 Analyzing Electrical Effects of RTA-driven Local Anneal Temperature Variation Vivek Joshi, Kanak Agarwal*, Dennis Sylvester, David Blaauw Electrical Engineering & Computer Science University of Michigan,

More information

Nanoscale Resolution Options for Optical Localization Techniques. C. Boit TU Berlin Chair of Semiconductor Devices

Nanoscale Resolution Options for Optical Localization Techniques. C. Boit TU Berlin Chair of Semiconductor Devices berlin Nanoscale Resolution Options for Optical Localization Techniques C. Boit TU Berlin Chair of Semiconductor Devices EUFANET Workshop on Optical Localization Techniques Toulouse, Jan 26, 2009 Jan 26,

More information

CO2005: Electronics I (FET) Electronics I, Neamen 3th Ed. 1

CO2005: Electronics I (FET) Electronics I, Neamen 3th Ed. 1 CO2005: Electronics I The Field-Effect Transistor (FET) Electronics I, Neamen 3th Ed. 1 MOSFET The metal-oxide-semiconductor field-effect transistor (MOSFET) becomes a practical reality in the 1970s. The

More information

WP001 - Flash Management A detailed overview of flash management techniques

WP001 - Flash Management A detailed overview of flash management techniques WHITE PAPER A detailed overview of flash management techniques November 2013 951 SanDisk Drive, Milpitas, CA 95035 2013 SanDIsk Corporation. All rights reserved www.sandisk.com Table of Contents 1. Introduction...

More information

Field-Effect (FET) transistors

Field-Effect (FET) transistors Field-Effect (FET) transistors References: Hayes & Horowitz (pp 142-162 and 244-266), Rizzoni (chapters 8 & 9) In a field-effect transistor (FET), the width of a conducting channel in a semiconductor and,

More information

Electron mobility in MOSFETs with ultrathin RTCVD silicon nitride/oxynitride stacked gate dielectrics

Electron mobility in MOSFETs with ultrathin RTCVD silicon nitride/oxynitride stacked gate dielectrics Solid-State Electronics 47 (2003) 49 53 www.elsevier.com/locate/sse Short Communication Electron mobility in MOSFETs with ultrathin RTCVD silicon nitride/oxynitride stacked gate dielectrics K.J. Yang a,

More information

Use of the VALIDATOR Dosimetry System for Quality Assurance and Quality Control of Blood Irradiators

Use of the VALIDATOR Dosimetry System for Quality Assurance and Quality Control of Blood Irradiators Technical Note: 9 Use of the VALIDATOR Dosimetry System for Quality Assurance and Quality Control of Blood Irradiators 1- Introduction The VALIDATOR, model TN-ID-60, is a compact, and stand-alone dosimetry

More information

Winbond W2E512/W27E257 EEPROM

Winbond W2E512/W27E257 EEPROM Construction Analysis Winbond W2E512/W27E257 EEPROM Report Number: SCA 9703-533 Global Semiconductor Industry the Serving Since 1964 15022 N. 75th Street Scottsdale, AZ 85260-2476 Phone: 602-998-9780 Fax:

More information

Solid State Drives Data Reliability and Lifetime. Abstract

Solid State Drives Data Reliability and Lifetime. Abstract Solid State Drives Data Reliability and Lifetime White Paper Alan R. Olson & Denis J. Langlois April 7, 2008 Abstract The explosion of flash memory technology has dramatically increased storage capacity

More information

Lecture N -1- PHYS 3330. Microcontrollers

Lecture N -1- PHYS 3330. Microcontrollers Lecture N -1- PHYS 3330 Microcontrollers If you need more than a handful of logic gates to accomplish the task at hand, you likely should use a microcontroller instead of discrete logic gates 1. Microcontrollers

More information

DISCRETE SEMICONDUCTORS DATA SHEET. BLF244 VHF power MOS transistor

DISCRETE SEMICONDUCTORS DATA SHEET. BLF244 VHF power MOS transistor DISCRETE SEMICONDUCTORS DATA SHEET September 1992 FEATURES High power gain Low noise figure Easy power control Good thermal stability Withstands full load mismatch Gold metallization ensures excellent

More information

Data remanence in Flash Memory Devices

Data remanence in Flash Memory Devices Data remanence in Flash Memory Devices Sergei Skorobogatov 1 Data remanence Residual representation of data after erasure Magnetic media SRAM and DRAM Low-temperature data remanence Long-term retention

More information

Fabrication and Characterization of N- and P-Type a-si:h Thin Film Transistors

Fabrication and Characterization of N- and P-Type a-si:h Thin Film Transistors Fabrication and Characterization of N- and P-Type a-si:h Thin Film Transistors Engineering Practical Jeffrey Frederick Gold Fitzwilliam College University of Cambridge Lent 1997 FABRCATON AND CHARACTERZATON

More information

LAB 7 MOSFET CHARACTERISTICS AND APPLICATIONS

LAB 7 MOSFET CHARACTERISTICS AND APPLICATIONS LAB 7 MOSFET CHARACTERISTICS AND APPLICATIONS Objective In this experiment you will study the i-v characteristics of an MOS transistor. You will use the MOSFET as a variable resistor and as a switch. BACKGROUND

More information

Samsung 3bit 3D V-NAND technology

Samsung 3bit 3D V-NAND technology White Paper Samsung 3bit 3D V-NAND technology Yield more capacity, performance and power efficiency Stay abreast of increasing data demands with Samsung's innovative vertical architecture Introduction

More information

MOS (metal-oxidesemiconductor) 李 2003/12/19

MOS (metal-oxidesemiconductor) 李 2003/12/19 MOS (metal-oxidesemiconductor) 李 2003/12/19 Outline Structure Ideal MOS The surface depletion region Ideal MOS curves The SiO 2 -Si MOS diode (real case) Structure A basic MOS consisting of three layers.

More information

1.1 Silicon on Insulator a brief Introduction

1.1 Silicon on Insulator a brief Introduction Table of Contents Preface Acknowledgements Chapter 1: Overview 1.1 Silicon on Insulator a brief Introduction 1.2 Circuits and SOI 1.3 Technology and SOI Chapter 2: SOI Materials 2.1 Silicon on Heteroepitaxial

More information

Frank Hong Advanced CAE Lab, Telecommunication R&D Center, Telecommunication Business, SAMSUNG ELECTRONICS, Suwon, Republic of Korea

Frank Hong Advanced CAE Lab, Telecommunication R&D Center, Telecommunication Business, SAMSUNG ELECTRONICS, Suwon, Republic of Korea Slots on Ground Fillings of Multi-layer Printed Circuit Board for Suppressing Indirect Crosstalk between Digital Clock Line and RF Signal Line in Mixed Mode Mobile Systems Jun So Pak School of Electrical

More information

Tobias Märkl. November 16, 2009

Tobias Märkl. November 16, 2009 ,, Tobias Märkl to 1/f November 16, 2009 1 / 33 Content 1 duction to of Statistical Comparison to Other Types of Noise of of 2 Random duction to Random General of, to 1/f 3 4 2 / 33 , to 1/f 3 / 33 What

More information

Class 18: Memories-DRAMs

Class 18: Memories-DRAMs Topics: 1. Introduction 2. Advantages and Disadvantages of DRAMs 3. Evolution of DRAMs 4. Evolution of DRAMs 5. Basics of DRAMs 6. Basics of DRAMs 7. Write Operation 8. SA-Normal Operation 9. SA-Read Operation

More information

A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes

A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes 1700 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 11, NOVEMBER 2001 A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes Taehee Cho, Yeong-Taek Lee, Eun-Cheol

More information

1700V Bi-Mode Insulated Gate Transistor (BIGT) on Thin Wafer Technology

1700V Bi-Mode Insulated Gate Transistor (BIGT) on Thin Wafer Technology 1700V Bi-Mode Insulated Gate Transistor (BIGT) on Thin Wafer Technology Munaf Rahimo, Jan Vobecky, Chiara Corvasce ISPS, September 2010, Prague, Czech Republic Copyright [2010] IEEE. Reprinted from the

More information

Large-Capacity Flash Memories and Their Application to Flash Cards

Large-Capacity Flash Memories and Their Application to Flash Cards Large-Capacity Flash Memories and Their Application to Flash Cards 68 Large-Capacity Flash Memories and Their Application to Flash Cards Takashi Totsuka Kazunori Furusawa OVERVIEW: Flash cards using flash

More information

IN current film media, the increase in areal density has

IN current film media, the increase in areal density has IEEE TRANSACTIONS ON MAGNETICS, VOL. 44, NO. 1, JANUARY 2008 193 A New Read Channel Model for Patterned Media Storage Seyhan Karakulak, Paul H. Siegel, Fellow, IEEE, Jack K. Wolf, Life Fellow, IEEE, and

More information

Scientific Exchange Program

Scientific Exchange Program Scientific Exchange Program Electrical characterization of photon detectors based on acoustic charge transport Dr. Paulo Santos, Paul Drude Institute, Berlin,Germany Dr. Pablo Diniz Batista, Brazilian

More information

A 10,000 Frames/s 0.18 µm CMOS Digital Pixel Sensor with Pixel-Level Memory

A 10,000 Frames/s 0.18 µm CMOS Digital Pixel Sensor with Pixel-Level Memory Presented at the 2001 International Solid State Circuits Conference February 5, 2001 A 10,000 Frames/s 0.1 µm CMOS Digital Pixel Sensor with Pixel-Level Memory Stuart Kleinfelder, SukHwan Lim, Xinqiao

More information

Data Retention in MLC NAND Flash Memory: Characterization, Optimization, and Recovery

Data Retention in MLC NAND Flash Memory: Characterization, Optimization, and Recovery Data Retention in MLC NAND Flash Memory: Characterization, Optimization, and Recovery Yu Cai, Yixin Luo, Erich F. Haratsch *, Ken Mai, Onur Mutlu Carnegie Mellon University, * LSI Corporation yucaicai@gmail.com,

More information

Observation of Long Transients in the Electrical Characterization of Thin Film BST Capacitors

Observation of Long Transients in the Electrical Characterization of Thin Film BST Capacitors Integrated Ferroelectrics, 53: 503 511, 2003 Copyright C Taylor & Francis Inc. ISSN: 1058-4587 print/ 1607-8489 online DOI: 10.1080/10584580390258651 Observation of Long Transients in the Electrical Characterization

More information

Evolution and Prospect of Single-Photon

Evolution and Prospect of Single-Photon S. Cova, M. Ghioni, A. Lotito, F. Zappa Evolution and Prospect of Single-Photon Avalanche Diodes and Quenching Circuits Politecnico di Milano, Dip. Elettronica e Informazione, Milano, Italy Outline Introduction

More information

2-DFINITE ELEMENT CABLE & BOX IEMP ANALYSIS

2-DFINITE ELEMENT CABLE & BOX IEMP ANALYSIS P 7. I 2-DFINITE ELEMENT CABLE & BOX IEMP ANALYSIS - "L C. David Turner and Gary J. Scrivner Sandia National Laboratories Albuquerque, NM 87185-1152 a ABSTRACT and multiple dielectric regions. The applicable

More information

Chapter 19 Operational Amplifiers

Chapter 19 Operational Amplifiers Chapter 19 Operational Amplifiers The operational amplifier, or op-amp, is a basic building block of modern electronics. Op-amps date back to the early days of vacuum tubes, but they only became common

More information

Application Note AN-1068 reva

Application Note AN-1068 reva Application Note AN-1068 reva Considerations for Designs Using Radiation-Hardened Solid State Relays By Alan Tasker Table of Contents Introduction Page Overview...1 The Contact...1 Actuation...1 The IR

More information

In-Block Level Redundancy Management for Flash Storage System

In-Block Level Redundancy Management for Flash Storage System , pp.309-318 http://dx.doi.org/10.14257/ijmue.2015.10.9.32 In-Block Level Redundancy Management for Flash Storage System Seung-Ho Lim Division of Computer and Electronic Systems Engineering Hankuk University

More information

Intel s Revolutionary 22 nm Transistor Technology

Intel s Revolutionary 22 nm Transistor Technology Intel s Revolutionary 22 nm Transistor Technology Mark Bohr Intel Senior Fellow Kaizad Mistry 22 nm Program Manager May, 2011 1 Key Messages Intel is introducing revolutionary Tri-Gate transistors on its

More information

3D Charge Trapping (CT) NAND Flash Yen-Hao Shih

3D Charge Trapping (CT) NAND Flash Yen-Hao Shih 3D Charge Trapping (CT) NAND Flash Yen-Hao Shih Macronix International Co., Ltd. Hsinchu,, Taiwan Email: yhshih@mxic.com.tw 1 Outline Why Does NAND Go to 3D? Design a 3D NAND Flash Memory Challenges and

More information

ISSCC 2003 / SESSION 10 / HIGH SPEED BUILDING BLOCKS / PAPER 10.5

ISSCC 2003 / SESSION 10 / HIGH SPEED BUILDING BLOCKS / PAPER 10.5 ISSCC 2003 / SESSION 10 / HIGH SPEED BUILDING BLOCKS / PAPER 10.5 10.5 Broadband ESD Protection Circuits in CMOS Technology Sherif Galal, Behzad Razavi Electrical Engineering Department, University of

More information

NAND Flash memory. Samsung Electronics, co., Ltd Flash design team 2010. 05. 07. Kihwan Choi - 1/48 - ELECTRONICS

NAND Flash memory. Samsung Electronics, co., Ltd Flash design team 2010. 05. 07. Kihwan Choi - 1/48 - ELECTRONICS NAND Flash memory Samsung Electronics, co., Ltd Flash design team 2010. 05. 07 Kihwan Choi - 1/48 - Contents Introduction Flash memory 101 Basic operations Current issues & approach In the near future

More information

These help quantify the quality of a design from different perspectives: Cost Functionality Robustness Performance Energy consumption

These help quantify the quality of a design from different perspectives: Cost Functionality Robustness Performance Energy consumption Basic Properties of a Digital Design These help quantify the quality of a design from different perspectives: Cost Functionality Robustness Performance Energy consumption Which of these criteria is important

More information

Trabajo 4.5 - Memorias flash

Trabajo 4.5 - Memorias flash Memorias flash II-PEI 09/10 Trabajo 4.5 - Memorias flash Wojciech Ochalek This document explains the concept of flash memory and describes it s the most popular use. Moreover describes also Microdrive

More information

High power picosecond lasers enable higher efficiency solar cells.

High power picosecond lasers enable higher efficiency solar cells. White Paper High power picosecond lasers enable higher efficiency solar cells. The combination of high peak power and short wavelength of the latest industrial grade Talisker laser enables higher efficiency

More information

Test Solution for Data Retention Faults in Low-Power SRAMs

Test Solution for Data Retention Faults in Low-Power SRAMs Test Solution for Data Retention Faults in Low-Power SRAMs L. B. Zordan 1 A. Bosio 1 L. Dilillo 1 P. Girard 1 A. Todri 1 A. Virazel 1 N. Badereddine 2 1 LIRMM - Université Montpellier II / CNRS 161, rue

More information