2 Manufacturing testing

Transcription

1 2 MANUFACTURING TESTING 3 2 Manufacturing testing 2. Definition During the development process of a chip, several different types of testing are used. While designing, it is useful to simulate the design with a (functional) testbench in order to verify whether the design conforms to its specifications. This can be seen as a kind of testing, but should rather be called (design) verification. When the chip is ready for production, prototype testing is done. This is a form of hardware testing which verifies both the design and technology. Its purpose is to find any major design- and technology-related faults. Manufacturing or post-production chip testing is a subset of prototype testing and is also used for every chip throughout its lifetime. Whenever we refer to testing in this thesis, we mean this type of testing. Its goal is to check whether a design implemented in silicon is free of manufacturing defects. Unfortunately, the fabrication process of chips is not perfect. Common defects are shorts, opens and bridges. The silicon itself is not always perfect either. It might contain crystal imperfections or surface impurities. All kinds of defects may be present in a fabricated chip. The focus in (manufacturing) testing is on circuit topology rather than functional behavior. Firstly, it is not its purpose to verify the circuit s functionality. Secondly, the functionality is in general too complicated to base the testing on. A main driver in manufacturing testing is cost, since every chip must be tested. Test time must be absolutely minimized and is directly proportional to the amount of test vectors needed. While the correct functionality of a circuit can often only be guaranteed by trying all possible input combinations, its structural correctness can be verified by toggling each line in the circuit. For example, consider a 6- bit adder. Two 6-bit input words make a total of 2 32 = 4, 294, 967, 296 possible input combinations. By comparison, about input patterns will suffice for the structural testing of such an adder circuit (see also Section 5.). 2.2 Sources for more information As this chapter only gives a cursory overview of relevant aspects about testing and testability, we refer to more elaborate sources beforehand: ˆ A general introduction to manufacturing testing, also used for the master course Testable Design and Test of Integrated Systems, is given by [2]. ˆ More on BIST, as well as manufacturing testing in general, can be found in [3]. ˆ [4] is a clear introduction to testability and the Synopsys tools with many practical hints. ˆ [5] is a self-written introduction to the Synopsys tools. ˆ [23], [24], [25] and [26] are major test conferences and symposia. Their proceedings contain papers on cutting-edge testing issues. 2.3 Fault models and test types Physical defects do not generally allow a direct mathematical treatment of testing. For that we need mathematical mechanisms, called fault models, as a means to abstractly represent manufacturing defects. To make a clear distinction in terminology, the word defect will only be used to mean a physical defect and fault will refer to an abstract representation of a defect in a fault model. Fault models can be grouped in the following hierarchical levels:

2 2 MANUFACTURING TESTING 4 Behavioral level The behavioral level has few implementation details. Fault simulation at this level is the fastest, but there is no obvious correlation to manufacturing defects. High-level fault models play a greater role in simulation-based design verification than in testing. Exceptions are the functional fault models of memories. Since the function of memory is simple, exhaustive functional tests are possible and normally used in practice. Logic level The logic or gate level consists of a netlist of gates. The stuck-at fault model at this level is the most popular fault model in digital testing. It is both simple and technology-independent. Other fault models at this level are bridging faults and delay faults. Component level Transistor and other lower levels are mainly used in analog circuit testing. An example at this level that is also used for digital circuitry is the quiescent current (I DDQ ) fault model. While switching, CMOS circuits exhibit an elevated current, which dies out quickly to a small quiescent current after the gate outputs settle to a steady state. Defects such as transistors stuck-on, shorted wires and shorts from transistor gates to drains elevate the quiescent current. There are several categories of test types, each targeting a different set of defects: Structural testing uses the logic levels of the device s input and output pins to detect the most common static defects, such as opens and shorts in the circuit interconnections. A pattern of s and s is applied to the input pins and then the logical results at the output pins are measured. In general, a defect produces a logical value at the outputs different from the expected one. This type of testing is used for the stuck-at fault model. I DDQ testing measures the quiescent power supply current rather than pin voltages, detecting defects not easily detected by other types of testing, such as transistor stuck-on/stuck-open or bridging defects. I DDQ testing equipment applies a set of patterns to the device, lets the current settle and then measures for excessive current draw. At-speed testing checks the amount of time it takes to change logic states. A circuit might operate correctly at a slow clock rate and then fail when operated at the normal system speed. Delay variations exist between chips due to statistical variations in the manufacturing process, resulting in defects such as partially conducting transistors and resistive interconnections. The purpose of at-speed testing is to detect these types of problems. It is done by running test patterns through the circuit at the normal system clock speed. This type of testing is used for delay faults, such as transition delay and path delay faults. The Stuck-At Fault (SAF) model has been the most popular fault model in the past several decades. We look at it in more detail in the Section 2.4. It will also remain the main focus in the rest of this chapter. As designs move to.3-micron processes and below, however, the defect spectrum is changing and the standard stuck-at tests alone will no longer be sufficient. The number of resistive defects is growing, which manifest themselves as speed-related problems as opposed to hard stuck-at failures. To help achieve a more adequate defect coverage for these processes, the stuck-at faults must be supplemented by delay faults [8]. 2.4 Stuck-at faults A stuck-at fault is assumed to only affect the interconnections between logic gates. Each connecting line can have two types of faults: stuck-at- and stuck-at-, commonly written as s-a- and s-a-. Several stuck-at faults can be simultaneously present in the circuit. A circuit with n lines can have 3 n possible stuck line combinations. Each line can be in one of the three states s-a-, s-a- or fault-free. All combinations except one having all lines in the fault-free state are counted as faults. Clearly, even a moderate value of n will give an enormously large number of multiple stuck-at faults. It is common practice, therefore, to model only single stuck-at faults. An n-line circuit has only 2n single stuck-at faults. The node of a stuck-at fault must be controllable and observable for the fault to be detectable. A node is controllable if it can be driven to a specified logic value by setting the primary inputs to specific values. A

3 2 MANUFACTURING TESTING 5 Primary Input (PI) is an input that can be directly controlled. A node is observable if its response can be predicted and the fault effect can be propagated to the primary outputs where the response can be measured. A Primary Output (PO) is an output that can be directly observed. The set of input stimuli and expected response values is called a test pattern or test vector. The controllability and observability are pivotal points for the testability of a design and will be a recurring theme in the rest of this chapter and indeed the whole thesis. While at first glance the gate-level single stuck-at fault model does not appear to be attractive in terms of its ability to accurately model defects, studies of actual faulty VLSI devices have shown that test vectors developed using this fault model can be very effective when applied at-speed [3]. 2.5 Test pattern generation 2.5. Path sensitization This section outlines a method called path sensitization to generate test patterns for stuck-at faults in a combinational logic circuit with no feedback paths. The approach consists of three steps:. Fault sensitization. The fault is activated by forcing the signal at that location to a value opposite to the stuck-at value, so that there is a behavioral difference between a good and faulty circuit. This step is also known as fault activation or fault excitation. 2. Fault propagation. The fault effect is propagated through one or more paths to the POs. This step is also known as path sensitization. 3. Line justification. The signal assignments previously made to sensitize a fault or propagate its effect are justified by setting the PIs of the circuit. This step is also known as fault justification. In the second and third step, a conflict can be found, where a necessary signal assignment contradicts some previously made assignment. This forces the ATPG algorithm (see Section 2.5.3) to backtrack, i.e. discard a previously made signal assignment and choose an alternative. A A B X s-a- / / / Y B C? X s-a- / / Y (a) Detectable fault (b) Undetectable fault Figure 5: Path sensitization As an example, consider the circuits in Figure 5. Figure 5a shows a circuit with a target stuck-at fault at the second input of the upper AND gate. To activate the fault, the net connected to this port must be set to (the opposite value). Propagating the fault is done by setting the first input of the AND gate to. This is the only way to propagate the fault through the gate. Its output is in a fault-free circuit, but if the

4 2 MANUFACTURING TESTING 6 stuck-at fault is present. This is indicated by /. Propagating further through the OR gate can only be done by setting its second input to. Now we can see the fault at output Y. Line justification is done from output Y to the inputs. The bottom AND gate must have a at the second input. All other signal values are already determined. Luckily, the assigned values are consistent with the NAND gate. The test pattern is with expected output. Figure 5b (a hazard-free multiplexer) shows an example where no test pattern can be found. Fault activation, propagation and line justification give us the values as shown in the figure. Here, there is a conflict between the value of the second input of the middle AND gate and the first input of the bottom AND gate. The values are opposite from each other, while they are connected to the same net. No choices were made while assigning the signals. It must be concluded that the fault is undetectable Fault collapsing A circuit can contain a significant number of faults that behave identically to other faults. These faults are said to be equivalent. Two faults of a Boolean circuit are equivalent if and only if they transform the circuit such that the two faulty circuits have identical output functions. Figure 6 shows which stuck-at faults are equivalent for an AND and OR gate. Similar equivalences can be found for all logic gates. The process of selecting one fault from each set of equivalent faults is called fault collapsing. This reduces the number of stuck-at faults from the initial number of 2n (where n is the number of lines in the circuit). s-a- s-a- s-a- s-a- s-a- s-a- s-a- s-a- s-a- s-a- s-a- s-a- (a) AND gate (b) OR gate Figure 6: Equivalent faults If all tests for a fault F detect another fault F2, then F2 is said to dominate F. When two faults F and F2 dominate each other, then they are equivalent. In an alternative form of fault collapsing, known as dominance fault collapsing, the fault set is further reduced. In this form of fault collapsing, the dominating faults are eliminated from the equivalence collapsed sets. There are some problems with dominance fault collapsing though, which limit its use [2]. In practice, often only equivalent fault collapsing is used Automatic test pattern generation Automatic Test Pattern Generation (ATPG) is implemented by software. An ATPG run consists of two main steps: generating patterns and performing fault simulation to determine which faults the patterns detect. Two typical methods for pattern generation are random and deterministic. Additionally, ATPG tools can fault simulate patterns from an external set. Random Pattern Generation (RPG) can be used as an initial ATPG step to improve the tool s performance. It is an inexpensive way to find some patterns. From a set of randomly generated patterns, those patterns that detect faults are identified and stored in the test pattern set. An ATPG tool uses deterministic test pattern generation when it creates a test pattern for a specific fault. The procedure is to pick a fault from the fault list, create a pattern to detect the fault, fault simulate the pattern and check to make sure the pattern detects the fault. Possibly, the pattern detects other faults as well. ATPG algorithms can follow the method of path sensitization outlined in Section Well-known algo-

5 2 MANUFACTURING TESTING 7 rithms for combinational logic are the D-algorithm, PODEM and FAN [2]. Most ATPG tools use proprietary techniques to speed up and extend these basic algorithms. Randomly-generated patterns may not be very good, in the sense that a more complex pattern may exist that activates a higher percentage of the circuit, and in one test determines whether a number of faults are present, rather than just one or two. At the end of ATPG, all test patterns can be fault simulated in the reverse order of their generation, so that the patterns from RPG are simulated last. When the fault coverage reaches %, all remaining RPG patterns are discarded. Almost all digital designs of any significant size are realized as sequential circuits. These circuits contain combinational logic and memory elements like flip-flops. Their testing is more complex than that of (purely) combinational logic. Since they have an internal state, the circuit must be brought to a known state before a test pattern can be applied. After a pattern is applied, the final state must be inferred indirectly from the POs. In comparison, faults in a combinational circuit can be detected by a single vector. ATPG algorithms for sequential circuits are more complex and the sequence of test vectors that needs to be applied can be long Fault classes and coverage ATPG software may not be able to generate a test pattern for every fault. When this happens, it must perform further analysis before classifying the fault. Faults requiring this analysis include possibly detected, undetectable and ATPG-untestable faults. ATPG tool TetraMAX distinguishes the following main fault classes: Detected Faults for which a pattern is found that distinguishes a good device from a bad one. Possibly detected These are faults that may or may not be detected, since it causes an undefined output value (X). This output is only potentially different from the correct one. A possible cause is a fault that prevents the initialization of a memory element. Undetectable Some faults are impossible to detect by any means. These typically result from reconvergent fan-out combined with redundant logic, global resets or power-up initialization circuitry. Other possibilities are unconnected lines or ties to logic or. The undetectable fault in Figure 5b is caused by redundancy masking the fault effect. Undetectable faults form an interesting situation. One cannot tell whether the fault exists or not, so that the system is not affected by its presence. ATPG-untestable These faults are not necessarily intrinsically untestable, but are untestable using ATPG methods. These faults cannot be proven to be undetectable and might be testable using other methods like functional tests or with less stringent constraints for the ATPG tool. Not detected Faults are only classified in this group when the analysis for the fault was not completed or aborted. This can be caused by ATPG iteration limits or by designs that are too complex for the ATPG algorithm. TetraMAX defines the fault coverage as the number of detected faults divided by the total number of faults. Since not all faults are detectable, this figure is in general. The test coverage TC is the number of detected faults divided by the number of faults detectable by ATPG. It is calculated as: TC = DT + x.pt T UD y.au where DT is the number of detected faults, PT is the number of possibly detected faults, x is the probability of detection for these faults, T is the total number of faults, UD is the number of undetectable faults, AU is the number of ATPG-undetectable faults and y is the credit assigned to these faults. The default value of x is.5; y is by default. The sets of faults are uncollapsed by default [6].

6 2 MANUFACTURING TESTING 8 What TetraMAX refers to as test coverage is also often called fault coverage, as do we in this thesis. Only TetraMAX results will show the term test coverage. This figure can be converted to a percentage by multiplying it with. It should be as close to (or %) as possible. Each manufacturer has its own minimum value. Some require 99.9%. Note that the coverage computation depends on the used fault model. The one shown here is for the stuck-at model. Also note that the test or fault coverage is only an approximation of the defect coverage. The approximation will be better if the fault model more accurately reflects the physical defects Memory testing As mentioned before, the testing of memory arrays (SRAM or DRAM) can be based on its function, since it has a very regular structure. Test patterns can be generated algorithmically. The most used algorithms are the MATS (Modified Algorithmic Test Sequence) and March tests of which different variants exist. The March C- algorithm in particular has been observed to provide a very high defect coverage. What all algorithms basically do is walk through the memory and read/write values on the current address. The March tests all have a complexity of αn, where α is an integer and N 2 is the array size. The March C- algorithm has a complexity of N [2]. 2.6 Design for testability Traditionally, the design and test processes were kept separate, with test considered only at the end of the design cycle. But in contemporary design flows, test merges with design much earlier in the process, creating what is called a Design-for-Test (DfT) process flow. There are some good design practices to improve the overall testability of a design. They include: ˆ Minimizing asynchronous logic (like flip-flop sets and resets); ˆ Isolating clocks from the logic; ˆ Using only D flip-flops as memory elements; ˆ Minimizing redundant logic; ˆ Minimizing combinational feedback paths. Besides these general guidelines, there are two main approaches to DfT: ad-hoc and structured techniques. Testable circuitry is both controllable and observable. Ad-hoc techniques are aimed at improving the observability or controllability of specific points in the circuit. This requires manual inspection of the circuitry, but can greatly improve its testability. Structured DfT provides a more systematic approach for enhancing the testability, which can be automated. The most common structured DfT technique is scan design, which modifies the sequential circuitry of the design Ad-hoc techniques A design can contain a number of points that are difficult to control or observe. By adding special circuitry at certain locations called test points, one can increase the testability of the design. Figure 7a shows a part of a circuit that poses a testability problem. The OR gate blocks any fault effects from propagating through the gate, since the output will always be. To be able to observe any fault effect, we need to insert an observation test point at the input side of the OR gate. The output side of the gate is uncontrollable. To be able to control any circuitry behind the gate, we need to insert a controllability test point at the output side of the OR gate.

7 2 MANUFACTURING TESTING 9 VCC/ VCC/ observation test point controllability test point to PO from PI Sel test mode (a) Before (b) After Figure 7: Test point insertion Figure 7b shows a possible implementation for the test points. An unobservable point can be connected to a new PO. This is a costly solution, however. Another possibility is connecting the point to an extra flip-flop to store the signal value. This flip-flop can be inserted in a scan chain (see Section 2.6.2), so that its value can be read out during testing. As a controllability test point we can use a multiplexer. An extra PI test mode is needed to indicate whether the circuit is in normal functional mode or testing mode. In normal functional mode, the system data is propagated. In testing mode, an alternative source drives the output. This source can be a new PI or, alternatively, a flip-flop. Any solution that makes a point observable/controllable can be used as a test point. However, not all options are equally good in terms of additional pins, silicon area and performance degradation. The identification of uncontrollable/unobservable points is generally a manual process, but ATPG software can be of some assistance. They typically use testability measures like SCOAP (Sandia Controllability/Observability Analysis Program) to determine paths with the least resistance. These measures give some indication about how controllable/observable a certain node is. The SCOAP measure can be viewed in TetraMAX s GUI, for example. Do note that it may not be trivial to translate a node in the gate-level implementation (after synthesis) back to the original design (in VHDL or other HDL) Scan design Many designs contain memory elements, like latches or flip-flops. These elements make the circuit sequential rather than combinational. The goal of scan design is to make a sequential circuit (which is difficult to test) behave like a combinational circuit (which is easier to test) during the testing process. Achieving this goal involves replacing sequential elements with scannable sequential elements, called scan cells, and then connecting the scan cells together into scan chains. One can then use these serially-connected scan cells (forming a shift register) to shift data in and out when the design is in scan mode. This way, the memory elements have become pseudo-inputs and pseudo-outputs. Figure 8: Scan replacement

8 2 MANUFACTURING TESTING 2 Figure 8 illustrates the scan replacement. Replacing all memory elements by scannable ones is referred to as full-scan design. This may not be acceptable because of area and timing constraints. Adding scan circuitry increases the size and power usage of the design, because the scan cells are generally larger than the non-scan cells they replace and the interconnections used for the scan signals also occupy additional area. Furthermore, the performance (speed) decreases marginally. Alternatively, one can replace only a subset of memory elements. This is referred to as partial-scan design. The decision to use full scan or partial scan has a significant impact on the ATPG tool. Full-scan designs allow combinational ATPG methods, which require minimal test generation effort, but carry a significant amount of area overhead. On the other hand, partial to non-scan designs consume far less area overhead, but require sequential ATPG techniques, which demand significantly more test generation effort. Also, the number and complexity of the test patterns will be higher, and hence testing costs. An other consideration is whether to use a single scan chain for all memory elements or multiple shorter scan chains. In case of multiple scan chains, data can be parallelly shifted in and out, which shortens the test time, but more pins are needed and more scan boards may be needed as well (see Section 2.7). The scan boards do need less depth (memory) for the shorter chains though. There are several different scan architectures or scan styles: Multiplexed flip-flop This is a scannable version of a flip-flop. Figure 9 shows its design. It assumes all memory elements in the circuit are D flip-flops, which can be replaced by a multiplexed scan flip-flop. Din SI SE D DFF Sel clk CK Q SO/ Dout Figure 9: Multiplexed scan flip-flop The multiplexer chooses between the normal system data, which is connected to Din (previously directly connected to input D of the flip-flop), and Scan Input SI. The selection signal is called Scan Enable (SE). A new PI is needed in the design to provide this signal to every scan flip-flop. During normal functional mode, SE is kept low. The output of the flip-flop simultaneously functions as Scan Output SO and Dout. The scan flip-flops can be connected in a chain by connecting SO to SI of the next scan flip-flop. Clocked scan This style is similar to the multiplexed flip-flop, but uses a dedicated test clock to shift in scan data instead of a multiplexer. LSSD (Level-Sensitive Scan Design) This style replaces D latches by a master and slave latch, forming a (master-slave) flip-flop. In normal mode, it is level-sensitive. The master latch captures system data using the system clock and sends it to the normal system output. In test mode, it is edge-triggered. Two test clocks trigger the shifting of test data through both the master and slave latch to the scan output. A single scan style must be used for a whole design. If a design only uses (D) flip-flops, one can use any scan style, but the multiplexed scan flip-flop is the most common choice. It is also the scan style most commonly supported in technology libraries for EDA software. If a design has a mixture of latches and flip-flops, the clocked scan and LSSD scan style are suitable. If a design predominately uses latches, the LSSD scan style is recommended. The basic operating procedure for a design with multiplexed flip-flops during testing by ATE (see Section 2.7) is as follows:

9 2 MANUFACTURING TESTING 2. A pattern is serially shifted into the scan chain, each bit at a clock edge and with scan enable signal SE activated. 2. Holding the clock and SE off (so that the circuit is in normal functional mode), PIs are applied early in the next clock cycle. The POs are measured late in the same clock cycle. 3. The clock is pulsed once to capture data in the scan chain. 4. The first bit is read out with the clock off. To be able to shift the scan cells, SE is activated again. 5. The rest of the scan chain is read out by shifting it using the clock. Figure illustrates the procedure. The encircled numbers refer to the above-mentioned steps. The square blocks at the top represent a scan pattern that is serially shifted through the scan chain; the high bars represent a (parallelly fed) test pattern on the PIs. While one pattern is shifted out (during steps 4 and 5), a new pattern can be simultaneously shifted in. That way, all shifting procedures overlap, except for the first and last one. Figure : Scan pattern procedure The procedure explained here assumes there is only one scan chain. The scan procedure used by ATE is actually very flexible. It can be specified in a STIL (Standard Test Interface Language, see also Section 2.8) file that is read by ATE. This allows for custom procedures or changes to standard ones. As a first step, before any test pattern is applied, the correct functioning of the scan chain(s) is tested by a shift test. While SE is activated, a toggle sequence... is applied to the input, producing all four transitions in each flip-flop. This is continued until the first eight bits are observed on the scan output. The amount of clock cycles CC needed for all (scan) test patterns is: CC = N T V (N F F + ) + N F F + 8 where N T V is the number of test vectors and N F F is the number of flip-flops in the scan chain. 2.7 Automatic test equipment and built-in self-test Traditionally, the manufacturing testing of VLSI devices is done by Automatic Test Equipment (ATE). Modern ATE is typically operated by a computer. To select ATE, one must consider the specifications of the VLSI device. Major factors are speed (clock rate), timing (strobe) accuracy and number of I/O pins. ATE is normally equipped with so-called scan boards, which contain serial memory to shift data into and out of scan chains. When multiple scan chains are present in a VLSI device, multiple scan boards are needed. (Although some scan boards now support multiple scan chains.) More expensive test machines are required to handle the increasing number of I/O pins, higher clock rates and the larger sets of test vectors that are needed for more complex VLSI devices. Test machines of several million dollars are already commonplace (for clock rates in the GHz range) and predictions say the testing problem will only get worse in the coming

10 2 MANUFACTURING TESTING 22 years. Currently, the cost associated with testing each transistor in a VLSI device is greater than the cost to manufacture that transistor [3]. Besides the purchasing costs, there are operational costs for ATE that can be a few dollar cents per test second. The amount of test vectors should therefore be as small as possible, while maintaining a high fault coverage. Built-In Self-Test (BIST) is considered to be one of the primary solutions to the growing testing problems. The basic idea is to design a circuit that can test itself and determine whether it is faulty or fault-free. This requires additional circuitry. The added functionality must be capable of generating test patterns as well as providing a mechanism to determine if the responses of the DUT (Device-Under-Test) correspond to that of a fault-free circuit. BIST will reduce or eliminate the need for test equipment. It can also more easily operate at the intended clock rate. The biggest disadvantages of BIST are that it adds to the design time, has an area overhead and imposes performance degradation. Figure : Generic BIST architecture Figure shows the components that BIST hardware typically contains: a test controller to operate the testing process, a Test Pattern Generator (TPG) and an Output Response Analyzer (ORA) to analyze (and compact) the circuit responses. There is a variety of ways to implement the components. The most common way to implement the TPG and ORA is using register (flip-flops). Register can be used to form a Linear Feedback Shift Register (LFSR) pattern generator or an LFSR-based response compactor, called a Multiple-Input Signature Register (MISR). This takes some additional circuitry between the flip-flops. An LFSR generates patterns algorithmically and is pseudo-random. The way the flip-flops are connected determine its characteristic polynomial and the same goes for the MISR. A MISR is based on signature analysis: compacting the responses in a signature which can be compared with the expected signature of a fault-free circuit. Instead of using separate chains of flip-flops, both the LFSR and MISR can be combined in a so-called Built-In Logic Block Observer (BILBO). A problem with LFSR pattern generators is that it does not necessarily generate all the test pattern one needs to get a high fault coverage. It might be needed to reinitialize the LFSR with a different seed (initial state) several times. Note that using ATE one can supply any desired sequence of test patterns. Because of their regular structure, memory arrays are highly suitable for hardware BIST. Algorithmic test patterns can be used to test them (see also Section 2.5.5). Memory BIST is available in many EDA systems or via OEMs (Original Equipment Manufacturers) and can be used as part of the overal BIST architecture or for embedded memories only. Normally, this is employed for memory arrays exceeding 28 Kb. 2.8 Boundary scan and wrapper cells The IEEE 49. standard entitled Standard Test Access Port and Boundary-Scan Architecture is a standard interface between VLSI devices and test equipment. It provides access to the input and output pads of a chip on a PCB (Printed Circuit Board). It is also known as Boundary Scan or JTAG (Joint Test

11 2 MANUFACTURING TESTING 23 Action Group) and is supported by many EDA tools and ATE vendors. All signals between the device s core logic and the input/output pins are intercepted by a serial scan path known as the Boundary Scan Register. During normal operation the boundary scan cells are invisible. However, in test mode the cells can be used to set and/or read values. A similar standard for cores (within a SoC) is the IEEE 5 standard [7]. The two most important components of the standard are the Core Test Language (CTL) and the scalable core test architecture. CTL is an extension of the IEEE 45 Standard Test Interface Language (STIL). Its purpose is to standardize core test knowledge transfer. It must be provided by the core provider. This is necessary because cores are typically IP (Intellectual Property) blocks and the implementation is unknown. The core test architecture, including wrapper cells, can be seen as an extension to the boundary scan architecture. functional inputs W B R core W B R functional outputs wrapper serial input WBY WIR wrapper serial output wrapper interface port Figure 2: Mandatory IEEE 5 wrapper components Figure 2 shows the mandatory wrapper components. The Wrapper Instruction Register (WIR) controls the mode of operation. The input and output ports of the core are equipped with a Wrapper Boundary Register (WBR). These act transparently during normal system functioning, but in (internal) test mode, the scan chain through the WBRs is used to set the inputs and observe the outputs of the core. A single chain can contain multiple wrappers for multiple cores. The Wrapper BYpass register (WBY) can be used to skip one of the wrappers in the chain (bypass mode). Typically, some so-called glue logic is present in between cores on an SoC. While the logic within the cores may be unknown to an SoC designer, the WBRs are standardized, so that they can be used to test the glue logic. They then function as controllable inputs and observable ouputs for the glue logic. The wrappers must be put in external test mode for the testing of glue logic. 2.9 Special testability cases The following sections explain certain design features that can pose testability problems Gated clocks In low-power designs gated clocks are sometimes used, as clocking generates much dynamic power dissipation. Memory elements connected to a gated clock might not be controllable from the PIs. Certains faults within the gating element can disable the gated version of the clock, so that there is no testing option. A working clock signal is a basic requirement for the testing of a scan design, as it is needed for the flip-flops in the scan

12 2 MANUFACTURING TESTING 24 chain(s) to function. If it is necessary to use clock gating, one should provide a way to disable or bypass the gating in test mode. This can be done with a controllability test point for the gated clock (see Section 2.6.) Latches Latches are replaced by scannable equivalents in the LSSD scan style (see Section 2.6.2). Many designs mainly use flip-flops. In that case, it is a far more logical choice to use multiplexed scan flip-flops. Because of its popularity, it is also the scan style most commonly supported in technology libraries (also an important consideration). When latches are not replaced by scannable elements (for example, when using multiplexed flip-flops as scan style), they must be transparent. A transparent latch is a latch in which the enable line (or gate or control) can be asserted so that data passes through it without activating any of the design s clocks. When latches are not transparent, one might need to use sequential ATPG to get a good fault coverage. This should be avoided if possible Tri-state buses Faults on a tri-state bus enable lines can cause one of two problems: bus contention, which means there is more than one active driver, or bus float, which means there is no active driver. Either of these conditions can cause unpredictable logic values on the bus, which allows the fault to go undetected Mixed phases in scan chains If clocking in a scan chain is both inverted and noninverted, a problem similar to excessive clock skew can occur. For example, if an upstream flip-flop is rising-edge-triggered and a downstream flip-flop is falling-edgetriggered, a positive clock pulse first clocks a value into the upstream flip-flop. Then, on the same pulse s falling edge, it clocks the same value into the downstream flip-flop. If one cannot avoid mixing phases, there can be only one point in the chain where the clock phase reverses [6].