Introduction to RTL. Horácio Neto, Paulo Flores INESC-ID/IST. Design Complexity

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1 Introduction to RTL INESC-ID/IST 1 Design Complexity How to manage the complexity of a digital design with logic gates? Abstraction simplify system model Consider only specific features for the given abstraction-level Ignore unnecessary detail E.g. at gate-level consider only logic values, 0 or 1, and fixed gate delays. Register Transfer Level Represent the digital system as a sequence of data processing/transfers between registers 2

2 Abstraction Hierarchy Set of representation levels that describe the system with more or less detail Higher-level Level 1 Less detail Level i Level i+1 Transformation Lower-level Level N More detail 3 Abstraction Levels Abstraction Representation in Level Behavioral Domain Structural Domain Processor Algorithm Microprocessor, or Chip RAM, ASICs... Register Data Flow Register, ALU, Counter, MUX,... Gate Boolean equations AND,OR,XOR,FF,... Circuit Differential equations Transistor, R, L, C Layout IC Masks 4

3 Design Flow Behavioral Domain Structural Domain Processor Register-Transfer Level RTL Algorithm Data Flow Behavioral The system is described by defining the relationship between the input and output signals Gate Circuit Layout Logic Transistors Masks Structural The system is described as an set of interconnections (netlist) of lower-level components 5 Main Design Tasks Synthesis Transform system representation from higher to lower abstraction level, (or from behavioral to structural domain) Placement and Routing Obtain final circuit layout Verification Check functionality and performance (timing) Testing Detect physical defects after circuit manufacture 6

4 Synthesis The outcome of a synthesis process is a circuit structural description at the lower (same) abstraction level High-level (Architectural) synthesis RT level synthesis Gate level synthesis Technology mapping 7 Design Space The designer must establish a tradeoff between: Area region of acceptable designs faster design (61ns, 394) speed area (cost!) power testability smaller design (78ns, 272) Delay 8

5 Verification Simulation cannot prove absence of errors not exhaustive depends on designer testbench. post P&R simulation may be very computation intensive Timing analysis (static) checks delay may be pessimistic 9 Algorithm to hardware? Example: y = ⅛ (a x 2 + b x + c) calculate 2 nd order polynomial divide by 8 round the result y = ⅛ ((a x + b) x + c) 10

6 Direct dataflow implementation? res <= r1 when p4(2) = '1' else r0; r1 <= r0 + 1; r0 <= "000" & p4(p4'high downto 3); p4 <= p3 + c ; p3 <= p2 * x ; p2 <= p1 + b ; p1 <= a * x ; -- c + x *(b + a*x) -- x *(b + a*x) -- (b + a*x) -- a * x 11 Datapath with intermediate regs Intermediate registers reduce critical path and may support pipelining (for streaming applications) y = ⅛ ((a x + b) x + c)

7 Problems with direct implementation Can only be used to implement simple algorithms Not flexible Resources cannot be shared Difficult to map algorithms where the number of operations (and/or their order of execution) is not fixed 13 Register-Transfer Level Methodology RTL: The digital system is represented as a sequence of data processing/transfers between registers Use registers to store (intermediate) data Use a datapath to implement all required operations between registers Use a control unit (FSM) to specify the order of execution of the operations FSMD = Finite-State Machine with Datapath 14

8 Basic RT Operation R dest f ( R src1, R src2,, R srcn ) At the rising edge of the clock, the values stored in registers R src are available The values are processed by a combinational circuit that implements f (...) At the next rising edge of the clock, the result is stored into R dest 15 Datapath Example (1) y = ⅛ (a x 2 + b x + c) y = ⅛ ((a x + b) x + c) Sequence of RT operations R 2 R A * R X R 2 R 2 + R B R 2 R 2 * R X R 2 R 2 + R C R 2 ⅛ * R 2 16

9 Control Unit Use a FSM to control the RT operations States transition is on clock-by-clock basis FSM enforces order of execution selects MUX paths selects ALU operations enables/disables registers FSM allows branches on execution sequence 17 Example (1) FSM controls sequence of RT operations New value of R 2 becomes available at the end of the corresponding execution state. x = 2 a = 3 b = 4 c = 5 y = ⅛ ((a x + b) x + c) = 3 18

10 Datapath Example (2) y = ⅛ ((a x + b) x + c) Sequence of RT operations R 2 R A * R X + R B R 2 ⅛ (R 2 * R X + R C ) 19

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