DESIGN AND VERIFICATION OF LSR OF THE MPLS NETWORK USING VHDL

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1 IJVD: 3(1), 2012, pp DESIGN AND VERIFICATION OF LSR OF THE MPLS NETWORK USING VHDL Suvarna A. Jadhav 1 and U.L. Bombale 2 1,2 Department of Technology Shivaji university, Kolhapur, 1 suvarna_jadhav@rediffmail.com 2 uttam_bombale@rediffmail.com Abstract: With extremely wide bandwidth and good channel properties, optical fibers have brought fast and reliable data transmission to today's data communications. However, to handle heavy traffic flowing through optical physical links, much faster processing speed is required or else congestion can take place at network nodes. Also, to provide people with voice, data and all categories of multimedia services, distinguishing between different data flows is a requirement. To address this router performance, Quality of Service /Class of Service and traffic engineering issues, Multi Protocol Label Switching (MPLS) was proposed for IP-based Internetworks. In addition, routers flexible in hardware architecture in order to support ever-evolving protocols and services without causing big infrastructure modification or replacement are also desirable. Therefore, reconfigurable hardware implementation of MPLS was proposed in this project to obtain the overall fast processing speed at network nodes. The long-term goal of this project is to develop a reconfigurable MPLS router, which uniquely integrates the best features of operations being conducted in software and in run-time reconfigurable hardware. Here we are designing one component i.e LSR of MPLS network. 1. INTRODUCTION The TCP/IP protocol is a classic and standard solution to the network information transport. Currently, however, Internet Service Providers (ISPs) have the challenge to manage extensive and complex networks with increasing Quality of Service (QoS) and bandwidth requirements. In this regard the natural evolution of IP networks and TCP/IP applications lead to the development of the MPLS architecture as an alternative to meet these requirements. MPLS, an open industry standard based on technology pioneered by Cisco Systems, bridges the gap between frame relay and IP networking. MPLS delivers the privacy and security that frame relay users are used to, with the any-toany connectivity they want from IP networks. MPLS is an IETF framework that integrates layer 2 and layer 3 of the OSI model without discontinuities, and therefore combines the routing control functions of the layer 3 and commutation speed of layer 2 through a network. The MPLS technology may be applied to any layer 3 network protocol, although almost all of the interest is in using MPLS with IP Traffic Engineering. Traffic Engineering is concerned with performance optimization of operational networks. In general, it encompasses the application of technology and scientific principles to the measurement, modelling, characterization, and control of Internet traffic, and the application of such knowledge and techniques to achieve specific performance objectives. The aspects of Traffic Engineering that are of interest concerning MPLS are measurement and control. Since MPLS works over any transport technology including Asynchronous Transfer Mode (ATM) it can facilitate the migration to future optical networks that integrates IP and WDM (Wavelengths Division Multiplexing) networks. Furthermore, MPLS offer several services that IP networks cannot provide because they are limited to routing based on destiny address. MPLS also provides QoS, supports IP traffic engineering and the creation of Virtual Private Networks (VPNs). Figure 1: MPLS Shim Header

2 16 Suvarna A. Jadhav and U.L. Bombale It can be seen that the shim header is a 32 bit length value where 20 bits represent the label assigned to the frame, 3 bits are used for the EXP field, 1 bit is assigned to the S field to indicate if label stack is present and the Time to Live (TTL) field prevents packets from looping forever in the network. The label transforms the packet from one that is forwarded based on its IP routing information to one that is forwarded based on information associated with the label. In MPLS, data transmission occurs on label switched paths (LSPs). LSPs are a sequence of labels at each and every node along the path from the source to the destination. LSPs are established either prior to data transmission (control driven) or upon detection of a certain flow of data (data driven). The labels, which are underlying protocol specific identifiers, are distributed using a label distribution protocol (LDP). Each data packet encapsulates and carries the labels during their journey from source to destination. High speed switching of data is possible because of the fixed-length labels are inserted at the very beginning of the packet or cell, and can be used by hardware to switch packets quickly between links. The devices that participate in the MPLS protocol mechanisms can be classified into label edge routers (LERs) and label switching routers (LSRs) (see Figure 2). Figure 2: Nodes in MPLS Network An LSR is a high-speed router device in the core of an MPLS network that participates in the establishment of LSPs using the appropriate label signaling protocol and high-speed switching of the data traffic based on the established paths. An LER is a device that operates at the edge of the access networks and MPLS network. LERs support multiple ports connected to dissimilar networks (such as Frame Relay, ATM, and Ethernet) and using the label signaling protocol at the ingress forwards this traffic to the MPLS network after establishing LSPs, and distribute the traffic back to the access networks at the egress. The LER plays a very important role in the assignment and removal of labels, as traffic enters or exits an MPLS network. Another concept of MPLS networks is the forward equivalence class (FEC) which is a representation of a group of packets that share the same requirements for their transport. All packets in such a group are provided the same treatment in route to the destination. As opposed to conventional IP forwarding, in MPLS, the assignment of a particular packet to a particular FEC is done just once, as the packet enters the network. FECs are based on service requirements for a given set of packets or simply for an address prefix. Each LSR builds a table to specify how a packet must be forwarded. The packet is then forwarded to the next router in the LSP. This router and all subsequent routers in the LSP do not examine any of the IP routing information in the labelled packet. Rather, they use the label to look up information in their label forwarding table. They then replace the old label with a new label and forward the packet to the next router in the path. When the packet reaches the egress router, the label is removed, and the packet again becomes a native IP packet and is again forwarded based on its IP routing information. 2. VHDL VHDL (VHSIC Hardware Description Language) is becoming increasingly popular as way to express complex digital design concepts for both simulations and synthesis. The power of VHDL makes it easy to describe very large digital designs and systems, and the wide variety of design tools now available make the translation of this description into actual working hardware much faster and less error-prone than in the past. The Power and depth of VHDL does have its price, however. To make effective use of VHDL as a design entry tool, you must invest time to learn the language and, perhaps more importantly, to learn to use the higher-level design methods made possible by this powerful language. 3. LSR DESIGN The LSR and LER are the node equipments of the MPLS network. LER works as intermediate node

3 Design and Verification of LSR of the MPLS Network Using VHDL 17 between access networks and MPLS domain; and LSR works as the high speed MPLS router within the MPLS network. In this chapter, we focus on the pin details of the LSR, its specifications and its top level design. Figure 3: Pin Diagram of the LSR When packet Val input is asserted, the data on to the packet_in input is written into the respective FIFO. If unread data are present into the FIFO, it generates the request for the process to the arbiter module. When arbiter module is enabled by the control state machine module, it gives grant as per the request given by the FIFO modules and its priority. Once the control state machine receives the grant, it disables the arbiter module and request of the respective FIFO. It reads the first data of the respective FIFO and retrieves the label and requests the label information base module to compare it with the internal static table. The label information base module reads the input label, compares it with the table, decodes the configured instruction and gives valid new modified output label and output port number on which packet is to be transmitted. When the Control state machine module receives the new label, it transmits the new label, reads the data from the respective FIFO and transmits all the data. It also enables the arbiter module for the next grant. 4. THE LSR VERIFICATION The LSR module needs to verify for push, pop and swap operation for all combination of the input ports and output ports. Also read write operations of the control registers needs to verify. The block diagram of the verification environment is given below. The initial values of the control registers and few data pattern are written into the control registers and read back to verify the read and write operations. To verify the LSR for different input labels, instructions and port information, the input label registers, output labels registers and control registers needs to write with the valid values. These values are listed into the input_state.txt files with other test scenarios. The packet control module reads the input_state.txt file and generates enable signals for the other modules as per the data listed into the input_state.txt file. The read/write control module is responsible for verifying the read write operation and configuration of the control registers for different input labels and its instructions using configuration interface. The packet gen modules are responsible for generating packets of the different length and label. The monitor modules receive the packets transmitted by the LSR and write them into monitor.txt files. The checker module reads the input and monitors files, compares the data sequentially and generates the final result file. 4.1 Simulation As shown in figure 6, input port2 and port 3 are giving data to the LSR and as per the LIB instruction it is forwarded on the port1.before output port 1 completes transactions for Input Port2, input port 3 starts giving data. The LSR continue with the transactions for input Port2 until the FIFO2 is empty and after that it starts transactions for the input port3. Also as first data written into the FIFO3, lsr_busy_3 is asserted high to indicates LSR is busy on input port3 and not able to receive the next packet.

4 18 Figure 4: Block Diagram OF the LSR Suvarna A. Jadhav and U.L. Bombale

5 Design and Verification of LSR of the MPLS Network Using VHDL 19 Figure 8: Simulation Result 5.1 Design Five LSRs are connected to create a network with six external input and output ports. Inter connections between the LSRs with the port number and external input and output ports interfaces are shown in figure 7. Figure 5: Block Diagram of Verification of LSR 5. THE LSR NETWORK DESIGN AND VERIFICATION The MPLS network is created by interconnection between number of LSRs and LERs. The design and verification of the LSRs are explained above. Using LSR s instances and interconnections between them, network is created. The simulation result is shown in figure 7. Figure 6: Simulation of LSR Verification Figure 7: Block Diagram of LSR Network 6. CONCLUSION In this paper, first the MPLS network is explained. Then it explains the layer where the network sits.we have seen the implementation of one of the elements of the network, LSR. The LSR deals with the input LER to get the input packets and after packets hopping on the route the last LSR sends the data packets to the output LER. LSR-LSR hopping happens with the use of labels which are attached to the MPLS packets as they enter into the network. This process takes place using internal modules such as control state machine, FIFO, arbiter and label information base.explaining the each module and putting simulation results for all modules, report gives the details about how exactly LSR works, to forward the packets received by it, showing the simulation results snapshots. Simulation results also show the time required for data transfer in terms of the clock. The verification of the design is done at two levels, firstly only one LSR is tested which we can call as low level abstraction and then the network of LSRs is tested which we can call as high level of abstraction. For verification, inputs are given through text files and output is received in another text file which shows success or failures of the design. The synthesis report shows the use of the device in percentage and maximum frequency (Minimum period: 6.962ns Maximum Frequency: MHz) at which we can work on with the LSR network. REFERENCES [1] Modeling an MPLS Network.pdf xst.pdf

6 20 Suvarna A. Jadhav and U.L. Bombale [2] MPLS, Charter, IETF, ietf.org/ html.charters/mpls-charter.html [3] Multiprotocol Label Switching (MPLS), International Engineering Consortium, [4] MPLS Guide, Ennovate Networks, Inc Switch/Router [5] K. Toda, K. Nishida, E. Takahashi, N. Michell, and Y. Yamaguchi, Design and Implementation of a Priority Forwarding Router Chip for Real-time Interconnection Networks, International Journal of Mini and Microcomputers, 17(1), pp , [6] S. Keshav and R. Sharma, Issues and Trends in Router Design, IEEE Communications Magazine, 36(5), pp , May [7] N. Yamanaka, E. Oki, H. Hasegawa, and T.M. Chen, User-Programmable Flexible ATM Network Architecture Active-ATM-Experimental Results, Third IEEE Symposium on Computers & Communications, pp , June 30-July 02, 1998, Athens, Greece. [8] Jack Foo, A Survey of Service Restoration Techniques in MPLS Networks, Australian Telecommunications, Networks and Applications Conference, ATNAC December 2003.