Best Practises for LabVIEW FPGA Design Flow. uk.ni.com ireland.ni.com

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1 Best Practises for LabVIEW FPGA Design Flow 1

2 Agenda Overall Application Design Flow Host, Real-Time and FPGA LabVIEW FPGA Architecture Development FPGA Design Flow Common FPGA Architectures Testing and Compilation 2

3 Application Development with LabVIEW Requirements Gathering Application Architecture Development Testing & Validation Deployment 3

4 Application Development with LabVIEW Requirements Gathering Application Architecture Development Testing & Validation Deployment 4

5 Real-Time/FPGA Applications Control System Automated Test Safety & Reliability 5

6 RIO Architecture Host PC RT Target FPGA Inter-process Communication Ethernet Communication Inter-process Communication Inter-process Communication 6

7 Why use an Field Programmable Gate Array (FPGA)? Execution: Speed, Determinism and Reliability Faster control Custom high speed protocols High speed interlocking/monitoring/alarming Signal Processing Fast signal processing Process information from other PXI modules via peer to peer Access a streamed waveform with custom filtering Application Requirement Pre-built FPGA IP Application is a highly parallel process Using Compact RIO and therefore FPGA 7

8 FPGA Design Flow 8

9 FPGAs are Dataflow Systems E F Implementing Logic on FPGA: F = {(A+B)CD} E A B C D 9

10 FPGAs are Dataflow Systems E F Implementing Logic on FPGA: F = {(A+B)CD} E A B C D 10

11 FPGAs are Dataflow Systems Implementing Logic on FPGA: F = {(A+B)CD} E LabVIEW FPGA Code E F A B C D 11

12 FPGAs are Parallel Dataflow Systems E F A B C D Z W X Y 12

13 FPGAs are Parallel Dataflow Systems E F A B C D Z W X Y 13

14 FPGA vs Microprocessor Development Task Microprocessor FPGA Paradigm Procedural Parallel Execution Executed commands Logic gates, No OS Maths Up to 64-bit Double Integer & Fixed Threading 10s threads per app Infinite, by design Timing Millisecond Nanosecond Memory Very large Small Compilation Time Near instant 10min..5 Hours...21 Hours.. Development Environment Graphical (LabVIEW) Graphical (LabVIEW FPGA) 14

15 Using the LabVIEW Project Windows System LabVIEW RT System FPGA Windows VI Network Comm. Host VI Comm. FPGA VI LabVIEW for Windows LabVIEW Real- Time LabVIEW FPGA 15

16 FPGA Design Flow Requirements Pre-compile Verification Floor Planning and Placement Architectural Design Logic Synthesis Routing Compilation All handled by LV and Xilinx compiler tools Logic Design Formal Verification Formal Post Layout Timing Analysis Component Integration Post Synthesis Timing Analysis Final Test Harness 16

17 Architectural Design 17

18 Architectural Design for FPGA Host Application Where to begin?... Look at your requirements Break down your problem Define purpose of the FPGA Define its inputs and outputs Define your internal architecture Other device(s) Realtime FPGA Component Component Unit Unit Component Component 18

19 FPGA Architecture: Interfaces 3 main interfaces Interface to external world i.e., IO (C-Series modules or other) Interface to control system i.e., RT host Don t forget... Other devices via Peer to peer data streaming FPGA RT IO FPGA 19

20 External Interfaces IO is defined by FPGA front end modules Add to project Drop I/O nodes onto the block diagram LV FPGA takes care of the rest RIO advanced funtions (e.g., FlexRIO) Access individual I/O pins via CLIP nodes, at 40 MHz within SCTL Access to onboard RAM at high data rates 20

21 Data to the Host Method 1 The Read/Write Controls method can be used for communicating current value data Host VI FPGA VI 21

22 Data to the Host Method 2 DMA FIFOs are an efficient mechanism for streaming data from the FPGA to RTOS Most RIO hardware targets have 3 dedicated DMA channels 22

23 FPGA Architectures Relatively easy and simple Getting data from C-Series modules into LV Real-Time Medium complexity Streaming data, perhaps synchronised with host/other devices, fast control loops Advanced FPGA designs Integrating existing IP, custom communication protocols, high speed deterministic processing, pipeline processing 23

24 Higher level communication with FPGA Scan Mode Interface Hybrid Mode 24

25 Simple: FPGA as a basic interface to I/O I/O to and from C-Series modules in a CompactRIO Timing Engine Communication Loop 25

26 Medium complexity: RIO Control LabVIEW 2012 FPGA Control on CompactRIO (Sample Project) 26

27 Medium complexity: Techniques Architecture Data Streams: DMA FIFOs to create continuous sample/finite length (CompactRIO Waveform Reference library) State Machine: Enum case-statement control Fast Control: Input -> Fast signal processing -> Output Truly parallel :Utilitise FPGA real power, multiple processing loops Implementation Configuration and setup: Use front panel controls/indicators Group like data together: Clusters (data rates, PID gains) Watchdogs: Monitor communication Check error conditions: FIFO timeout, sample rate overruns 27

28 Advanced FPGA design: Example State machine control with and interupt driven DMA FIFOs, custom analog input and outputs 80 MHz, PIDs, filtering... Custom Analog Input clocked by FlexRIO CLK input via CLIP 80 MHz (SCTL) TS FIFO A Tx Control State Machine STCL 40 MHz (basic enum-case statement state machine) IRQ driven data control Controls data flow to host Application Processing Logic SCTL 40 MHz TS FIFO A Rx Logic and addressing Dual port memory blocks DMA FIFOs TS FIFO A Tx Custom Analog Output clocked by derived (x2) 80 MHz (SCTL) (with interpolation) TS FIFO A Rx Lower speed peripheral IO via SPI and I2C comms SCTL 40 MHz Custom Custom PID PIDs with filtering (multiple with custom filtering ~100 khz 28

29 Advanced designs: Techniques Architecture State machine controlled data flow IRQ driven DMA FIFO IP Integration Custom filtering (COREGEN tools, LV Digital Filter Design Toolkit) Custom communication protocols Implementation Use single cycle timed loops (SCTLs) Communicate across multiple clock domains P2P streaming from other devices Fully utilise DMA FIFOs bandwidth 29

30 Compile Synthesis Compilation VI DFIR LLVM EXE LabVIEW Compiler FPGA VI HDL Netlist Bitfile LabVIEW Back End Xilinx ISE 30

31 Design Flow Summary Break down your problem into components Identify FPGA interfaces and internal architecture Highly dependant on specific application requirements Use reference designs as examples Implementation Design and test algorithms first on host computer (most resources) Translate design into LV FPGA (bearing in mind the FPGA constraints) Testing the code Pre-compile Test code on host then with random or simulated inputs minimise number of compiles Create unit tests for individual modules and a full system test harness using host interface techniques 31

32 Design Flow Best Practises Modularise your code to ease debug, testing and code re-use Choose the right architecture for you Keep IO on top level diagram Use space efficiently (numeric sizing, FXP etc) Limit front panel objects Add safe error states and communication watchdogs Manage interface bandwidth e.g. data rates and FIFO sizes Decimate higher rates (with filtering if necessary) to rate required on RT Validate throughout design especially pre-compile Process where most appropriate (RT, CPU or FPGA) Parallel computation on FPGA vs. complex floating point arithmatic on RT 32

33 LabVIEW RIO Evaluation Kit 90-day LabVIEW FPGA & LabVIEW Real-Time evaluation Step-by-step tutorials and configuration wizard NI RIO evaluation device with daughter card for easy access to I/O Orderable now at ni.com/rioeval 33

34 Build on what you have learned today Recommended Courses LabVIEW Core Courses LabVIEW FPGA LabVIEW RealTime 1 LabVIEW FPGA Performance 34

35 Questions? 35