Switching Circuits & Logic Design

Transcription

1 Swithing iruits & Logi Design Jie-Hong Roland Jiang 江介宏 Department of Eletrial Engineering National Taiwan University Fall 23 9 Multiplexers, Deoders, and Programmable Logi Devies 2

2 Outline Introdution Multiplexers Three-state buffers Deoders and enoders Read-only memories Programmable logi devies Deomposition of swithing funtions 3 Introdution uilding bloks of logi design Gates More omplex integrated iruits Multiplexers, deoders, enoders, 3-state buffers, ROMs, PLs, PL, PLDs, FPGs, et. Integrated iruits Small-sale integration (SSI) Roughly ~ gates NND, NOR, ND, OR, inverters, flip-flops Medium-sale integration (MSI) Roughly ~ gates dders, multiplexers, deoders, registers, ounters Large-sale integration (LSI) Roughly ~ gates Memories, miroproessors Very-large-sale integration (VLSI) Roughly + gates

3 Multiplexers Multiplexer (data seletor, MUX) Selet one of the data inputs and onnet it to the output terminal I I 2-to- MUX I I = I when = I when = = 'I +I 5 Multiplexers I Data inputs I I I 2 I 3 -to- MUX I I 2 I 3 I I 5 8-to- MUX I 6 I 7 ontrol inputs = ''I +'I +'I 2 +I 3 = '''I +''I +''I 2 +'I 3 +''I +'I 5 +'I 6 +I 7 6

4 Multiplexers -to- MUX realization using 2-to- MUXes = ''I +'I +'I 2 +I 3 I I I 2 I 3 We will learn later how to realize any oolean funtion with MUXes (Shannon expansion) 7 Multiplexers -to- MUX realization using two-level ND-OR logi = ''I +'I +'I 2 +I 3 I I I 2 I 3 8

5 Multiplexers General 2 n -to- MUX 2 n data inputs 2 n -to- MUX n 2 k m k I k n ontrol inputs 9 Multiplexers Multi-bit data seletion = X when = Y when = X, Y are multi-bit words 2-to- X Y z z z 2 z 3 2-to- 2-to- 2-to- 2-to- x y x y x 2 y 2 x 3 y 3

6 uffers Logi gates have limited driving apability Gate output an only drive a limited number of other gate inputs without degrading iruit performane uffers an be inserted to inrease the driving apability of a gate output F X Y = X uffer X Y Inverter pair uffers Multi-stage buffer insertion for high fan-out gates mortize apaitive loads 2

7 Three-State uffers Diret onnetion of two or more gate outputs together is dangerous Use of three-state (tri-state) buffers permits the onnetion =, when = Hi-,when = 3 Three-State uffers Four kinds of three-state buffers

8 Three-State uffers Data seletion using three-state buffers D 2-to- MUX D re the set of three-state buffers funtionally omplete? 5 Three-State uffers iruit with two three-state buffers D S S2 F F S X S2 X X X X X X X X X X 6

9 Three-State uffers ppliations Data seletion using tri-state buffers (alternative to MUXes) Example Data ommuniation over a shared hannel (bus) Tri-state bus E -bit adder Sum En En En EnD out D Only one of {En, En, En, EnD} is ative, i.e., they are mutually exlusive 7 Three-State uffers ppliations Integrated iruit with bi-diretional input/output pin i-diretional I/O pin an be used as an input pin and as an output pin, but not both at the same time i-diretional Input-Ouput Pin Integrated Logi iruit Output Input EN 8

10 Deoders and Enoders Deoders 3-to-8 line deoder Exatly one output line will be for eah ombination of input values a b 3-to-8 line deoder y =a'b'' y =a'b' y 2 =a'b' y 3 =a'b y =ab'' y 5 =ab' y 6 =ab' y 7 =ab a b y y y 2 y 3 y y 5 y 6 y 7 9 Deoders and Enoders Deoders -to- deoder with inverted outputs (indiated by irles) Exatly one output line will be for eah ombination of input values Truth table lok diagram D 72 D input Deimal Output Logi diagram m 9 'm 8 'm 7 'm 6 'm 5 'm 'm 3 'm 2 'm 'm ' Inputs D Outputs D

11 Deoders and Enoders Deoders n-to-2 n line deoder generates all 2 n minterms (or maxterms) of the n input variables The outputs are defined by the equations y i = m i, for i =,, 2 n - (noninverted outputs) y i = m i ' = M i, for i =,, 2 n - (inverted outputs) an be used for funtion onstrution Example f(a,b,,d) = m +m 2 +m = (m 'm 2 'm ')' f2(a,b,,d) = m +m 7 +m 9 = (m 'm 7 'm 9 ')' a b d -to- line deoder m ' m 2 ' m ' m 7 ' m 9 ' f f 2 Note that m i ' with i is not available in the -to- line deoder 2 Deoders and Enoders Enoders n enoder performs the inverse funtion of a deoder 8-to-3 priority enoder If input y i is with y j = for all j > i, then the outputs (a,b,) represent a binary number equal to i Output d is if any input is, otherwise, d is y y y 2 y 3 y y 5 y 6 y 7 8-to-3 Priority Enoder a b d y y y 2 y 3 y y 5 y 6 y 7 X X X X X X X X X X X X X X X X X X X X X X X X X X X X a b d don t are distinguished by d 22

12 Read-Only Memories read-only memory (ROM) stores an array of binary data, whih an be read out whenever desired, but annot be hanged under normal operating onditions n output pattern stored in the ROM is alled a word n input ombination serves as an address whih an selet one of the words stored in the ROM lok diagram 3 input lines (address) ROM 8 Words x its F F F 2 F 3 output lines (word) Truth table for ROM F F F 2 F 3 typial data stored in a ROM (here, 2 3 words of bits eah) 23 Read-Only Memories ROM whih has n input lines and m output lines ontains an array of 2 n words, and eah word is m bits long The input lines serve as an address to selet one of the 2 n words (2 n m) ROM an realize m funtions of n variables n input lines ROM 2 n Words x m its m output lines size = 2 n m (bits) n input variables : m output variables : typial data array stored in ROM (here, 2 n words of m bits eah) 2

13 Read-Only Memories asi Struture ROM onsists of a deoder and a memory array ROM n input lines Deoder Memory rray 2 n Words m its 2 n lines m output lines 25 Read-Only Memories asi Struture Example The ontents of a ROM are usually speified by a truth table m i m m m m 6 F F F 2 F 3 F F = m(,,,6) = ''+' F = m(2,3,,6,7) = +' F 2 = m(,,2,6) = ''+' F 3 = m(2,3,5,6,7) = + 3-to-8 Deoder m =''' m ='' m 2 ='' m 3 =' m ='' m 5 =' m 6 =' m 7 = swithing element F F F 2 F 3 output lines 26 word lines

14 Read-Only Memories asi Struture Multiple-output ombinational iruits an be realized using ROMs Example 6 W 5 X ROM Y 3 2 Input WXY Hex Digit D E F SII ode for Hex Digit ROM inputs W X Y -to-6 Deoder m m m 2 m 3 m m 5 m 6 m 7 m 8 m 9 m m m 2 m 3 m m ROM outputs 27 Read-Only Memories ommon types of ROMs Mask-programmable ROMs t the time of manufaturing, data array is permanently stored in a mask-programmable ROM Programmable ROMs (PROMs) an be programmed one Eletrially erasable programmable ROM (EEPROMs); flash memories an be erased and reprogrammed a limited number of times 28

15 Programmable Logi Devies programmable logi devie (PLD) is a general name for a digital I apable of being programmed to provide a variety of different logi funtions For a digital system designed using a PLD, hanges in the design an easily be made by hanging the programming of the PLD without hanging the wiring ommon types of PLD Programmable logi arrays (PLs) Programmable array logi (PL) speial ase of PLs 29 Programmable Logi Devies Programmable Logi rrays programmable logi array (PL) performs the same basi funtion as a ROM PL with n inputs and m outputs an realize m funtions of n variables PL implements an SOP expression, while a ROM implements a truth table The deoder of a ROM is replaed with an ND array realizing seleted produt terms of the input variables; the OR array ORs together the produt terms PL n input lines ND rray OR rray k word lines m output lines 3

16 Programmable Logi Devies Programmable Logi rrays Example Inputs OR rray +V +V +V +V ND rray +V F F F 2 F 3 PL table Produt Term Inputs Outputs F F F 2 F 3 F = ''+' F = '+ F 2 = ''+' F 3 = + F F F 2 F 3 Outputs 3 Programmable Logi Devies Programmable Logi rrays Example (Eq. 7-23b) f = a'bd+abd+ab''+b' f 2 = +a'bd f 3 = b+ab''+abd Inputs a b d PL struture a bd abd ab b b PL table a b d f f 2 f 3 a bd abd ab b b F F 2 F 3 Outputs word lines 32

17 Programmable Logi Devies Programmable Logi rrays PL table for a PL differs from a truth table for a ROM In a truth table, exatly one row will be seleted by eah ombination of input values In a PL table, zero, one, or more rows may be seleted by eah ombination of input values (sine eah row represents a general produt term) To determine the value of f i for a given input ombination, the values in the seleted rows must be ORed together ommon types of PLs Mask-programmable PLs Field-programmable PLs (FPLs) 33 Programmable Logi Devies Programmable rray Logi The programmable array logi (PL) is a speial ase of PL in whih the ND array is programmable and the OR array is fixed PL is less expensive and easier to program D Fixed OR array D P Produts P P 2 P 2 O P 3 P 3 P P 5 P 6 P P 5 P 6 O 2 Programmable ND array O O 2 PL devie Standard PL representation 3

18 Programmable Logi Devies Programmable rray Logi Example I F Fixed OR gate with fixed input size Programmable produt terms F F 5 Output I 2 F 8 Unprogrammed PL segment I I I 2 '+I 'I 2 I 2 Programmed PL segment 35 Programmable Logi Devies Programmable rray Logi Notation I I I 2 '+I 'I 2 I 2 Non-Inverted Output Inverted Output 36

19 Programmable Logi Devies Programmable rray Logi Example PL implementation of full adder X Y in Sum out X Y in Sum Sum = X'Y' in +X'Y in '+XY' in '+XY in out = X in +Y in +XY out 37 Programmable Logi Devies Programmable rray Logi Unlike PL, the ND terms annot be shared among two or more OR gates Eah funtion to be realized an be simplified by itself without regard to ommon terms For a given type of PL, the number of ND terms that feed eah output OR gate is fixed and limited Need to hoose a PL with an appropriate number of OR-gate inputs 38

20 Other Programmable Logi Devies omplex programmable logi devies (PLDs) 9.7 (skipped) Field programmable gate arrays (FPGs) 9.8 (skipped) 39 Funtion Generators Implementation of a -input Lookup Table (LUT) bits stored in the LUT (enable/disable minterms) a b d F x x x 5 x i {,} x x a' b' ' d' a' b' ' d F x 5 ab d

21 Funtion Generators nother implementation of a Lookup Table (LUT) F a b d F x x x 5 a b b a i {,} d x x Deomposition of Swithing Funtions To implement a oolean funtion with more than inputs using -variable funtion generators, it has to be deomposed into subfuntions, eah with inputs Shannon s expansion theorem provides a deomposition method 2

22 Deomposition of Swithing Funtions Shannon s Expansion Theorem Shannon s expansion theorem y expanding a funtion f(a,b,,d) about variable a, the following equality holds: f(a,b,,d) = a' f(,b,,d) + a f(,b,,d) = a'f +af Example f(a,b,,d) = 'd'+a'b'+bd+a' = a'('d'+b'+bd)+a('d'+bd+') =a'('d'+b'+d)+a('+bd) f f fewer inputs 3 Deomposition of Swithing Funtions Shannon s Expansion Theorem Shannon s expansion using K-map ab d ab a= a= d f f f a=, f ='d'+b'+d a=, f ='+bd

23 Deomposition of Swithing Funtions Shannon s Expansion Theorem Shannon s expansion theorem y expanding a funtion f(a,b,,d) about variable a, the following equality holds: f(x,,x i-,x i,x i+,,x n ) = x i ' f(x,,x i-,,x i+,,x n ) + x i f(x,,x i-,,x i+,,x n ) = x i ' f +x i f fewer inputs 5 Deomposition of Swithing Funtions Multiplexers and Shannon Expansion ny 5-variable funtion an be realized using two -variable funtion generators and a 2-to- MUX pply Shannon s expansion one: f(a,b,,d,e) = a' f(,b,,d,e) + a f(,b,,d,e) = a'f +af b d e b d e FG FG F F a F 6

24 Deomposition of Swithing Funtions Multiplexers and Shannon Expansion ny 6-variable funtion an be realized using four - variable funtion generators and three 2-to- MUXes pply Shannon s expansion twie: G(a,b,,d,e,f)=a' G(,b,,d,e,f)+a G(,b,,d,e,f)=a'G +ag G = b' G(,,,d,e,f)+b G(,,,d,e,f) = b'g +bg G = b' G(,,,d,e,f)+b G(,,,d,e,f) = b'g +bg G(a,b,,d,e,f) = a'b'g +a'bg +ab'g +abg d ef d ef d ef d ef FG FG FG FG G G G G b b G G a G 7 Deomposition of Swithing Funtions Multiplexers and Shannon Expansion Exerises Realize F=''+ using a -to- MUX Realize F='''+'D+'+D'+'D' using an 8-to- MUX Realize F='''+'D+'+D'+'D' using a -to- MUX and 2-input funtion generators 8