ATI 215PADAKA12FG Graphics Processor extracted from ATI Radeon X195 Pro Graphics Card Structural Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks. 3685 Richmond Road, Suite 5, Ottawa, ON K2H 5B7, Canada Tel: 613.829.414 Fax: 613.829.515 www.chipworks.com
Structural Analysis Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 2 Device Overview 2.1 Package and Die Overview 2.2 Die Features 2.3 Selected Package Analysis 3 Process 3.1 General Structure 3.2 Passivation and Dielectrics 3.3 Metallization 3.4 Vias and Contacts 3.5 Logic and I/O Transistors, and STI 3.6 Isolation 3.7 Wells 4 SRAM Cell Analysis 4.1 SRAM Cell Overview and Schematics 4.2 8T SRAM Plan View Analysis 4.3 8T SRAM Cross-Sectional Analyses (Parallel to Bitlines) 4.4 6T SRAM Plan View Analysis 4.5 6T SRAM Cross Sectional Analyses 5 Materials Analysis 5.1 Materials Analysis Overview 5.2 SEM-EDS Analysis 5.3 TEM-EDS Analysis of the Dielectrics 5.4 TEM-EDS Analysis of the Metals 5.5 TEM-EDS Analysis of Transistors
Structural Analysis 6 Critical Dimensions 6.1 Package and Die 6.2 Dielectrics, Metals and Vias 6.3 Logic Transistors, Polysilicon, and STI 6.4 SRAM 7 Statement of Measurement Uncertainty and Scope Variation 8 References Report Evaluation
Overview 1-1 1 Overview 1.1 List of Figures 2 Device Overview 2.1.1 Package Top 2.1.2 Package Bottom 2.1.3 Package X-Ray 2.1.4 Die Photograph 2.1.5 Die Markings 2.1.6 Die Photograph Backside Polysilicon 2.2.1 Die Corner A 2.2.2 Die Corner B 2.2.3 Die Corner C 2.2.4 Die Corner D 2.2.5 Hexagonal Pad Arrangement 2.2.6 Square Pad Arrangement 2.2.7 Pad Under Bump Metallization 2.2.8 Standard Logic Layout at Polysilicon 2.2.9 Standard Logic Cell at Polysilicon 2.2.1 Dummy Gates in Logic Layout at Polysilicon 2.2.11 Gate Array at Polysilicon 2.2.12 Dummy Polysilicon Array Separating Circuit Blocks 2.3.1 Silicon Die and Fiberglass Substrate 2.3.2 Solder Bump Overview 2.3.3 Solder Bump/Die Interface 2.3.4 Solder Bump/Package Land Interface 2.3.5 Package Ball 3 Process 3.1.1 General Die Structure 3.1.2 Die Edge 3.1.3 Die Seal 3.2.1 Passivation FESEM 3.2.2 ILD 7 FESEM 3.2.3 ILD 7 TEM 3.2.4 ILD 6 TEM 3.2.5 ILD 5 TEM 3.2.6 ILD 4 TEM 3.2.7 ILD 3 TEM 3.2.8 ILD 2 TEM 3.2.9 ILD 1 TEM 3.2.1 PMD FESEM 3.2.11 PMD TEM 3.2.12 STI Under Polysilicon and Gates FESEM
Overview 1-2 3.3.1 Minimum Pitch Metal 8 3.3.2 Metal 7 to Metal 1 and ILD Stack 3.3.3 Minimum Pitch Metal 7 FESEM 3.3.4 Metal 7 TEM 3.3.5 Minimum Pitch Metal 6 FESEM 3.3.6 Metal 6 TEM 3.3.7 Metal 6 Liner TEM 3.3.8 Minimum Pitch Metal 5 FESEM 3.3.9 Metal 5 TEM 3.3.1 Minimum Pitch Metal 4 3.3.11 Metal 4 TEM 3.3.12 Minimum Pitch Metal 3 3.3.13 Metal 3 TEM 3.3.14 Minimum Pitch Metal 2 3.3.15 Metal 2 TEM 3.3.16 Minimum Pitch Metal 1 FESEM 3.3.17 Metal 1 TEM 3.4.1 Minimum Pitch Via 7 3.4.2 Minimum Pitch Via 6 and 5 3.4.3 Minimum Pitch Via 4 and 3 FESEM 3.4.4 Via 4 TEM 3.4.5 Via 3 TEM 3.4.6 Minimum Pitch Via 2 and 1 3.4.7 Via 1 TEM 3.4.8 Contact to Poly TEM 3.4.9 Contact to S/D TEM 3.4.1 Contact to S/D, Top TEM 3.4.11 4 Contact to S/D, Bottom TEM 3.4.12 Contacts to Polysilicon TEM 3.4.13 Butted Contact in 6T SRAM 3.5.1 General View of Logic MOS Transistors and Minimum Width STI FESEM 3.5.2 Logic Transistor Gate (Length) TEM 3.5.3 8T SRAM NMOS Transistor Gate (Length) TEM 3.5.4 8T SRAM PMOS Transistor Gate (Length) TEM 3.5.5 Transistor Gate (Width) TEM 3.5.6 Logic Transistor Gate Dielectric 3.5.7 NMOS Gates at Silicon Delineation 3.5.8 PMOS Gates at Silicon Delineation 3.5.9 I/O Transistor Gate TEM 3.5.1 I/O Transistor Gate Dielectric TEM 3.6.1 Minimum Width STI 3.7.1 Logic Area P-Well and N-Well SCM 3.7.2 Logic Area P-Well Profile SIMS 3.7.3 Logic Area N-Well Profile SIMS 3.7.4 SRAM Area P-Well Profile SIMS 3.7.5 SRAM Area N-Well Profile SIMS
Overview 1-3 4 SRAM Cell Analysis 4.1.1 Dual Port 8T SRAM Cell Schematic 4.1.2 6T SRAM Cell Schematic 4.2.1 8T SRAM at Metal 3 4.2.2 8T SRAM at Metal 2 4.2.3 8T SRAM at Metal 1 4.2.4 8T SRAM at Polysilicon 4.2.5 8T SRAM at Silicon 4.3.1 NMOS Pull Down Transistors TEM 4.3.2 NMOS Access Transistors TEM 4.3.3 PMOS Pull Up Transistors TEM 4.4.1 6T SRAM at Polysilicon 4.4.2 6T SRAM at Silicon 4.4.3 6T SRAM at Metal 1 4.4.4 6T SRAM at Metal 2 4.4.5 6T SRAM at Metal 3 4.5.1 NMOS Pull Down and Access Transistors FESEM 4.5.2 PMOS Pull Up Transistors FESEM 5 Materials Analysis 5.2.1 SEM-EDS Spectrum of UBM 1 5.2.2 SEM-EDS Spectrum of UBM 2 5.2.3 SEM-EDS Spectrum of UBM 3 5.2.4 SEM-EDS Analysis of Solder Bump 5.2.5 SEM-EDS Analysis of Package Land Plating (Top) 5.2.6 SEM-EDS Analysis of Package Land 5.3.1 TEM-EDS Spectrum of Passivation 1, 3, and 5 5.3.2 TEM-EDS Spectrum of Passivation 2 and 4 5.3.3 TEM-EDS Spectrum of ILD 7-1 5.3.4 TEM-EDS Spectrum of ILD 7-3 5.3.5 TEM-EDS Spectrum of ILD 7-2 and ILD 7-4 5.3.6 TEM-EDS Spectrum of ILD 6-1 5.3.7 TEM-EDS Spectrum of ILD 6-2 5.3.8 TEM-EDS Spectrum of ILD 6-3 5.3.9 TEM-EDS Spectrum of PMD 2 and PMD 3 5.3.1 TEM-EDS Spectrum of PMD 4 5.3.11 TEM-EDS Spectrum of PMD 5 5.3.12 TEM-EDS Spectrum of STI 5.4.1 TEM-EDS Spectrum of Metal 1 Liner 5.5.1 TEM-EDS Spectrum of Gate Silicide 5.5.2 TEM-EDS Spectrum of MOS S/D Silicide
Overview 1-4 1.2 List of Tables 1 Overview 1.4.1 Device Identification 1.5.1 215PADAKA12FG Device Summary 1.5.2 215PATAKA12FG Process Summary 2 Device Overview 2.3.1 Package and Die Critical Dimensions 3 Process 3.2.1 Measured Dielectric Thicknesses 3.3.1 Measured Metal Line Thicknesses 3.3.2 Minimum Observed Metal Line Horizontal Dimensions 3.4.1 Minimum Observed Via and Contact Pitch 3.5.1 Transistor Horizontal Dimensions 3.5.2 Transistor Vertical Dimensions 4 SRAM Cell Analysis 4.3.1 8T SRAM Cell and Transistor Dimensions 4.5.1 6T SRAM Cell and Transistor Dimensions 6 Critical Dimensions 6.1.1 Package and Die Critical Dimensions 6.2.1 Measured Dielectric Thicknesses 6.2.2 Measured Metal Line Thicknesses 6.2.3 Minimum Observed Metal Line Horizontal Dimensions 6.2.4 Minimum Observed Via and Contact Pitch 6.3.1 Transistor Horizontal Dimensions 6.3.2 Transistor Vertical Dimensions 6.4.1 8T SRAM Cell and Transistor Dimensions 6.4.2 6T SRAM Cell and Transistor Dimensions
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