MITSUBISHI SEMICONDUCTO <pplication Specific Specific Intelligent Power Power Module> FLT-BSE TYPE TYPE INSULTED TYPE TYPE INTEGTED FUNCTIONS ND FETUES Converter bridge for 3 phase C-to-DC power conversion. 3 phase IGBT inverter bridge configured by the latest 3rd. generation IGBT and diode technology. Inverter output current capability IO (Note ): Type Name Motor ating.5 kw/ C IO (%) 7.rms IO (5%; 6sec).5rms (Note ) : The inverter output current is assumed to be sinusoidal and the peak current value of each of the above loading cases is defined as : IOP = IO, < INTEGTED DIE, POTECTION ND SYSTEM CONTOL FUNCTIONS: P-Side IGBTs : Drive circuit, high-level-shift circuit, bootstrap circuit supply scheme for Single Control-Power-Source drive, and under voltage (U) protection. N-Side IGBTs : Drive circuit, DC-Link current sense and amplifier circuits for overcurrent protection, control-supply under-voltage protection (U), and fault output (FO) signaling circuit. Fault Output : N-side IGBT short circuit (SC), over-current (OC), and control supply under-voltage (U). Inverter nalog Current Sense : N-Side IGBT DC-Link Current Sense. Input Interface : 5 CMOS/TTL compatible, Schmitt Trigger input, and rm-shoot-through interlock protective function. PPLICTION coustic noise-less.5kw/ C Class 3 phase inverters, motor control applications, and motors with built-in small size inverter package PCKGE OUTLINES 7± 63± 5 5 9.5 -.5 5.8 3 5 6 6 36 7 8 9 3 5 3 5 6 7 8 9 5.7 (69) 6.6 -.5. 3 5±.5 (5.7) 5.7±.8..6 6.5±.5 3±.5 8.5±.5 6.5±.5 3.5-3 Terminals ssignment :. CBU+. CBU 3. CB+. CB 5. CBW+ 6. CBW 7. D 8. UP 9. P. WP. UN. N 3. WN. FO 5. amp 6. GND. P. 3. S. T 5. N 6. P 7. U 8. 9. W 3. N 55.5 Type name,lotno. (Fig. ) Jan.
MITSUBISHI SEMICONDUCTO <pplication Specific Intelligent Power Module> FLT-BSE TYPE INSULTED TYPE INTENL FUNCTIONS BLOCK DIGM D UP P WP UN N WN FO (amp) U Protection Input signal conditioning (Interlock circuit) Fo Circuit + OC/SC Protection U Protection Level shifter Drive circuit Drive circuit P S T N P U W GND N (Fig. ) MXIMUM TINGS (Tj = 5) INETE PT CC pplied between P-N 5 CC(surge) P or N P(S) or N(S) ±Ic(±Icp) (surge) Each output IGBT collector-emitter static voltage Each output IGBT collector-emitter switching voltage Each output IGBT collector current pplied between P-N, Surge-value pplied between P-U..W, U..W-N pplied between P-U..W, U..W-N = 5, ( ) means IC peak value 5 6 6 ± (±) CONETE PT M Ea IO IFSM I t epetitive peak reverse voltage ecommended C input voltage DC output current Surge (non-repetitive) forward current I t for fusing 3φ rectifying circuit cycle at 6Hz, peak value non-repetitive alue for one cycle of surge current 8 96 65 rms s CONTOL PT D, DB CIN FO IFO Iamp Input signal voltage Fault output supply voltage Fault output current DC-Link IGBT current signal mp output current.5 ~.5 ~ +7.5.5 ~ +7.5 5 Jan.
MITSUBISHI SEMICONDUCTO <pplication Specific Intelligent Power Module> FLT-BSE TYPE INSULTED TYPE TOTL SYSTEM Tj Tstg ISO Junction temperature Storage temperature Module case operating temperature Isolation voltage Mounting torque (Note ) (Fig. 3) 6 Hz sinusoidal C applied between all terminals and the base plate for minute. Mounting screw: M ~ +5 ~ +5 ~ + 5.98 ~.7 (Note ) : The indicated values are specified considering the safe operation of all the parts within the SIPM. The max. ratings for the SIPM power chips (IGBT & FWDi) is Tj < 5. rms N m CSE TEMPETUE MESUEMENT POINT (Fig. 3) THEML ESISTNCE th(jc)q th(jc)f th(jc)f Junction to case Thermal esistance Inverter IGBT (/6) Inverter FWDi (/6) Converter Di (/6).3 3..8 /W /W /W th(cf) Contact Thermal esistance Case to fin thermal, grease applied ( Module).7 /W ELECTICL CHCTEISTICS (Tj = 5, D = 5, DB = 5 unless otherwise noted) CE(sat) EC F IM ton tc(on) toff tc(off) trr Short circuit endurance (Output, rm, and Load Short Circuit Modes) Switching SO Collector-emitter saturation voltage FWDi forward voltage Converter diode voltage Converter diode reverse current Switching times FWDi reverse recovery time Tj = 5, Input = ON, Ic =, D = DB = 5 (Shunt voltage drop not included) Tj = 5, IC = Tj = 5, IF = = M, Tj = 5 / Bridge inductive, Input = 5 CC = 3, IC =, Tj = 5 D = 5, DB = 5 Note: ton, toff include delay time of the internal control circuit. @CC, Input = 5 (One-Shot) Tj (start) 5, 3.5 D = DB 6.5 @CC, Input = 5, Tj 5 IC < OC trip level, 3.5 D = DB 6.5.3.6.5.6.5..9.9.5 8.5..5.3 No destruction FO output by protection operation No destruction No protecting operation No FO output Jan.
MITSUBISHI SEMICONDUCTO <pplication Specific Intelligent Power Module> FLT-BSE TYPE INSULTED TYPE ELECTICL CHCTEISTICS (Tj = 5, D = 5, DB = 5 unless otherwise noted) ID IDB th(on) th(off) i fpwm tdead tint amp(%) amp(%) amp(5%) amp() OC toc SC tsc UD UDr UDB UDBr td tfo IFo(H) IFo(L) Circuit current (verage) Circuit current (verage) Input on threshold voltage Input off threshold voltage Input pull-up resistor PWM input frequency rm shoot-through blocking time Input interlock sensing Inverter DC-Link IGBT current sense voltage output signal Inverter DC-Link IGBT current sense voltage output limit Over current trip level Over current delay time Short circuit trip level Short circuit delay time Trip level Supply circuit under voltage protection Fault output pulse width Fault output current eset level Trip level eset level Delay time Tj = 5, D = 5, in = 5 Tj = 5, D = DB = 5, in = 5 pplied between input terminal-inside power supply, Tj 5 elates to corresponding inputs = ~ + (Note 3) elates to corresponding input (Fig. 6) IC = IOP(%) D = 5 IC = IOP(%) Tj = 5 (Fig. ) IC = IOP(5%) D = 5 IC = (Fig. ) Tj = 5 (Fig. 5) Tj = 5 (Fig. 5) Tj = 5 (Fig. 5) Tj = 5 (Fig. 5) = Tj = 5 (Fig. 5) Tj = 5 (Note ) Open collector output (Note ).8.5..5 3. 5. 9.8..5..6.. 3. 5 (Note 3) : The dead-time has to be set externally by the CPU; it is not part of the SIPM internal functions. (Note ) : Fault output signaling is given only when the internal OC, SC, & U protection circuits are activated. The OC, SC and U protection (and fault output) operate for the lower arms only. The OC and SC protection Fault output is given in a pulse format while that of U protection is maintained throughout the duration of the under-voltage condition... 5.7..5.8.3.8 5 5.. 5.5 5. 35. 3. 3.5.6. 5 kω khz ns m ms µ ECOMMENDED OPETING CONDITIONS CC D DB D, DB CIN(ON) CIN(OFF) tdead fpwm txx ripple Input on voltage Input off voltage rm shoot-through blocking time Module case operating temperature PWM Input frequency llowable minimum input on-pulse width pplied across P-N terminals pplied between D-GND pplied between CBU+ & CBU, CB+ & CB, CBW+ & CBW pplied between UP P WP UN N WN and GND elates to corresponding inputs, Tj 5 3.5 3.5.. 3 5. 5. 6.5 6.5 +.8 5. 5 / khz INETE DC-LINK IGBT CUENT NLOGUE SIGNLING OUTPUT (TYPICL) 5 D = 5 Tj = 5 amp amp (%) amp () 3 amp (%) 3 ctual Load Peak Current (%), (IC = IO ) (Fig. ) Jan.
MITSUBISHI SEMICONDUCTO <pplication Specific Intelligent Power Module> FLT-BSE TYPE INSULTED TYPE CUENT BNOMLITY POTECTIE FUNCTIONS Ic() Short circuit trip level SC Over current trip level OC Collector current tw () (Fig. 5) Protection is achieved by monitoring and filtering the N-side DC-Bus current. The over-current protection is activated (after allowing a filtering time of ) when the line current reaches 5% of the rated load-current IO (rms). Similarly, the short circuit protection is activated (after allowing a filtering time of ) when the line current reaches twice the rated collector-current (IC). When a current trip-level is exceeded (OC or SC), all the N-side IGBTs are intercepted (turned OFF) and a fault-signal is output. fter the fault-signal output duration (.8 ms - typ.), the interception is eset at the following OFF input signal. However, since the fault may be repetitive, it is recommended to stop the system after the fault-signal is received and check the fault. The trip-level settings described above are summarized in the following figure: M-SHOOT-THOUGH INTE-LOCK POTECTIE FUNCTION P-Side Input Signal : CIN(p) ON a b N-Side Input Signal : CIN(n) ON a b P-Side IGBT Gate : GE(p) a a3 b N-Side IGBT Gate : GE(n) b3 (Fig. 6) Description: () During the ON-State of either of the upper-arm or the lower-arm IGBT, the inter-lock protection circuit blocks any erroneous ON pulses (resulting from input noise) from triggering the other arm IGBT and thus it prevents the arm-shoot-through situation. () When two ON-signals are received for both the upper and the lower arms, the signal received first will be passed to the IGBT and the second signal will be blocked. The second signal will be passed to its corresponding IGBT immediately after the first signal is OFF. Note: This protective function provides no fault signaling output. The Dead-Time has to be set using the micro-controller (CPU). Operation: a. P-side normal ON-signal P-side IGBT gate turns ON. a. N-side erroneous ON-signal N-side IGBT gate remains OFF. a3. While P-side ON-signal remains P-side IGBT gate remains ON. a. N-side normal ON-signal N-side IGBT gate turns ON. b. N-side normal ON-signal N-side IGBT gate turns ON. b. Simultaneous ON-signals P-side IGBT gate remains OFF. b3. N-side receives OFF-signal N-side IGBT gate turns OFF. b. Immediately after (b3) P-side IGBT gate turns ON. ECOMMENDED I/O INTEFCE CICUIT 5 5 CPU 5.kΩ kω.nf.nf D(5) SIPM UP,P,WP,UN,N,WN Fo (amp) GND(Logic) (Fig. 7) Jan.