APPLICATION AC100V~200V three-phase inverter drive for small power motor control.

Transcription

1 MITSBISHI SEMIODTOR <Intelligent ower ower Module> TYE TYE TEGRTED OWER FTIOS 4th generation (planar) IGBT inverter bridge for 3 phase D-to- power conversion. TEGRTED DRIE, ROTETIO D SYSTEM OTROL FTIOS r upper-leg IGBTS : Drive circuit, High voltage isolated high-speed level shifting, ontrol circuit under-voltage () protection. ote : Bootstrap supply scheme can be applied. r lower-leg IGBTS : Drive circuit, ontrol circuit under-voltage protection (), Short circuit protection (S). Fault signaling : orresponding to a S fault (Low-side IGBT) or a fault (Low-side supply). Input interface : 5 line MOS/TTL compatible, Schmitt Trigger receiver circuit. LITIO 100~200 three-phase inverter drive for small power motor control. Fig. 1 KGE OTLES Dimensions in mm 2-φ4.5± (=75.6) 2.8± Type name, Lot o ±0.3 10±0.3 10±0.3 20± ±0.5 31± ± ±0.5 3~5 28± ±0.2 TERML ODE FB 4 FS FB 8 FS 9 W WFB 13 WFS FO W W 26 67±0.3 79±0.5 B (71) 8±0.5 16±1 or 12.8±1 0.5±0.2 Irrgulor solder remains 0.5MX 1.9±0.05 1± ± MX Irrgulor solder remains 0.5MX 1.75MX 0.8± ±0.5 HET SK SIDE Detail Detail B (t=0.7) Detail (t=0.7)

2 Fig. 2 TERL FTIOS BLOK DIGRM (TYIL LITIO EXMLE) 3 : Tight tolerance, temp-compensated electrolytic type (ote : The capacitance value depends on the WM control scheme used in the applied system). 4 : 0.22~2µF R-category ceramic capacitor for noise filtering. Inrush current limiter circuit High-side input (WM) (5 line) (ote 1,2) Input signal coditioning Level shifter Level shifter Level shifter rotection circuit () Input signal coditioning rotection circuit () Input signal coditioning rotection circuit () Drive circuit Drive circuit Drive circuit B B+ BW+ BW B+ B 4 3 Bootstrap circuit r detailed description of the boot-strap circuit construction, please contact Mitsubishi Electric (ote 6) line input Z Z : ZR (Surge absorber) : filter (eramic capacitor 2.2~6.5nF) (ote : dditionally, an appropriate line-to line surge absorber circuit may become necessary depending on the application environment). Low-side input (WM) (5 line) (ote 1, 2) (ote 4) Fig. 3 1 Drive circuit Input signal conditioning logic rotection circuit FO Fault output (5 line) (ote 3, 5) ontrol supply nder-oltage protection H-side IGBTS M W line output L-side IGBTS ote1: To prevent the input signals oscillation, an R coupling at each input is recommended. (see also Fig. 6) (15 line) 2: By virtue of integrating an application specific type HI inside the module, direct coupling to terminals without any opto-coupler or transformer isolation is possible. (see also Fig. 6) 3: This output is open collector type. The signal line should be pulled up to the positive side of the 5 power supply with approximately 5.1kΩ resistance. (see also Fig. 6) 4: The wiring between the power D link capacitor and the /1 terminals should be as short as possible to protect the against catastrophic high surge voltages. r extra precaution, a small film type snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be mounted close to these and 1 D power input pins. 5: output pulse width should be decided by putting external capacitor between and terminals. (Example : =22nF tfo=1.8ms (Typ.)) 6: High voltage (600 or more) and fast recovery type (less than 100ns) diodes should be used in the bootstrap circuit. D Fig. 3 EXTERL RT OF THE ROTETIO IRIT Drive circuit Short ircuit rotective Function (S) : S protection is achieved by sensing the L-side D-Bus current (through the external shunt resistor) after allowing a suitable filtering time (defined by the R circuit). When the sensed shunt voltage exceeds the S trip-level, all the L-side IGBTs are turned OFF and a fault signal () is output. Since the S fault may be repetitive, it is recommended to stop the system when the signal is received and check the fault. I () H-side IGBTS W S rotection Trip Level External protection circuit L-side IGBTS 1 Shunt Resistor (ote 1) R Drive circuit B rotection circuit (ote 2) ote1: In the recommended external protection circuit, please select the R time constant in the range 1.5~2.0. 2: To prevent erroneous protection operation, the wiring of, B, should be as short as possible. 0 ollector current waveform 2 tw ()

3 MXIMM RTGS (Tj = 25, unless otherwise noted) ERTER RT Symbol arameter Ratings nit (surge) ES ±I ±I Tj Supply voltage Supply voltage (surge) ollector-emitter voltage Each IGBT collector current Each IGBT collector current (peak) ollector dissipation Junction temperature pplied between - pplied between - T = 25 T = 25, instantaneous value (pulse) T = 25, per 1 chip (ote 1) ~+150 ote 1 : The maximum junction temperature rating of the power chips integrated within the is 150 (@ T 100 ) however, to ensure safe operation of the, the average junction temperature should be limited to Tj(ave) 125 (@ T 100 ). W OTROL (ROTETIO) RT Symbol arameter Ratings nit D DB FO IFO S Input voltage Fault output supply voltage Fault output current urrent sensing input voltage pplied between 1-, 1- pplied between FB-FS, FB-FS, WFB-WFS pplied between,, W-,,, W- pplied between FO- Sink current at FO terminal pplied between ~ ~D ~D+0.5 m TOTL SYSTEM Symbol arameter Ratings nit (ROT) Self protection supply voltage limit D = 13.5~16.5, Inverter part Tj = 125, non-repetitive, less than 2 (short circuit protection capability) T Module case operation temperature (ote 2) Tstg iso Storage temperature Isolation voltage 60Hz, Sinusoidal, 1 minute, connection pins to heat-sink plate ~ ~ rms ote 2 : T MESREMET OT ontrol Terminals Heat sink boundary Heat sink Tc Tc ower Terminals

4 THERML RESISTE Symbol Rth(j-c)Q Rth(j-c)F Rth(c-f) arameter Junction to case thermal resistance ontact thermal resistance Inverter IGBT part (per 1/6 module) Inverter FWD part (per 1/6 module) ase to fin, (per 1 module) thermal grease applied Min. Typ. Max nit /W /W /W ELETRIL HRTERISTIS (Tj = 25, unless otherwise noted) ERTER RT E(sat) E ton trr Symbol tc(on) toff tc(off) IES arameter ollector-emitter saturation voltage FWD forward voltage Switching times ollector-emitter cut-off current D = DB = 15 I = 20, Tj = 25 = 0 I = 20, Tj = 125 Tj = 25, I = 20, = 5 = 300, D = DB = 15 I = 20, Tj = 125, = 5 0 Inductive load (upper-lower arm) E = ES Tj = 25 Tj = 125 Min. Typ. Max nit m OTROL (ROTETIO) RT Symbol D DB ID FOH FOL FOsat tdead S(ref) DBt DBr Dt Dr tfo th(on) th(off) ircuit current arameter Fault output voltage rm shoot-through blocking time Short circuit trip level Supply circuit under-voltage protection Fault output pulse width O threshold voltage OFF threshold voltage pplied between 1-, 1- pplied between FB-FS, FB-FS, WFB-WFS D = DB = 15, Total of 1-, 1- = 5 FB-FS, FB-FS, WFB-WFS S = 0, FO = 10kΩ 5 pull-up S = 1, FO = 10kΩ 5 pull-up S = 1, IFO = 15m Relates to corresponding input signal for blocking arm shoot-through. 20 T 100 Tj = 25, D = 15 (ote 3) Trip level Reset level Tj 125 Trip level Reset level = 22nF (ote 4) pplied between :,, W-,,, W- Min. Typ. Max ote 3 : Short circuit protection is functioning only at the low-arms. lease select the value of the external shunt resistor such that the S triplevel is less than 34. 4:Fault signal is output when the low-arms short circuit or control supply under-voltage protective functions operate. The fault output pulsewidth tfo depends on the capacitance value of according to the following approximate equation : = tfo [F] nit m ms

5 MEHIL HRTERISTIS D RTGS arameter Mounting torque Terminal pulling strength Bending strength Weight Heat-sink flatness Mounting screw : M4 Weight 19.6 Weight deg bend (ote 5) EIJ-ED-4701 EIJ-ED-4701 Min Typ Max nit m s times g µm ote 5: Measurement point of heat-sink flatness (ote 5) Measurement point 3mm Heat sink lace to contact a heat sink Heat sink REMEDED OERTIO ODITIOS Symbol D DB D, DB tdead fwm (O) (OFF) arameter Supply voltage ontrol supply variation rm shoot-through blocking time WM input frequency Input O threshold voltage Input OFF threshold voltage pplied between - pplied between 1-, 1- pplied between FB-FS, FB-FS, WFB-WFS Relates to corresponding input signal for blocking arm shoot-through T 100, Tj 125 pplied between,, W- pplied between,, W- Min. Typ. Max ~ ~ nit / khz

6 Fig. 4 THE TERL IRIT FB FS 1 HI 1 B IGBT1 Di1 S FB FS 1 HI 2 B IGBT2 Di2 S WFB WFS 1 HI 3 B IGBT3 Di3 W S W LI IGBT4 Di4 OT 1 IGBT5 Di5 OT WOT IGBT6 Di6 W W O GD

7 Fig. 5 TIMG HRTS OF THE ROTETIE FTIOS [] Short-ircuit rotection (-side only) (r the external shunt resistor and R connection.) a1. ormal operation : IGBT O and carrying current. a2. Short circuit current detection (S trigger). a3. Hard IGBT gate interrupt. a4. IGBT turns OFF. a5. FO timer operation starts : The pulse width of the FO signal is set by the external capacitor. a6. Input H : IGBT OFF state. a7. Input L : IGBT O state. a8. IGBT OFF state. -side control input a6 a7 rotection circuit state SET RESET Internal IGBT gate a2 a3 Output current Ic() a1 S a4 a8 Sense voltage of the shunt resistor S reference voltage R circuit time constant DELY Error output a5 [B] nder-oltage rotection (-side, D) a1. ormal operation : IGBT O and carrying current. a2. nder voltage trip (Dt). a3. IGBT OFF in spite of control input condition. a4. FO timer operation starts. a5. nder voltage reset (Dr). a6. ormal operation : IGBT O and carrying current. ontrol input rotection circuit state SET RESET D Dr Dt a2 a5 a1 a3 a6 Output current Ic() Error output a4

8 [] nder-oltage rotection (-side, DB) a1. rises : fter the voltage level reachs DBr, the circuits start to operate when the next input is applied. a2. ormal operation : IGBT O and carrying current. a3. nder voltage trip (DBt). a4. IGBT OFF in spite of control input condition, but there is no FO signal output. a5. nder-voltage reset (DBr). a6. ormal operation : IGBT O and carrying current. ontrol input rotection circuit state RESET SET RESET DBr DB a1 DBt a3 a5 a2 a4 a6 Output current Ic() Error output High-level (no fault output) Fig. 6 REMEDED I/O TERFE IRIT 5 line 5.1kΩ 4.7kΩ,,W,,,W 1nF 1nF, (Logic) ote : R coupling at each input (parts shown dotted) may change depending on the WM control scheme used in the application and on the wiring impedances of the application s printed circuit board.

9 Fig. 7 TYIL LITIO IRIT EXMLE 1: Tight tolerance temp-compensated electrolytic type; 2,3: 0.22~2 µ F R-category ceramic capacitor for noise filtering 5 line 2 1 FB FS 1 3 B 2 S FB 1 FS WFB WFS 1 W B S B M I T S OT W line OT 15 line W W GD WOT O The long wiring of GD might generate noise on input signals and cause IGBT to be malfunctioned. 4() 5 B R1 If this wiring is too long, the S level fluctuation might be larger and cause S malfunction. If this wiring is too long, short circuit might be caused. Shunt resistor 1 ote 1 : To prevent the input signals oscillation, an R coupling at each input is recommended, and the wiring of each input should be as short as possible. (Less than 2cm) 2:By virtue of integrating an application specific type HI inside the module, direct coupling to terminals without any opto-coupler or transformer isolation is possible. 3:FO output is open collector type. This signal line should be pulled up to the positive side of the 5 power supply with approximately 5.1kΩ resistance. 4:FO output pulse width should be decided by connecting an external capacitor between and terminals (). (Example : = 22 nf tfo = 1.8 ms (typ.)) 5:Each input signal line should be pulled up to the 5 power supply with approximately 4.7kΩ resistance (other R coupling circuits at each input may be needed depending on the WM control scheme used and on the wiring impedances of the system s printed circuit board). pproximately a 0.22~2µF by-pass capacitor should be used across each power supply connection terminals. 6:To prevent errors of the protection function, the wiring of, B, should be as short as possible. 7:In the recommended protection circuit, please select the R15 time constant in the range 1.5~2. 8:Each capacitor should be put as nearby the pins of the as possible. 9:To prevent surge destruction, the wiring between the smoothing capacitor and the &1 pins should be as short as possible. pproximately a 0.1~0.22µF snubber capacitor between the &1 pins is recommended.