AC/DC Power Supply Reference Design. Advanced SMPS Applications using the dspic DSC SMPS Family

Transcription

1 AC/DC Power Supply Reference Design Advanced SMPS Applications using the dspic DSC SMPS Family

2 dspic30f SMPS Family Excellent for Digital Power Conversion Internal hi-res PWM Internal high speed ADC Internal fast comparators Internal precision oscillator Internal Communication Peripherals Single Supply Voltage Small packages Internal Flash and RAM Extended temperature Power Factor Correction can be implemented

3 Design Overview Total Output Power Rating of 350 W Multiple DC Outputs: 3.3V, 69A (max) 5V, 23A (max) 12V, 29A (max) Universal Operating Voltage 85V 265V AC, Hz Digital PFC Implementation PF > 0.98 Automatic Fault Handling Flexible Start-up Capability Remote Power Management Capability Full Digital Control

4 Block Diagram Rectified Sinusoidal Voltage 400V dc Isolation Barrier 12V dc Bus Phase Shift ZVT Converter 12V Output 12V dc 29A EMI Filter and Bridge Rectifier PFC Boost Converter ZVT Full-Bridge Converter Synchronous Rectifier Multi-Phase Buck Converter 3.3V dc 69A Vac 45-65Hz dspic 30F2023 Opto- Coupler Opto- Coupler dspic 30F2023 Single-Phase Buck Converter 5V dc 23A

5 PFC Output (Drain of Q1 & Q4) Multi-phase sync buck +12V GND +3.3V Primary Ground GND Line Earth Neutral +5V GND Input connector Single phase sync buck Output connectors

6 Architectural Considerations Multi-stage architecture Boost PFC Topology (120 khz PWM/40 khz control loop) Soft Switching (ZVT) (240 khz PWM/40 khz control loop) 12-Volt Intermediate Bus Multi-phase Synchronous Buck Outputs (500 khz PWM/125 khz control loop) Single phase Synchronous Buck Outputs (500 khz PWM/125 khz control loop)

7 Power Factor Correction (f sw 120kHz) Additional Information Available in Apps note AN1106

8 Power Factor Correction With no Power Factor Correction, the input current is highly distorted Diode ON Diode ON Diode ON Diode ON Diode OFF Diode OFF Diode OFF Induces Noise in the Power Grid Input Voltage Higher current rating device is required I in V in Boost Circuit Output Voltage AC Vhb AC Input Current Load Load Current is not sinusoidal

9 PFC Boost Converter PFC Inductor Boost Diode Primary (Live) Side L1 D1 +HV_BUS R1 R4 Vac + ~ ~ - R2 V AC Sense C2 Q1 PWM4L C3 R5 V HV Sense C1 R3 C4 R6 R sense I PFC sense PFC MOSFET -HV_BUS

10 Feedback and Control Signals PFC Boost Converter L I ac I S D I D V dc V ac S C Load k 2 PWM k 3 Driver k 1 V ac I ac Control Signal V dc ADC channel ADC channel PWM pulses ADC channel dspic Digital Signal Controller

11 voltage profile to improve Power Factor and minimize current harmonics Control Strategy Average Inductor Current is controlled I L I L L PFC Boost Converter D t ON + I S v 1 I L I S S I D C + - I D - Average Current Mode Control The average current through the inductor is made to follow the input

12 PFC Control Scheme Voltage Reference Rectified AC Mains Voltage Calculated Current Reference + - Voltage Error Compensator X + - Current Error Compensator PWM PFC Choke Vout V AC MEAN 1 V 2 Current Feedback S&H PFC Current sense Voltage Feedback ADC S&H V OUT Sense

13 Digital Implementation ADC I AC ANx V AC ANx V DC ANx 40 Ksps VDCref Voltage Error Compensator 1.3 KHz V DC + - V ERR V PI V COMP * * VAC * I ACref 6.65 KHz + Current Error Compensator 40 KHz - I AC I ERR PWM PDC 120 KHZ PWM pulses 1/V avg 2 V AC V avg Voltage Feed Forward Compensator

14 PFC Software Overview ADC Conversions are initiated by the PWM Trigger Feature The Current Control Loop is Executed in Each ADC Interrupt Routine The Voltage Loop executed at every 30 th ADC Interrupt PFC Current reference (I ACref ) loop is executed at every 6 th ADC Interrupt Faults are handled by the PWM Module using the on-chip Analog Comparators

15 Phase Shift Full-Bridge ZVT Converter (f sw 240kHz)

16 Zero Voltage Switching At transition period from one state to another state of the switch, the voltage is zero, hence no losses V ds V ds (t) I d (t) G D I d S ZVS t PWM t

17 Switching Methodology Zero Voltage Switching : Eliminates V*I losses during transitions Eliminates MOSFET output capacitor (C oss ) loss during switch Turn-ON Reduces Noise in the system hence better EMI performance Preferred in high voltage high power system

18 Full-Bridge Phase Shift ZVT Converter +Vin C oss PWM1H PWM2H T1 L1 Vout I pri L Lkg V pri PWM1L PWM2L Full-bridge Phase Shift ZVT converter Complementary, fixed duty cycle PWM gate pulses Phase shift in gate pulse of two legs control the power flow Parasitic of MOSFET (C oss ) and Transformer (L Lkg ) used to achieved ZVT Zero Voltage Switching, hence Turn ON losses in the MOSFET eliminated A popular converter for very high power application

19 ZVT Control Scheme Voltage Reference Calculated Current Reference Rectifier Vout + - Voltage Error Compensator + - Current Error Compensator PWM Phase ZVT Xformer Current Feedback S&H ZVT Current sense Voltage Feedback ADC S&H Optocoupler S&H V OUT Sense

20 Resources Required for Digital ZVT Converter V HV_BUS Isolation Barrier V OUT I ZVT FET Driver FET Driver FET k 2 k 1 Driver PWM1H PWM1L PWM2H PWM2L ADC Channel ADC Channel PWM3H ADC Channel PWM3L dspic30f2023 UART RX UART TX dspic30f2023

21 ZVT Software Overview ADC Conversions are initiated by the PWM Trigger Feature The Current Control Loop is Executed in Each ADC Interrupt Routine Additional Check for Transformer Primary Current Balance to prevent Flux Walking The Voltage Loop is Executed from a UART Receive Interrupt Faults are handled by the PWM Module using the on-chip Analog Comparators

22 Intermediate Bus 12-Volt Bus Voltage regulation of ~1% Sufficient for our design goals (final outputs will be tightly regulated) Could be improved to 0.5% to 0.1% range using 2 nd generation dspic33f SMPS devices (40 MIPS vs. 30 MIPS) and running faster PID loops Dynamic Response Sufficient for our design goals Could be improved by feeding the secondary-side voltage sense to an A/D input on the primary-side dspic30f2023 though a linear opto-coupler (eliminating the UART delay) AC/DC demo design already configured for this option

23 Additional Guidelines for Primary side dspic DSC Software

24 PWM1H PWM2H Full-Bridge Phase Shift ZVT Converter T1 Vout PWM1H Phase Shift +Vin I pri L1 V T PWM3H PWM3L PWM1L PWM2H PWM2L Duty Cycle PWM1L PWM2L ZVT Current #1 Trigger Instant Trigger at end of PWM1H Pulse I pri ZVT Current #2 Trigger Instant Trigger on at start of PWM1H

25 Sequence of Current Loop ZVT Current 1 Trigger: Once every 6 ZVT cycles ZVT Current 2 Trigger: Once every 6 ZVT cycles Triggers ZVT Current 1 Trigger: Once every 6 ZVT cycles PWM1H PWM1L PWM2H PWM2L PWM4L Execute ZVT Current Loop #1 PFC Current Trigger: Once every 3 PFC cycles Execute ZVT Current Loop #1 Sample and Convert AN2, AN3 Sample and Convert AN0, AN1 Idle Loop Execute ZVT Current Loop #2 Idle Loop Sample and Convert AN4, AN5 Execute PFC Current Loop Idle Loop Sample and Convert AN0, AN1

26 Multi-Phase Buck Converter (f sw 500kHz)

27 Synchronous Buck Converter +Vin Q1 I LOAD + Iripple Vout Cin PWMH PWML Q2 L1 Cout Iripple ILOAD Period PWMH PWML Iripple

28 Multi-Phase Buck Converter 12V Input Q1 Q2 3.3V Output Drive Signals are Phase Shifted by 120 Q1 Q3 Q4 Q3 Q5 Q6 Q5 GND

29 Why the Multi-phase Buck Converter? Each phase is rated for less power Semiconductor services have lower current rating Smaller MOSFET s usually mean better switching speed Higher output ripple frequency decreases size of output filter Ripple magnitude is reduced

30 5V Buck Converter Control Scheme Voltage Reference 5V Current sense 5V OUT + - Voltage Error Compensator Calculated Current Reference V ref - + Analog Comparator PWM Current Limit Shutdown 5Vout Inductor Voltage Feedback ADC S&H V OUT Sense

31 3.3V Buck Converter Control Scheme Voltage Reference 3.3V OUT + - Voltage Error Compensator PWM Current Limit Shutdown Phase 3 Inductor Voltage Feedback ADC S&H V OUT Sense

32 Resources Required for Digital Buck Converters 12V Input I 3.3V_1 3.3V Output I 5V 5V Output I 3.3V_2 FET Driver FET Driver k 7 FET Driver k 1 k 2 I 3.3V_3 k 6 ADC Channel UART TX PWM PWM Analog Comp. ADC Channel PWM PWM dspic30f2023 PWM PWM PWM PWM Analog Comp. Analog Comp. Analog Comp. ADC Channel FET Driver k 3 k 4 k 5

33 Multi-Phase Buck Converter Software Overview ADC Conversions are initiated by the PWM Trigger Feature Peak Current Control is implemented using the Analog Comparators Additional Check Desired for Current Imbalance between the three phases The Voltage and Current Loops are executed at the same speed The UART Transmission for 12V digital feedback is executed from a Timer Interrupt

34 Sequence of Current Loop Triggers 5V Buck Voltage Trigger 3.3V Buck Voltage Trigger 5V Buck Voltage Trigger 3.3V Buck Voltage Trigger 5V Buck Voltage Trigger 3.3V Buck Voltage Trigger PWM1H PWM1L PWM2H PWM2L PWM3H PWM3L PWM4H PWM4L Execute 5V Buck Control Loop Execute 5V Buck Control Loop Execute 5V Buck Control Loop Sample and Convert AN1 Idle Loop Execute 3.3V Buck Control Loop Sample and Convert AN1 Idle Loop Execute 3.3V Buck Control Loop Sample and Convert AN1 Idle Loop Execute 3.3V Buck Control Loop Sample and Convert AN3 Idle Loop Sample and Convert AN3 Idle Loop Sample and Convert AN3

35 Remote Monitoring Capability Vac 45-65Hz EMI Filter and Bridge Rectifier Rectified Sinusoidal Voltage PFC Boost Converter 400V dc Synchronous ZVT Converter ZVT Full-Bridge Converter Isolation Barrier Synchronous Rectifier 12Vdc Multi-Phase Buck Converter 3.3V dc 69A dspic 30F2023 Opto- Coupler dspic 30F2023 Single-Phase Buck Converter 5V dc 23A +V GND SDA SCK PICkit Serial Analyzer Power monitoring can be implemented using a Serial I 2 C interface provided on the Secondary (Isolated) side

36 Benefits of Digital Control Reduce Component Count Increase design flexibility Increase control flexibility Protect Intellectual Property Implement non-linear and adaptive control Control multiple stages Error logging capability Flexible fault handling

37 Thank You!