HW1: (Page 71: 2, 3) CS100: Itroductio to Computer Sciece 2. For each of the followig circuits, idetify the iput combiatios that produce a output of 1. Lecture 6: Data Maipulatio -- computer architecture, machie laguage & program executio 3. I each circuit below, the rectagles represet the same type of gate. Based o the iput ad output iformatio give, idetify whether the gate ivolved is a AND, OR, or XOR. HW1: (Page 72: 5) Address Cotets After step1 After step2 After step3 00 AB 02 02 02 01 53 53 53 53 02 D6 D6 01 01 03 02 02 02 53 Step 1: Move the cotets of the cell whose address is 03 to the cell at address 00. Step 2: Move the value 01 ito the cell at address 02. Step 3: Move the value stored at address 01 ito the cell at address 03. Review: Data compressio q Lossless Ru-legth ecodig Frequecy-depedet ecodig Dictioary ecodig q Lossy GIF JPEG TIFF MPEG MP3 Commuicatio errors q Parity bits (eve versus odd) q Checkbytes q Error correctig codes Chapter 2: Data Maipulatio 2.1 Computer Architecture 2.2 Machie Laguage 2.3 Program Executio Figure 2.1 CPU ad mai memory coected via a bus 1
Computer Architecture Stored Program Cocept Cetral Processig Uit (CPU) or processor q Arithmetic/Logic uit versus Cotrol uit Perform operatios o data Coordiate the machie s activities q Registers : for temporary storage of ifo. Geeral purpose Special purpose Bus q Wires coect CPU to mai memory Motherboard q Mai circuit board A program ca be ecoded as bit patters ad stored i mai memory. From there, the CPU ca the extract the istructios ad execute them. I tur, the program to be executed ca be altered easily. Termiology Machie Laguage Philosophies Machie istructio: A istructio (or commad) ecoded as a bit patter recogizable by the CPU Machie laguage: The set of all istructios recogized by a machie Reduced Istructio Set Computig (RISC) q Few, simple, efficiet, ad fast istructios q Example: PowerPC from Apple/IBM/Motorola Complex Istructio Set Computig (CISC) q May, coveiet, ad powerful istructios Easy to program A simple istructio i a CISC desig may require a multi-istructio sequece i a RISC desig. q Example: Petium from Itel Machie Istructio Types Data Trasfer: copy data from oe locatio to aother q LOAD: fill geeral-purpose register with the cotets of a memory cell q STORE: trasfer the cotets of a register to a memory cell Figure 2.2 Addig values stored i memory Arithmetic/Logic: use existig bit patters to compute a ew bit patters q Basic arithmetic operatios: ADDITION, DIVISION q Boolea operatios: AND, OR, XOR q Other operatios: SHIFT, ROTATE Cotrol: direct the executio of the program q Direct the executio of the program q JUMP: 2
Figure 2.3 Dividig values stored i memory Figure 2.4 The architecture of the machie described i Appedix C (16 geeralpurpose registers ad 256 memory cells) Parts of a Machie Istructio Op-code: Specifies which operatio to execute Operad: Gives more detailed iformatio about the operatio q Iterpretatio of operad varies depedig o opcode Figure 2.5 The compositio of a istructio for the machie i Appedix C (2 bytes for each istructio) Figure 2.6 Decodig the istructio 35A7 Figure 2.7 A ecoded versio of the istructios i Figure 2.2 3
Questios: Questios: 1. The followig are istructios writte i the machie laguage described i Appedix C. Rewrite them i Eglish q 368A q BADE 2. Traslate some istructios i Eglish ito machie laguage of Appedix C. q Load register umber 3 with the hexadecimal value 56 q Move the cotets of register F to register 4. 1. The followig are istructios writte i the machie laguage described i Appedix C. Rewrite them i Eglish q 368A: STORE the cotets of register 6 i memory cell umber 8A q BADE: JUMP to locatio DE if the cotets of register A equals to that of the register 0. 2. Traslate some istructios i Eglish ito machie laguage of Appedix C. q LOAD register umber 3 with the hexadecimal value 56: 2356 q MOVE the cotets of register F to register 4: 40F4 Program Executio Figure 2.8 The machie cycle Cotrolled by two special-purpose registers q Program couter: address of ext istructio q Istructio register: curret istructio Machie Cycle q q q Fetch Decode Execute Figure 2.9 Decodig the istructio B258 Figure 2.10 The program from Figure 2.7 stored i mai memory ready for executio 4
Figure 2.11 Performig the fetch step of the machie cycle Figure 2.11 Performig the fetch step of the machie cycle (cot d) Questios: Questios: 1. Suppose the memory cells from address 00 to 05 i the machie described i Appedix C cotai the (hexadecimal) bit patters give i the followig table: Address Cotets 00 14 Istructios: Istructios: 01 02 1402 1402(LOAD) 02 34 03 17 3417 3417(STORE) 04 C0 05 00 C000 C000(HALT) If we start the machie with is program couter cotaiig 00, what bit patter is i the memory cell whose address is hexadecimal 17 whe the machie halts. 1. Suppose the memory cells from address 00 to 05 i the machie described i Appedix C cotai the (hexadecimal) bit patters give i the followig table: Address Cotets 00 14 Istructios: Istructios: 01 02 1402 1402(LOAD) 02 34 03 17 3417 3417(STORE) 04 C0 05 00 C000 C000(HALT) If we start the machie with is program couter cotaiig 00, what bit patter is i the memory cell whose address is hexadecimal 17 whe the machie halts. (34) Questios: Questios: 2. Suppose the memory cells from address B0 to i the machie C cotai the (hexadecimal) bit patters give i the described i Appedix followig table: B0 B2 B4 B6 13 A3 33 C0 Address B1 B3 B5 B7 Cotets 02 00 0F Istructios: 13 A302 33 C000 Istructios: 13(LOAD) A302(ROTATE) 33(STORE) C000(HALT) a. If the program couter starts at B0, what bit patter is i register umber 3 after the first istructio has bee executed? b. What bit patter is i memory cell whe the halt istructio is executed. 2. Suppose the memory cells from address B0 to i the machie C cotai the (hexadecimal) bit patters give i the described i Appedix followig table: B0 B2 B4 B6 13 A3 33 C0 Address B1 B3 B5 B7 Cotets 02 00 0F Istructios: 13 A302 33 C000 Istructios: 13(LOAD) A302(ROTATE) 33(STORE) C000(HALT) a. If the program couter starts at B0, what bit patter is i register umber 3 after the first istructio has bee executed? (0F) b. What bit patter is i memory cell whe the halt istructio is executed. (C3) 5
Next Lecture: Istructios, commuicatig & other Architectures Readig assigmets: Chapter 2.4, 2.5,2.6 The 3 rd homework assigmet will be aouced 6