Lecture 16: Address decoding

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1 Lecture 16: Address decodi Itroductio to address decodi Full address decodi Partial address decodi Implemeti address decoders Examples Microprocessor-based System Desi Ricardo Gutierrez-Osua Wriht State Uiversity 1

2 Itroductio to address decodi Althouh the memory space i the is said to be flat, it does ot mea that the physical implemetatio of memory is homoeeous Differet portios of memory are used for differet purposes: RAM, ROM, I/O devices Eve if all the memory was of oe type, we still have to implemet it usi multiple ICs This meas that for a ive valid address, oe ad oly oe memory-mapped compoet must be accessed Address decodi is the process of eerati chip select () sials from the address bus for each device i the system The address bus lies are split ito two sectios the N most siificat bits are used to eerate the sials for the differet devices the M least siificat sials are passed to the devices as addresses to the differet memory cells or iteral reisters Address decodi stratey Memory map M SB L SB Address lies. 2 N blocks N bits to decoder M bits to memory 2 M address rae Microprocessor-based System Desi Ricardo Gutierrez-Osua Wriht State Uiversity 2

must be accessed Address decodi is the process of eerati chip select () sials from the address bus for each device i the system The address bus lies are split ito two sectios the N most siificat bits

3 A very simple example Let s assume a very simple microprocessor with 10 address lies (1KB memory) Let s assume we wish to implemet all its memory space ad we use 128x8 memory chips SOLUTION We will eed 8 memory chips (8x128=1024) We will eed 3 address lies to select each oe of the 8 chips Each chip will eed 7 address lies to address its iteral memory cells 7 MEM 0 MEM 4 Memory map to-8 decoder MEM 1 MEM 5 MEM 0 MEM 1 MEM 2 MEM 3 CPU MEM 2 MEM 6 MEM 4 MEM 5 MEM 3 MEM 7 MEM 6 MEM 7 Microprocessor-based System Desi Ricardo Gutierrez-Osua Wriht State Uiversity 3

8 chips Each chip will eed 7 address lies to address its iteral memory cells 7 MEM 0 MEM 4 Memory map 10 3 3-to-8 decoder MEM 1 MEM 5 MEM 0

4 Address decodi methods The previous example specified that all addressable memory space was to be implemeted but There are some situatios where this requiremet is ot ecessary or affordable If oly a portio of the addressable space is oi to be implemeted there are two basic address decodi strateies Full address decodi All the address lies are used to specify a memory locatio Each physical memory locatio is idetified by a uique address Partial address decodi Sice ot all the address space is implemeted, oly a subset of the address lies are eeded to poit to the physical memory locatios Each physical memory locatio is idetified by several possible addresses (usi all combiatios of the address lies that were ot used) Microprocessor-based System Desi Ricardo Gutierrez-Osua Wriht State Uiversity 4

locatio is idetified by a uique address Partial address decodi Sice ot all the address space is implemeted, oly a subset of the address lies are eeded to poit to the physical memory locatios Each

5 Full address decodi Let s assume the same microprocessor with 10 address lies (1KB memory) However, this time we wish to implemet oly 512 bytes of memory We still must use 128-byte memory chips Physical memory must be placed o the upper half of the memory map SOLUTION Used for Address Decodi Used to referece memory cells o each memory IC Device A9 A6 A5 A4 A3 A2 A1 A0 MEM X X X X X X X MEM X X X X X X X MEM X X X X X X X MEM X X X X X X X Memory map A9 CS MEM0 CS MEM1 CS MEM2 CS MEM3 MEM 0 MEM 1 MEM 2 MEM 3 Not used Not used Not used Not used Microprocessor-based System Desi Ricardo Gutierrez-Osua Wriht State Uiversity 5

each memory IC Device A9 A6 A5 A4 A3 A2 A1 A0 MEM 0 0 0 0 X X X X X X X MEM 1 0 0 1 X X X X X X X MEM 2 0 1 0 X X X X X X X MEM 3 0 1 1 X X X X X X X Memory map A9

6 Partial address decodi Let s assume the same microprocessor with 10 address lies (1KB memory) However, this time we wish to implemet oly 512 bytes of memory We still must use 128-byte memory chips Physical memory must be placed o the upper half of the memory map SOLUTION Not used Used for Address Decodi Used to referece memory cells o each memory IC Device A9 A6 A5 A4 A3 A2 A1 A0 MEM 0 X 0 0 X X X X X X X MEM 1 X 0 1 X X X X X X X MEM 2 X 1 0 X X X X X X X MEM 3 X 1 1 X X X X X X X CS MEM0 CS MEM1 CS MEM2 CS MEM3 Memory map MEM 0 MEM 1 MEM 2 MEM 3 MEM 1 MEM 2 MEM 3 MEM 4 Microprocessor-based System Desi Ricardo Gutierrez-Osua Wriht State Uiversity 6

memory cells o each memory IC Device A9 A6 A5 A4 A3 A2 A1 A0 MEM 0 X 0 0 X X X X X X X MEM 1 X 0 1 X X X X X X X MEM 2 X 1 0 X X X X X X X MEM 3 X 1 1 X X X X X X X

7 Implemeti address decoders Discrete loic Hih speed (propaatio sials) Hih chip-cout Lacks flexibility Data decoders More appropriate tha radom loic The selectio of devices is determied by the physical wiri All the memory blocks must have the same size Prorammable Read Oly Memory (PROM) Versatile, sice the selectio of devices is determied by the prorammi Memory blocks ca be of differet sizes Lookup tables ca become very lare for more tha 8 address lies Other methods (beyod the scope of the lecture) are Field Prorammable Gate Arrays (FPGA) ad Prorammable Address Decoders Microprocessor-based System Desi Ricardo Gutierrez-Osua Wriht State Uiversity 7

is determied by the prorammi Memory blocks ca be of differet sizes Lookup tables ca become very lare for more tha 8 address lies Other methods (beyod the scope of

8 Example 1 A circuit cotaii 64K words of RAM is to be iterfaced to a based system, so that the first address of RAM (the base address) is at $ Solutio What is the etire rae of RAM addresses? Desi a FULL address decoder usi two 64K 8 RAM ICs The address rae for the RAM is from $ to $ (128K=$20000)=$4A0000-1=$49FFFF The two ICs must be differetiated throuh UDS*/LDS* (sice the DOES NOT have A 0 ) 4 8 or 9 0 to F 0 to F 0 to F 0 to F A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A6 A5 A4 A3 A2 A1 A X X X X X X X X X X X X X X X X X These 7 address lies set the base address of the memory These 16 address lies will select oe of the 2 16 (64K) locatios iside each RAM IC This address lie is implemeted with UDS*/LDS* A 23 A 22 A 21 A 20 SEL UDS SEL D8-D15 A 19 A 18 A 17 AS* LDS SEL D0-D7 Microprocessor-based System Desi Ricardo Gutierrez-Osua Wriht State Uiversity 8

Desi a FULL address decoder usi two 64K 8 RAM ICs The address rae for the RAM is from $480000 to $480000+(128K=$20000)=$4A0000-1=$49FFFF The two ICs must be differetiated throuh UDS*/LDS* (sice the

9 Example 2 A based system is to be built with these memory requiremets a 16K word EPROM with a starti address of $ a 16K word RAM with a starti address of $ Desi a FULL address decoder for this applicatio usi 16K 8 chips for both EPROM ad RAM $ (16KWord=32KB=$8000)-1=$60 7FFF $ (16KWord=32KB=$8000)-1=$70 7FFF ROM to 7 0 to F 0 to F 0 to F A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A6 A5 A4 A3 A2 A1 A X X X X X X X X X X X X X X X RAM A to 7 0 to F 0 to F 0 to F A21 A20 A19 A18 A17 A16 A15 A14 A13 A X X X X X X X X X X X X X X X A 23 A 22 A 21 A 19 A 18 A 17 A 16 A 15 A 20 AS* ROMSEL RAMSEL A11 A10 A9 UDS LDS UDS LDS A6 A5 A4 A3 A2 A1 ROMSEL D8-D15 ROMSEL D0-D7 RAMSEL D8-D15 RAMSEL D0-D7 A0 Microprocessor-based System Desi Ricardo Gutierrez-Osua Wriht State Uiversity 9

A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A6 A5 A4 A3 A2 A1 A0 0 1 1 0 0 0 0 0 0 X X X X X X X X X X X X X X X RAM A22 7 0 0 to 7 0 to F 0 to F 0 to F A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 0 1 1 1

10 Example 3 Desi a PARTIAL address decoder for a based system with oly 8K words of EPROM space, ad a base address at $4000, usi 8Kx8 memory chips to 7 0 to F 0 to F 0 to F A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A6 A5 A4 A3 A2 A1 A X X X X X X X X X X X X X X Microprocessor-based System Desi Ricardo Gutierrez-Osua Wriht State Uiversity 10

A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 0 1 X X X X

11 Example 4 Desi a partial address decoder for a based system that cotais 2MB of EPROM at a starti address $ usi 512Kx8 chips 2MB of RAM at a starti address $ usi 256Kx8 chips 64KB I/O space starti at $FF0000 SOLUTION For the EPROM we will eed 4 512Kx8 chips, oraized as 2 pairs of 512x8 chips (i order to use UDS*/LDS*). We will call these pairs ROM1 ad ROM2 For the RAM we will eed 8 256Kx8 chips, oraized as 4 pairs of 256Kx8: RAM1 to RAM4 Microprocessor-based System Desi Ricardo Gutierrez-Osua Wriht State Uiversity 11

512Kx8 chips, oraized as 2 pairs of 512x8 chips (i order to use UDS*/LDS*).

EXERCISES OF FUNDAMENTALS OF COMPUTER TECHNOLOGY UNIT 5. MEMORY SYSTEM

EXERCISES OF FUNDAMENTALS OF COMPUTER TECHNOLOGY UNIT 5. MEMORY SYSTEM Unit 5. Memory System 2 / 6 Most of the exercises in this units deal with installing memory chips in a computer to increase its capacity,