DKT 122/3 DIGITAL SYSTEM 1

Similar documents
COMBINATIONAL CIRCUITS

Combinational circuits

Sistemas Digitais I LESI - 2º ano

Two-level logic using NAND gates

1. True or False? A voltage level in the range 0 to 2 volts is interpreted as a binary 1.

Understanding Logic Design

Copyright Peter R. Rony All rights reserved.

5 Combinatorial Components. 5.0 Full adder. Full subtractor

Figure 8-1 Four Possible Results of Adding Two Bits

Combinational Logic Design

earlier in the semester: The Full adder above adds two bits and the output is at the end. So if we do this eight times, we would have an 8-bit adder.

Gates, Circuits, and Boolean Algebra

CSE140: Components and Design Techniques for Digital Systems

Lecture 12: More on Registers, Multiplexers, Decoders, Comparators and Wot- Nots

2011, The McGraw-Hill Companies, Inc. Chapter 3

Combinational-Circuit Building Blocks

DM Segment Decoder/Driver/Latch with Constant Current Source Outputs

LOGICOS SERIE Precios sujetos a variación. Ref. Part # Descripción Precio Foto Ref. Quad 2-Input NOR Buffered B Series Gate / PDIP-14

Multiplexing. Multiplexing is the set of techniques that allows the simultaneous transmission of multiple signals across a single physical medium.

Take-Home Exercise. z y x. Erik Jonsson School of Engineering and Computer Science. The University of Texas at Dallas

Design Example: Counters. Design Example: Counters. 3-Bit Binary Counter. 3-Bit Binary Counter. Other useful counters:

SECTION C [short essay] [Not to exceed 120 words, Answer any SIX questions. Each question carries FOUR marks] 6 x 4=24 marks

United States Naval Academy Electrical and Computer Engineering Department. EC262 Exam 1

(1) /30 (2) /30 (3) /40 TOTAL /100

Memory Elements. Combinational logic cannot remember

Hexadecimal and Numeric Indicators. Technical Data

EE 261 Introduction to Logic Circuits. Module #2 Number Systems

Lab 1: Study of Gates & Flip-flops

ASYNCHRONOUS COUNTERS

Lab 17: Building a 4-Digit 7-Segment LED Decoder

Digital Design. Assoc. Prof. Dr. Berna Örs Yalçın

ELEC EXPERIMENT 1 Basic Digital Logic Circuits

Read-only memory Implementing logic with ROM Programmable logic devices Implementing logic with PLDs Static hazards

Counters and Decoders

Multiplexers and demultiplexers

Gates, Plexers, Decoders, Registers, Addition and Comparison

Today s topics. Digital Computers. More on binary. Binary Digits (Bits)

Digital Logic Design. Basics Combinational Circuits Sequential Circuits. Pu-Jen Cheng

Number of bits needed to address hosts 8

Multiplexers and Demultiplexers

List of Experiment. 8. To study and verify the BCD to Seven Segments DECODER.(IC-7447).

The string of digits in the binary number system represents the quantity

Guru Ghasidas Vishwavidyalaya, Bilaspur (C.G.) Institute of Technology. Electronics & Communication Engineering. B.

The use of binary codes to represent characters

FORDHAM UNIVERSITY CISC Dept. of Computer and Info. Science Spring, Lab 2. The Full-Adder

Digital Multiplexer and Demultiplexer. Features. General Description. Input/Output Connections. When to Use a Multiplexer. Multiplexer 1.

Chapter 1: Digital Systems and Binary Numbers

Operating Manual Ver.1.1

Standart TTL, Serie Art.Gruppe

Seven-Segment LED Displays

Digital circuits make up all computers and computer systems. The operation of digital circuits is based on

Decimal Number (base 10) Binary Number (base 2)

Digital Fundamentals. Lab 8 Asynchronous Counter Applications

Android based Alcohol detection system using Bluetooth technology

HCF4028B BCD TO DECIMAL DECODER

ENGI 241 Experiment 5 Basic Logic Gates

plc numbers Encoded values; BCD and ASCII Error detection; parity, gray code and checksums

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

Experiment # 9. Clock generator circuits & Counters. Eng. Waleed Y. Mousa

Chapter 4: Computer Codes

Binary Adders: Half Adders and Full Adders


RAM & ROM Based Digital Design. ECE 152A Winter 2012

EE360: Digital Design I Course Syllabus

DEPARTMENT OF INFORMATION TECHNLOGY

Interfacing To Alphanumeric Displays

DATA SHEETS DE COMPONENTES DA FAMÍLIA LÓGICA TTL GATES AND INVERTERS POSITIVES NAND GATES AND INVERTERS DESCRIÇÃO

HOMEWORK # 2 SOLUTIO

Lecture 4: Binary. CS442: Great Insights in Computer Science Michael L. Littman, Spring I-Before-E, Continued

Logic gates. Chapter. 9.1 Logic gates. MIL symbols. Learning Summary. In this chapter you will learn about: Logic gates

Programming A PLC. Standard Instructions

BINARY CODED DECIMAL: B.C.D.

Content Map For Career & Technology

Section 1.4 Place Value Systems of Numeration in Other Bases

TCOM 370 NOTES 99-6 VOICE DIGITIZATION AND VOICE/DATA INTEGRATION

Oct: 50 8 = 6 (r = 2) 6 8 = 0 (r = 6) Writing the remainders in reverse order we get: (50) 10 = (62) 8

Layout of Multiple Cells

Upon completion of unit 1.1, students will be able to

A Lesson on Digital Clocks, One Shots and Counters

Digital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill

Chapter 4 Register Transfer and Microoperations. Section 4.1 Register Transfer Language

Gray Code Generator and Decoder by Carsten Kristiansen Napier University. November 2004

Lecture 8: Synchronous Digital Systems

DM74LS47 BCD to 7-Segment Decoder/Driver with Open-Collector Outputs

University of St. Thomas ENGR Digital Design 4 Credit Course Monday, Wednesday, Friday from 1:35 p.m. to 2:40 p.m. Lecture: Room OWS LL54

CDA 3200 Digital Systems. Instructor: Dr. Janusz Zalewski Developed by: Dr. Dahai Guo Spring 2012

Using Logic to Design Computer Components

Let s put together a Manual Processor

Chapter 2 Logic Gates and Introduction to Computer Architecture

WEEK 8.1 Registers and Counters. ECE124 Digital Circuits and Systems Page 1

Course Requirements & Evaluation Methods

Karnaugh Maps (K-map) Alternate representation of a truth table

Asynchronous counters, except for the first block, work independently from a system clock.

DM74LS153 Dual 1-of-4 Line Data Selectors/Multiplexers

Memory unit. 2 k words. n bits per word

54157 DM54157 DM74157 Quad 2-Line to 1-Line Data Selectors Multiplexers

CONTENTS PREFACE 1 INTRODUCTION 1 2 NUMBER SYSTEMS AND CODES 25. vii

Course: Bachelor of Science (B. Sc.) 1 st year. Subject: Electronic Equipment Maintenance. Scheme of Examination for Semester 1 & 2

Cyber Security Workshop Encryption Reference Manual

Transcription:

Company LOGO DKT 122/3 DIGITAL SYSTEM 1 E d i t y o u r s l o g a n h e r e CHAPTER 6 FUNCTIONS OF COMBINATIONAL LOGIC (ENCODER & DECODER, MUX & DEMUX)

Topic Outlines Company LOGO Encoder Decoder Multiplexers (MUX) Demultiplexers (DEMUX)

Topic Outlines Company LOGO Encoder Decoder Multiplexers (MUX) Demultiplexers (DEMUX)

Encoder Encoder converts information such as decimal number, alphabetical character, or symbols into some coded form, such as BCD or binary Encoder is usually used for: Data representation Data security

Encoder Question 1: Design a Decimal to BCD Encoder Hints: (a) Draw a Truth-Table showing input and output - How many inputs? : 10 (0 to 9) - How many outputs? : 4 because we need 4 bits to express 9 (1001) (b) From the Truth-Table, get the equation for each output - How many Boolean expression? : 4 since there are 4 outputs (c) Based on the output equation, draw a circuit for basic decimal-to-bcd encoder

Encoder Draw a Truth-Table showing input and output DECIMAL BCD CODE DIGIT A 3 A 2 A 1 A 0 0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 8 1 0 0 0 9 1 0 0 1

Encoder (b) From the Truth-Table, get the equation for each output: A 3 = I 8 OR I 9 A 2 = I 4 OR I 5 OR I 6 OR I 7 A 1 = I 2 OR I 3 OR I 6 OR I 7 A 0 = I 1 OR I 3 OR I 5 OR I 7 OR I 9 (c) Based on the output equation, draw a circuit for basic decimal-to-bcd encoder (a) (b) (a) Logic symbol for a 10-line-to 4 line encoder (b) Logic diagram. A 0-digit input is not needed because the BCD outputs are all low when there are no HIGH inputs

Decoder A decoder is a circuit that creates an output based on the binary states of a given input Do the opposite of encoder Decoder block diagram

Decoder Basic Binary Decoder Example: To determine when a binary 1001 occurs on the input of a digital circuit, AND gate can be used as the basic decoding element. AND gate -> produce HIGH output when all inputs are HIGH How to ensure that inputs to the AND gate are HIGH when binary 1001 occurs? Other than this input combinations, the output is 0 Decoding logic for the binary code 1001 with an active-high output.

Decoder Question 2: (a) Determine the logic required to decode the binary 11100 by producing a high level (active-high) on the output. A 4 A 3 A 2 A 1 A 0 Active-HIGH produce HIGH output Decoding function, Decodingfu nction, X A A A A A 4 3 2 1 0

Decoder 4-bit Decoder This type of decoder is called 4-line-to-16-line decoder or 1-of-16 decoder For a 4-bit decoder, there are 16 possible combinations (2 4 =16). This means that 16 decoding gates are required

Decoder 3 to 8 Binary Decoder Question: Is this active-high or active-low output?

-- don t care inputs -- Company LOGO Decoder Example: Seven Segment Decoder A seven segment decoder has 4-bit BCD input and the seven segment display code as its output: In minimizing the circuits for the segment outputs all nondecimal input combinations (1010, 1011, 1100,1101, 1110, 1111) are taken as don t-cares D C B A a b c d e f g 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 0 1 1 0 0 0 0 0 0 1 0 1 1 0 1 1 0 1 0 0 1 1 1 1 1 1 0 0 1 0 1 0 0 0 1 1 0 0 1 1 0 1 0 1 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 1 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 0 1 1 1 0 1 0 0 0 0 1 1 0 1 1 0 1 1 0 0 1 1 0 0 1 1 1 0 0 0 1 0 0 0 1 1 1 1 0 1 1 0 0 1 0 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0

Multiplexers (MUX) Company LOGO MUX is a device that allows digital information from several sources to be routed onto a single line for transmission It is made up of several datainput lines and a single output line. It also has data-select inputs which permits digital data on any one of the inputs to be switched to the output line. MUX is also known as data selectors n select inputs 2 n data inputs 1 data output Logic symbol for a 4-input multiplexer (4:1 MUX)

Multiplexers (MUX) 2:1 MUX Logic circuit Truth-table

Multiplexers (MUX) 4:1 MUX 2 data-select lines means that any one of the 4 data-input lines can be selected DATA-SELECT INPUTS S 0 S 1 INPUT SELECTED D 0 D 1 D 2 D 0 D 1 D 2 4-to-1 MUX Z Z 0 0 D 0 0 1 D 1 1 0 D 2 D 3 D 3 S 1 S 0 1 1 D 3 S 1 S 0 If a binary 0 (S 0 =0 and S 1 =0) is applied to the data-select lines, the data on input D 0 appear on the data-output line

4:1 MUX Multiplexers (MUX) Logic diagram for 4:1 MUX Total expression for the data output is: Y D 0 S1S0 D1 S1S0 D2S1 S0 D3S1S 0

Multiplexers (MUX) Question 3: Construct an 8:1 multiplexer using block diagram. 8 input lines means there must be 3 data select lines.

Demultiplexers (DEMUX) Company LOGO DEMUX reverse the multiplexing functions It takes digital information from one line and distributes it to a given number of output lines DEMUX is also known as data distributor 1 data input n select inputs 2 n data outputs 1-line to 4-line DEMUX

Demultiplexers (DEMUX) 1:4 DEMUX

Demultiplexers (DEMUX) Question 4: Construct a 1:4 DEMUX using block diagram. Show the equivalent Truth-Table. Q 0 1-4 Q I 1 0 DEMUX Q 2 Truth-table S1 S0 I1 Q3 Q2 Q1 Q0 S 1 S 0 I 0 S 1 S 0 Q 3 Block diagram Q0 Q1 Q2 0 0 1 0 0 0 1 0 1 1 0 0 1 0 1 0 1 0 1 0 0 1 1 1 1 0 0 0 Q3 Logic circuit