Review: MOSFET Modeling and CMOS Circuits. Sangyoung Park Institute for Real-Time Computer Systems Technische Universität München

Similar documents
Integrated Circuits & Systems

CO2005: Electronics I (FET) Electronics I, Neamen 3th Ed. 1

EDC Lesson 12: Transistor and FET Characteristics EDCLesson12- ", Raj Kamal, 1

BJT Ebers-Moll Model and SPICE MOSFET model

CHAPTER 10 Fundamentals of the Metal Oxide Semiconductor Field Effect Transistor

The MOSFET Transistor

Transconductance. (Saturated) MOSFET Small-Signal Model. The small-signal drain current due to v gs is therefore given by

CONTENTS. Preface Energy bands of a crystal (intuitive approach)

Lecture 8 MOSFET(I) MOSFET I-V CHARACTERISTICS

Field-Effect (FET) transistors

Lecture 9 - MOSFET (I) MOSFET I-V Characteristics. March 6, 2003

Lecture 9 MOSFET(II) MOSFET I-V CHARACTERISTICS(contd.)

Lecture 9 - MOSFET (I) MOSFET I-V Characteristics. October 6, 2005

COMMON-SOURCE JFET AMPLIFIER

MOSFET DEVICE MODELING FOR ANALOG CIRCUITS DESIGN

Lecture 090 Large Signal MOSFET Model (3/24/10) Page 090-1

Digital Integrated Circuit (IC) Layout and Design - Week 3, Lecture 5

Bob York. Transistor Basics - MOSFETs

MOS (metal-oxidesemiconductor) 李 2003/12/19

The MOS Transistor in Weak Inversion

Junction FETs. FETs. Enhancement Not Possible. n p n p n p

Here we introduced (1) basic circuit for logic and (2)recent nano-devices, and presented (3) some practical issues on nano-devices.

Lecture 030 DSM CMOS Technology (3/24/10) Page 030-1

EE-612: Nanoscale Transistors (Advanced VLSI Devices) Spring 2005

Fig6-22 CB configuration. Z i [6-54] Z o [6-55] A v [6-56] Assuming R E >> r e. A i [6-57]

MRF175GU MRF175GV The RF MOSFET Line 200/150W, 500MHz, 28V

An Introduction to the EKV Model and a Comparison of EKV to BSIM

A PHYSICAL MODEL FOR MOSFET OUTPUT RESISTANCE. by J. H. Huang, 2. H. Liu, M. C. Jeng, P. K. KO, C. Hu. Memorandum No.

SPICE MOSFET Declaration

Evaluation of the Surface State Using Charge Pumping Methods

MOS Capacitor CHAPTER OBJECTIVES

5.11 THE JUNCTION FIELD-EFFECT TRANSISTOR (JFET)

Source. Gate N+ N+ N+ Drain. Figure 1 Structure of D Series (Vertical type) (N channel) Channel. Source. Drain. Gate N N+ N+ P+ Substrate

Fourth generation MOSFET model and its VHDL-AMS implementation

Introduction to VLSI design (EECS 467)

Power MOSFET Basics Abdus Sattar, IXYS Corporation

Advanced VLSI Design CMOS Processing Technology

A Review of MOS Device Physics

MOS Transistor 6.1 INTRODUCTION TO THE MOSFET

Notes about Small Signal Model. for EE 40 Intro to Microelectronic Circuits

LAB IV. SILICON DIODE CHARACTERISTICS

Module 7 : I/O PADs Lecture 33 : I/O PADs

Statistical Models for Hot Electron Degradation in Nano-Scaled MOSFET Devices

Fabrication and Characterization of N- and P-Type a-si:h Thin Film Transistors

3. Diodes and Diode Circuits. 3. Diodes and Diode Circuits TLT-8016 Basic Analog Circuits 2005/2006 1

Intel s Revolutionary 22 nm Transistor Technology

CHAPTER 2 POWER AMPLIFIER

Lecture 30: Biasing MOSFET Amplifiers. MOSFET Current Mirrors.

Lecture 23 - Frequency Response of Amplifiers (I) Common-Source Amplifier. December 1, 2005

W04 Transistors and Applications. Yrd. Doç. Dr. Aytaç Gören

Lecture 060 Push-Pull Output Stages (1/11/04) Page ECE Analog Integrated Circuits and Systems II P.E. Allen

Title : Analog Circuit for Sound Localization Applications

ENEE 313, Spr 09 Midterm II Solution

Chapter 10 Advanced CMOS Circuits

Chapter 2 Sources of Variation

Features. Symbol JEDEC TO-220AB

Introduction to CMOS VLSI Design

AN105. Introduction: The Nature of VCRs. Resistance Properties of FETs

Automotive MOSFETs in Linear Applications: Thermal Instability

Field Effect Transistors

Semiconductor doping. Si solar Cell

California Eastern Laboratories AN1023 Converting GaAs FET Models For Different Nonlinear Simulators

Semiconductor Memories

MOSFET TECHNOLOGY ADVANCES DC-DC CONVERTER EFFICIENCY FOR PROCESSOR POWER

LAB 7 MOSFET CHARACTERISTICS AND APPLICATIONS

MOSFET N-channel enhancement switching transistor IMPORTANT NOTICE. use

AN3022. Establishing the Minimum Reverse Bias for a PIN Diode in a High-Power Switch. 1. Introduction. Rev. V2

potential in the centre of the sphere with respect to infinity.

Application Note AN-940

V-I CHARACTERISTICS OF DIODE

Introduction to VLSI Fabrication Technologies. Emanuele Baravelli

Basic Electronics Prof. Dr. Chitralekha Mahanta Department of Electronics and Communication Engineering Indian Institute of Technology, Guwahati

S-Band Low Noise Amplifier Using the ATF Application Note G004

MOS Transistors as Switches

Biasing in MOSFET Amplifiers

BUZ11. 30A, 50V, Ohm, N-Channel Power MOSFET. Features. [ /Title (BUZ1 1) /Subject. (30A, 50V, Ohm, N- Channel. Ordering Information

SIPMOS Small-Signal-Transistor

Chapter 8 Differential and Multistage Amplifiers. EE 3120 Microelectronics II

Application Notes FREQUENCY LINEAR TUNING VARACTORS FREQUENCY LINEAR TUNING VARACTORS THE DEFINITION OF S (RELATIVE SENSITIVITY)

Modeling the Characteristics of a High-k HfO 2 -Ta 2 O 5 Capacitor in Verilog-A

BJT Characteristics and Amplifiers

Lecture 17 The Bipolar Junction Transistor (I) Forward Active Regime

OptiMOS 3 Power-Transistor

Contents. State of the Art and Current Trends for Multiple Gate MOS Devices. Current, Charge and Capacitance Model for Multiple Gate MOSFETs

Surfacing the facts of DMOS Power RF transistors from Published Data Sheets

Inrush Current. Although the concepts stated are universal, this application note was written specifically for Interpoint products.

Characteristic curves of a solar cell

Slide 1. Slide 2. Slide 3. Cable Properties. Passive flow of current. Voltage Decreases With Distance

Depletion-Mode Power MOSFETs and Applications Abdus Sattar, IXYS Corporation

Solar Photovoltaic (PV) Cells

DISCRETE SEMICONDUCTORS DATA SHEET. BLF244 VHF power MOS transistor

High Open Circuit Voltage of MQW Amorphous Silicon Photovoltaic Structures

New materials on horizon for advanced logic technology in mobile era

Project 2B Building a Solar Cell (2): Solar Cell Performance

Characteristic and use

Lecture 21: Junction Field Effect Transistors. Source Follower Amplifier

Highly Scalable NAND Flash Memory Cell Design Embracing Backside Charge Storage

HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS

PHYSICS OF DEVICES ESONN 04. ARCES, University of Bologna. 8/19/2004 Enrico Sangiorgi. Enrico Sangiorgi. ARCES University of Bologna

MP MHz Boost Converter

Transcription:

Review: MOSFET Modeling and CMOS Circuits Sangyoung Park Institute for Real-Time Computer Systems park@rcs.ei.tum.de

Contents MOSFET Structure and Operation MOSFET Threshold Voltage 1st-Order Current-Voltage Characteristics Velocity Saturation Short-Channel Effect MOS Capacitance 2

MOSFET Structure and Operation MOSFET structure www.wikipedia.com 3

MOSFET Threshold Voltage Energy band diagram 4

MOSFET Structure and Operation Cut-off / sub-threshold / weak inversion mode Triode mode / linear region Saturation / active mode reference: http://en.wikipedia.org/wiki/file:mosfet_functioning.svg 5

MOSFET Structure and Operation Depletion Mobile holes are pushed down under the gate Weak inversion Depletion layer thickness increases and an initial layer of mobile electron appears at the surface of the silicon Strong inversion The concentration of the mobile electrons is increased until it becomes equal to the concentration of the holes in the substrate Depletion layer thickness remains constant 6

MOSFET Threshold Voltage Flat-band voltage: V FB The voltage that when applied to a MOS Capacitor produces zero net charge in the underlying semiconductor 7

MOSFET Threshold Voltage V GS required to produce strong inversion is threshold voltage V T Offset the induced depletion-layer charge Q B Need to bend the bands in the channel region by relative to the substrate Surface potential must be equal to The semiconductor surface that is normally p-type becomes n-type 8

MOSFET Threshold Voltage Rearrangement of V T Body effect coefficient 9

MOSFET Threshold Voltage With no body bias (V BS =0), and With body bias (V BS ), 10

1st-Order Current-Voltage Characteristics Cut off No inversion layer exists Drain current is approximately zero 11

1st-Order Current-Voltage Characteristics Linear when 12

1st-Order Current-Voltage Characteristics Drain current: In the 1st order model, the velocity is linearly proportional to the E field Carrier mobility in cm/s 13

1st-Order Current-Voltage Characteristics Drain current 14

1st-Order Current-Voltage Characteristics Saturation (pinched off) 15

1st-Order Current-Voltage Characteristics Saturation voltage Beyond the saturation voltage, I DS is obtained by 16

1st-Order Current-Voltage Characteristics Channel-length modulation 17

1st-Order Current-Voltage Characteristics Channel-length modulation Measured V-I characteristics show a weak function of V DS Width of the depletion layer between the pinch-off point and the drain Corrected saturation current 18

1st-Order Current-Voltage Characteristics The i D v DS characteristics for a device with k n (W/L) = 1.0 ma/ V 2 Channel-length modulation 19

Velocity Saturation Quadratic model is valid for long-channel devices Modern DSM devices Channel length has been scaled to the point where the vertical and horizontal electric fields may interact Saturation occurs at the pinch-off point is no longer valid Saturation occurs due to velocity saturation 0.18um device is rather linear than quadratic 20

Velocity Saturation Horizontal field acts to push the carriers to their velocity limit and cause Early saturation Mobility degradation Due to electron scattering caused by dangling bonds at the Si-SiO 2 interface Empirical values 21

Velocity Saturation Piece-wise continuous model Drain current 22

Short-Channel Effect Short-channel effect V T roll-off: charge partitioning model Long channel Short channel 23

Short-Channel Effect V T roll-off impact Threshold voltage reduces as L reduces I off increases Reduced control of the gate on the channel 24

MOS Capacitance Very important for transient simulation Thin oxide capacitance: C gs, C gd and C gb ) represented by C g Junction capacitance (C sb and C db ) Depletion layer capacitance (C jc ) associated with C gb 25

MOS Capacitance Thin oxide capacitance The most important MOS capacitance Two plates of the capacitance are defined as the gate and the channel Cg remains constant for over 25 years because both L and tox are scaled at the same rate 26

MOS Capacitance Area of source and drain Bottom area: A b =WY Side wall area: A sw =Wx j Junction capacitance 27

Note Slides are modified from lecture notes of Advanced Computer System Design from Seoul National University (Lecturer: Prof. Naehyuck Chang) 28