MOSFET transistor I-V characteristics

MOSFET transistor I-V characteristics Linear region: v DS «v GS Triode region: v DS < v GS i D = K[ 2( v GS )v DS ] 2 i D = K[ 2( v GS )v DS v DS ] K n K = = C ox µ n W ----- K 2L n v DS = v GS sat (current) Saturation region: v DS v GS i D = K[ ( v GS ) 2 ]( 1 + λv DS ) + v - GS i D + v DS - Lecture 20-1

Is the transistor in saturation region? v DS = v GS sat V t = 1V V D = 3.5V V D = 3.5V V G = 4V V G = V S = 2V V S = 2V Lecture 20-2

Body Effect The source and bulk will not be at zero volts all of the time The p-type bulk will be connected to the lowest supply voltage for an IC Discrete MOSFETs may have bulk tied directly to the source But for ICs we can assume that there can be a positive V SB for NMOSFETs V S2B =0 V S2 >0 V S2B >0 V B V S1B =0 V S1B =0 Lecture 20-3

Body Effect Positive V SB for NMOSFETs tends to increase Q B, hence decrease Q I, for a fixed V GS V S >0 V GS > V t n+ Q B0 + Q I V DS > 0 n+ V B Lecture 20-4

Body Effect Modeled as a change in the threshold voltage as a function of V SB The source is, by definition for NMOSFET, at a lower positive potential than the drain, which is why we use it as our reference voltage V t = V t0 + γ ( 2φ f + V SB 2φ f ) SPICE will calculate this variation in threshold voltage, or you can over-ride its calculation by directly specifying gamma Lecture 20-5

Temperature Variations The threshold voltage varies with temperature due to carrier generation in the substrate --- tends to decrease with increasing temperature ~2mV for every 1ºC increase V t = V t0 + γ ( 2φ f + V SB 2φ f ) K also changes with temperature due to change in mobility Tends to dominate temperature variation for large i 1 W D I --µ 2 n C ---- ( v ox L GS ) 2 Will i D increase or decrease with temperature? T 1 T 2 > T 1 Lecture 20-6

Where is drain, where is source? D S G B G B S n-channel transistor D p-channel transistor Lecture 20-7

All of the voltages are negative PMOSFETs Carrier mobility is about half of what it is for n channels S p + G D p + n B The bulk is now connected to the most positive potential in the circuit Strong inversion occurs when the channel becomes as p-type as it was n-type The inversion layer is a positive charge that is sourced by the larger potential and drained at the smallest potential The threshold voltage is negative for an enhancement PMOSFET Note that the flatband voltage (which is negative) effects now tend to increase the PFET threshold while they decreased the NFET threshold Lecture 20-8

PMOS The equations are the same, but all of the voltages are negative Triode region: v GS V t v DS v GS 2 i D = K[ 2( v GS ) v DS v DS ] K = 1 W --µ 2 n C ox ---- L A ------ V 2 i D is also negative --- positive charge flows into the drain Saturation expression is the same as it is for NFETs: +V dd i D = K[ ( v GS ) 2 ]( 1 + λ v DS ) sat Lecture 20-9

PMOS Characteristic appears to be the same, except that all of the voltages are negative V DS -5-4 -3-2 -1 0 10 V GS =-1.0V 0 I DS (µa) -10-20 -30-40 -50 V GS =-1.5V V GS =-2.0V W=1 micron L=1 microns V t0 = -1 volt K p =2e-5 (A/v 2 ) phi =-0.6 N D =1e15-60 -70 V GS =-2.5V -80-90 -100 V GS =-3.0V Lecture 20-10

PMOS But it is generally displayed as: -I DS (µa) 100 90 80 70 60 50 40 30 20 10 0-10 -V DS 0 1 2 3 4 5 V GS =-3.0V V GS =-2.5V V GS =-2.0V V GS =-1.5V V GS =-1.0V W=1 micron L=1 microns V t0 = -1 volt K p =2e-5 (A/v 2 ) phi =-0.6 N D =1e15 Lecture 20-11

Depletion Mode NMOSFET Depletion mode FETs have a channel implanted such that there is conduction with V GS =0 The operation is the same as the enhancement mode FET, but the threshold voltage is shifted V t is negative for depletion NMOS, and positive for depletion PMOS V S V GS V DS n+ n+ n+ p Lecture 20-12

Depletion Mode NMOSFET Negative gate voltage is required to turn the channel off I DS (ma) 0.4 0.2 V DS 0 1 2 3 4 5 V GS =2.0V V GS =1.0V W=1 micron L=1 microns V t0 = -2 volt K p =2e-5 (A/v 2 ) V GS =0.0V V GS =-1.0V 0.0 V GS =-2.0V Lecture 20-13

Depletion Mode NMOSFET The i DS vs. v GS characteristic is still quadratic in saturation V GS -4-3 -2-1 0 1 2 3 4 5 2 I DS (ma) 1 W=1 micron L=1 microns V t0 = -2 volt K p =2e-5 (A/v 2 ) 0 Lecture 20-14

Examples Find the largest value that R D can have before the transistor fails to operate in saturation 5V -5V R D 5kΩ V t = 2V K n = 20µA V 2 L = 10µm W = 400µm λ = 0 Lecture 20-15

Examples Find the drain currents and voltages for both transistors 10kΩ M2 10V 10V M1 15kΩ V t = 2V K n = 20µA V 2 L = 10µm W = 100µm λ = 0 Lecture 20-16

Examples What is the effective resistance of the transistor in the triode region? 10V 24.8kΩ V t = 1V K = 0.5mA V 2 Lecture 20-17

Examples Select the R s so that the gate voltage is 4V, the drain voltage is 4V and the current is 1mA. 10V R G1 10V V t = 2V R D K = 1mA V 2 λ = 0 R G2 R S Lecture 20-18

Examples Select the R s so that the transistor is in saturation with a drain current of 1.0mA and a drain voltage of 5V 10V R G1 V t = 1V K = 0.5mA V 2 λ = 0 R G2 R D Lecture 20-19

Examples Solve for the drain current and voltage 32kΩ 20V V t = 2V K = 1mA V 2 λ = 0 10MΩ 4kΩ Lecture 20-20