CURRENT LIMITING SINGLE CHANNEL DRIVER V OFFSET. Packages

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1 Features Floating channel designed for bootstrap operation Fully operational to +5V Tolerant to negative transient voltage dv/dt immune Gate drive supply range from 12 to 18V Undervoltage lockout Current detection and limiting loop to limit driven power transistor current Error lead indicates fault conditions and programs shutdown time Output in phase with input 2.5V, 5V and 15V input logic compatible Also available LEAD-Free Description CURRENT LIMITING SINGLE CHANNEL DRIVER The IR2125(S) is a high voltage, high speed power MOSFET and IGBT driver with over-current limiting protection circuitry. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. Logic inputs are compatible with standard CMOS or LSTTL outputs, down to 2.5V logic. The output driver features a high pulse current Product Summary V OFFSET I O +/- V OUT V CSth t on/off (typ.) Packages 8-Lead PDIP Data Sheet No. PD617 Rev.Q IR2125(S) & (PbF) 5V max. 1A / 2A 12-18V 23 mv 15 & 15 ns 16-Lead SOIC (Wide Body) buffer stage designed for minimum driver cross-conduction. The protection circuitry detects over-current in the driven power transistor and limits the gate drive voltage. Cycle by cycle shutdown is programmed by an external capacitor which directly controls the time interval between detection of the over-current limiting conditions and latched shutdown. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high or low side configuration which operates up to 5 volts. Typical Connection (Refer to Lead Assignments for correct pin configuration). This/These diagram(s) show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout. 1

2 Absolute Maximum Ratings Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Units V B High Side Floating Supply Voltage V S High Side Floating Offset Voltage V B - 25 V B +.3 V HO High Side Floating Output Voltage V S -.3 V B +.3 V CC Logic Supply Voltage V V IN Logic Input Voltage -.3 V CC +.3 V ERR Error Signal Voltage -.3 V CC +.3 V CS Current Sense Voltage V S -.3 V B +.3 dv s /dt Allowable Offset Supply Voltage Transient 5 V/ns P D Package Power T A +25 C (8 lead PDIP) 1. (16 lead SOIC) 1.25 Rth JA Thermal Resistance, Junction to Ambient (8 lead PDIP) 125 (16lLead SOIC) 1 T J Junction Temperature 15 T S Storage Temperature T L Lead Temperature (Soldering, 1 seconds) 3 W C/W C Recommended Operating Conditions The Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the recommended conditions. The V S offset rating is tested with all supplies biased at 15V differential. Symbol Definition Units V B High Side Floating Supply Voltage V S + 12 V S + 18 V S High Side Floating Offset Voltage Note 1 5 V HO High Side Floating Output Voltage V S V B V CC Logic Supply Voltage 18 V V IN Logic Input Voltage V CC V ERR Error Signal Voltage V CC V CS Current Sense Signal Voltage V S V B T A Ambient Temperature C Note 1: Logic operational for V S of -5 to +5V. Logic state held for V S of -5V to -V BS. (Please refer to the Design Tip DT97-3 for more details). 2

3 Dynamic Electrical Characteristics V BIAS (V CC, V BS ) = 15V, C L = 33 pf and T A = 25 C unless otherwise specified. The dynamic electrical characteristics are measured using the test circuit shown in Figures 3 through 6. Symbol Definition Figure Units Test Conditions t on Turn-On Propagation Delay V IN = & 5V ns V S = to 6V t off Turn-Off Propagation Delay t sd ERR Shutdown Propagation Delay µs t r Turn-On Rise Time t f Turn-Off Fall Time ns t cs CS Shutdown Propagation Delay µs t err CS to ERR Pull-Up Propagation Delay C ERR = 27 pf Static Electrical Characteristics V BIAS (V CC, V BS ) = 15V and T A = 25 C unless otherwise specified. The V IN, V TH and I IN parameters are referenced to COM. The V O and I O parameters are referenced to V S. Symbol Definition Figure Units Test Conditions V IH Logic 1 Input Voltage V IL Logic Input Voltage 15.8 V V CSTH+ CS Input Positive Going Threshold V CSTH- CS Input Negative Going Threshold mv V OH High Level Output Voltage, V BIAS - V O 18 1 I O = A V OL Low Level Output Voltage, V O 19 1 I O = A I LK Offset Supply Leakage Current 2 5 V B = V S = 5V I QBS Quiescent V BS Supply Current V IN = V CS = V or 5V I QCC Quiescent V CC Supply Current V IN = V CS = V or 5V I IN+ Logic 1 Input Bias Current µa V IN = 5V I IN- Logic Input Bias Current V IN = V I CS+ High CS Bias Current V CS = 3V I CS- Low CS Bias Current V CS = V V BSUV+ V BS Supply Undervoltage Positive Going Threshold V BSUV- V BS Supply Undervoltage Negative Going Threshold V CCUV+ V CC Supply Undervoltage Positive Going V Threshold V CCUV- V CC Supply Undervoltage Negative Going Threshold I ERR ERR Timing Charge Current V IN = 5V, V CS = 3V µa ERR < V ERR+ I ERR+ ERR Pull-Up Current V IN = 5V, V CS = 3V ma ERR > V ERR+ I ERR- ERR Pull-Down Current V IN = V I O+ Output High Short Circuit Pulsed Current V O = V, V IN = 5V A PW 1 µs I O- Output Low Short Circuit Pulsed Current V O = 15V, V IN = V PW 1 µs 3

4 Functional Block Diagram Lead Definitions Symbol Description V CC IN ERR COM V B HO V S CS Logic and gate drive supply Logic input for gate driver output (HO), in phase with HO Serves multiple functions; status reporting, linear mode timing and cycle by cycle logic shutdown Logic ground High side floating supply High side gate drive output High side floating supply return Current sense input to current sense comparator Lead Assignments 1 Vcc VB V CC IN ERR V B HO CS IN ERR COM HO CS VS COM V S Lead PDIP IR2125 Part Number 16 Lead SOIC (Wide Body) IR2125S 4

5 HV=1 to 6V ERR tsd HO 5

6 Turn-On Delay Time (ns) 3 2 Turn-On Time (ns) Figure 7A. Turn-On Time vs. Temperature VBIAS Supply Voltage (V) Figure 7B. Turn-On Time vs. Voltage Turn-Off Delay Time (ns) 3 2 Turn-Off Time (ns) Figure 8A. Turn-Off Time vs. Temperature VBIAS Supply Voltage (V) Figure 8B. Turn-Off Time vs. Voltage ERR to Output Shutdown Delay Time (µs) ERR to Output Shutdown Delay Time (µs) Figure 9A. ERR to Output Shutdown vs. Temperature VBIAS Supply Voltage (V) Figure 9B. ERR to Output Shutdown vs. Voltage 6

7 Turn-On Rise Time (ns) 6 4 Turn-On Rise Time (ns) Figure 1A. Turn-On Rise Time vs. Temperature VBIAS Supply Voltage (V) Figure 1B. Turn-On Rise Time vs. Voltage Turn-Off Fall Time (ns) 6 4 Turn-Off Fall Time (ns) Figure 11A. Turn-Off Fall Time vs. Temperature VBIAS Supply Voltage (V) Figure 11B. Turn-Off Fall Time vs. Voltage CS to Output Shutdown Delay Time (µs) CS to Output Shutdown Delay Time (µs) Figure 12A. CS to Output Shutdown vs. Temperature VBIAS Supply Voltage (V) Figure 12B. CS to Output Shutdown vs. Voltage 7

8 2. 2. CS to ERR Pull-Up Delay Time (µs) CS to ERR Pull-Up Delay Time (µs) Figure 13A. CS to ERR Pull-Up vs. Temperature. VBIAS Supply Voltage (V) Figure 13B. CS to ERR Pull-Up vs. Voltage Logic "1" Input Threshold (V) Logic "1" Input Threshold (V) Figure 14A. Logic 1 Input Threshold vs. Temperature VCC Logic Supply Voltage (V) Figure 14B. Logic 1 Input Threshold vs. Voltage Logic "" Input Threshold (V) Logic "" Input Threshold (V) Figure 15A. Logic Input Threshold vs. Temperature VCC Logic Supply Voltage (V) Figure 15B. Logic Input Threshold vs. Voltage 8

9 5 5 CS Input Positive Going Threshold (mv) CS Input Positive Going Threshold (mv) Figure 16A. CS Input Threshold (+) vs. Temperature Figure 16B. CS Input Threshold (+) vs. Voltage 5 5 CS Input Negative Going Threshold (mv) CS Input Negative Going Threshold (mv) Figure 17A. CS Input Threshold (-) vs. Temperature Figure 17B. CS Input Threshold (-) vs. Voltage High Level Output Voltage (V) High Level Output Voltage (V) Figure 18A. High Level Output vs. Temperature Figure 18B. High Level Output vs. Voltage 9

10 Low Level Output Voltage (V).6.4 Low Level Output Voltage (V) Figure 19A. Low Level Output vs. Temperature Figure 19B. Low Level Output vs. Voltage 5 5 Offset Supply Leakage Current (µa) Figure 2A. Offset Supply Current vs. Temperature Offset Supply Leakage Current (µa) VB Boost Voltage (V) Figure 2B. Offset Supply Current vs. Voltage VBS Supply Current (ma) VBS Supply Current (ma) Figure 21A. V BS Supply Current vs. Temperature Figure 21B. V BS Supply Current vs. Voltage 1

11 VCC Supply Current (ma) VCC Supply Current (ma) Figure 22A. V CC Supply Current vs. Temperature VCC Logic Supply Voltage (V) Figure 22B. V CC Supply Current vs. Voltage Logic "1" Input Bias Current (µa) Logic "1" Input Bias Current (µa) Figure 23A. Logic 1 Input Current vs. Temperature VCC Logic Supply Voltage (V) Figure 23B. Logic 1 Input Current vs. Voltage Logic "" Input Bias Current (µa) Logic "" Input Bias Current (µa) Figure 24A. Logic Input Current vs. Temperature VCC Logic Supply Voltage (V) Figure 24B. Logic Input Current vs. Voltage 11

12 "High" CS Bias Current (µa) "High" CS Bias Current (µa) Figure 25A. High CS Bias Current vs. Temperature. Figure 25B. High CS Bias Current vs. Voltage "Low" CS Bias Current (µa) "Low" CS Bias Current (µa) Figure 26A. Low CS Bias Current vs. Temperature Figure 26B. Low CS Bias Current vs. Voltage VBS Undervoltage Lockout + (V) VBS Undervoltage Lockout - (V) Figure 27. V BS Undervoltage (+) vs. Temperature 6. Figure 28. V BS Undervoltage (-) vs. Temperature 12

13 VCC Undervoltage Lockout + (V) VCC Undervoltage Lockout - (V) Figure 29. V CC Undervoltage (+) vs. Temperature 6. Figure 3. V CC Undervoltage (-) vs. Temperature ERR Timing Charge Current (µa) ERR Timing Charge Current (µa) Figure 31A. ERR Timing Charge Current vs. Temperature VCC Logic Supply Voltage (V) Figure 31B. ERR Timing Charge Current vs. Voltage ERR Pull-Up Current (ma) ERR Pull-Up Current (ma) Figure 32A. ERR Pull-Up Current vs. Temperature. VCC Logic Supply Voltage (V) Figure 32B. ERR Pull-Up Current vs. Voltage 13

14 ERR Pull-Down Current (ma) ERR Pull-Down Current (ma) Figure 33A. ERR Pull-Down Current vs.temperature V CC Logic Supply Voltage (V) Figure 33B. ERR Pull-Down Current vs. Voltage Output Source Current (A) Output Source Current (A) Figure 34A. Output Source Current vs. Temperature Figure 34B. Output Source Current vs. Voltage Output Sink Current (A) Output Sink Current (A) Figure 35A. Output Sink Current vs.temperature Figure 35B. Output Sink Current vs. Voltage 14

15 3 3 Turn-On Delay Time (ns) Turn-Off Delay Time (ns) Input Voltage (V) Input Voltage (V) Figure 36A. Turn-On Time vs. Input Voltage Figure 36B. Turn-Off Time vs. Input Voltage -3. VS Offset Supply Voltage (V) Figure 37. Maximum V S Negative Offset vs. Supply Voltage 15

16 Case outlines 8-Lead PDIP (MS-1AB) 16-Lead SOIC (wide body) (MS-13AA) 16

17 LEADFREE PART MARKING INFORMATION Part number IRxxxxxx Date code YWW? IR logo Pin 1 Identifier? MARKING CODE P Lead Free Released Non-Lead Free Released?XXXX Lot Code (Prod mode - 4 digit SPN code) Assembly site code Per SCOP 2-2 ORDER INFORMATION Basic Part (Non-Lead Free) 8-Lead PDIP IR2125 order IR Lead SOIC IR2125S order IR2125S Leadfree Part 8-Lead PDIP IIR2125 order IR2125PbF 14-Lead SOIC IR2125S order IR2125SPbF IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 9245 Tel: (31) This product has been qualified per industrial level Data and specifications subject to change without notice. 9/12/