Lecture 9 MOSFET(II) MOSFET I-V CHARACTERISTICS(contd.)



Similar documents
Lecture 8 MOSFET(I) MOSFET I-V CHARACTERISTICS

Lecture 9 - MOSFET (I) MOSFET I-V Characteristics. March 6, 2003

Lecture 9 - MOSFET (I) MOSFET I-V Characteristics. October 6, 2005

BJT Ebers-Moll Model and SPICE MOSFET model

COMMON-SOURCE JFET AMPLIFIER

Transconductance. (Saturated) MOSFET Small-Signal Model. The small-signal drain current due to v gs is therefore given by

Integrated Circuits & Systems

EDC Lesson 12: Transistor and FET Characteristics EDCLesson12- ", Raj Kamal, 1

Bob York. Transistor Basics - MOSFETs

An Introduction to the EKV Model and a Comparison of EKV to BSIM

Digital Integrated Circuit (IC) Layout and Design - Week 3, Lecture 5

AN105. Introduction: The Nature of VCRs. Resistance Properties of FETs

Field-Effect (FET) transistors

SMA Compound Semiconductors Lecture 2 - Metal-Semiconductor Junctions - Outline Introduction

Fig6-22 CB configuration. Z i [6-54] Z o [6-55] A v [6-56] Assuming R E >> r e. A i [6-57]

The MOS Transistor in Weak Inversion

CO2005: Electronics I (FET) Electronics I, Neamen 3th Ed. 1

3. Diodes and Diode Circuits. 3. Diodes and Diode Circuits TLT-8016 Basic Analog Circuits 2005/2006 1

Lecture 090 Large Signal MOSFET Model (3/24/10) Page 090-1

Lecture 17 The Bipolar Junction Transistor (I) Forward Active Regime

III. Reaction Kinetics

Notes about Small Signal Model. for EE 40 Intro to Microelectronic Circuits

EE-612: Nanoscale Transistors (Advanced VLSI Devices) Spring 2005

CHAPTER 10 Fundamentals of the Metal Oxide Semiconductor Field Effect Transistor

Small Signal Analysis of a PMOS transistor Consider the following PMOS transistor to be in saturation. Then, 1 2

CONTENTS. Preface Energy bands of a crystal (intuitive approach)

Chapter 10 Advanced CMOS Circuits

Junction FETs. FETs. Enhancement Not Possible. n p n p n p

5.11 THE JUNCTION FIELD-EFFECT TRANSISTOR (JFET)

Bipolar Junction Transistor Basics

Lecture 23 - Frequency Response of Amplifiers (I) Common-Source Amplifier. December 1, 2005

MOSFET DEVICE MODELING FOR ANALOG CIRCUITS DESIGN

Fourth generation MOSFET model and its VHDL-AMS implementation

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences

Power MOSFET Basics Abdus Sattar, IXYS Corporation

Basic Electronics Prof. Dr. Chitralekha Mahanta Department of Electronics and Communication Engineering Indian Institute of Technology, Guwahati

Figure 1. Diode circuit model

Transistors. NPN Bipolar Junction Transistor

Biasing in MOSFET Amplifiers

Diode Circuits. Operating in the Reverse Breakdown region. (Zener Diode)

CHAPTER 2 POWER AMPLIFIER

Characteristic and use

Lecture 30: Biasing MOSFET Amplifiers. MOSFET Current Mirrors.

California Eastern Laboratories AN1023 Converting GaAs FET Models For Different Nonlinear Simulators

MOS Transistors as Switches

Features. Symbol JEDEC TO-220AB

LAB 7 MOSFET CHARACTERISTICS AND APPLICATIONS

SPICE MOSFET Declaration

Lecture 21: Junction Field Effect Transistors. Source Follower Amplifier

Steps for D.C Analysis of MOSFET Circuits

Solar Cell Parameters and Equivalent Circuit

Depletion-Mode Power MOSFETs and Applications Abdus Sattar, IXYS Corporation

W04 Transistors and Applications. Yrd. Doç. Dr. Aytaç Gören

The MOSFET Transistor

IRF150 [REF:MIL-PRF-19500/543] 100V, N-CHANNEL. Absolute Maximum Ratings

AMPLIFIERS BJT BJT TRANSISTOR. Types of BJT BJT. devices that increase the voltage, current, or power level

2SK1056, 2SK1057, 2SK1058

Basic FET Ampli ers 6.0 PREVIEW 6.1 THE MOSFET AMPLIFIER

Transistor amplifiers: Biasing and Small Signal Model

A Review of MOS Device Physics

MOS Transistor 6.1 INTRODUCTION TO THE MOSFET

MOS (metal-oxidesemiconductor) 李 2003/12/19

GS66516T Top-side cooled 650 V E-mode GaN transistor Preliminary Datasheet

LAB IV. SILICON DIODE CHARACTERISTICS

Solid State Detectors = Semi-Conductor based Detectors

or, put slightly differently, the profit maximizing condition is for marginal revenue to equal marginal cost:

Understanding Low Drop Out (LDO) Regulators

An FET Audio Peak Limiter

Testing a power supply for line and load transients

IRF6201PbF. HEXFET Power MOSFET V DS 20 V. R DS(on) max mω. Q g (typical) 130 nc 27 A. Absolute Maximum Ratings

6.041/6.431 Spring 2008 Quiz 2 Wednesday, April 16, 7:30-9:30 PM. SOLUTIONS

Field Effect Transistors

Automotive MOSFETs in Linear Applications: Thermal Instability

Introduction to PSP MOSFET Model

Here we introduced (1) basic circuit for logic and (2)recent nano-devices, and presented (3) some practical issues on nano-devices.

A PHYSICAL MODEL FOR MOSFET OUTPUT RESISTANCE. by J. H. Huang, 2. H. Liu, M. C. Jeng, P. K. KO, C. Hu. Memorandum No.

Design and Construction of Variable DC Source for Laboratory Using Solar Energy

Evaluation of the Surface State Using Charge Pumping Methods

TPN4R712MD TPN4R712MD. 1. Applications. 2. Features. 3. Packaging and Internal Circuit Rev.4.0. Silicon P-Channel MOS (U-MOS )

DIODE CIRCUITS LABORATORY. Fig. 8.1a Fig 8.1b

IRLR8743PbF IRLU8743PbF HEXFET Power MOSFET

Lecture 060 Push-Pull Output Stages (1/11/04) Page ECE Analog Integrated Circuits and Systems II P.E. Allen

Features 1.7 A, 20 V. R DS(ON) Symbol Parameter Ratings Units

physics 1/12/2016 Chapter 20 Lecture Chapter 20 Traveling Waves

RoHS Compliant Containing no Lead, no Bromide and no Halogen. IRF9310PbF SO8 Tube/Bulk 95 IRF9310TRPbF SO8 Tape and Reel 4000

Lecture 17. Bipolar Junction Transistors (BJT): Part 1 Qualitative Understanding - How do they work? Reading: Pierret , 11.

BUZ11. 30A, 50V, Ohm, N-Channel Power MOSFET. Features. [ /Title (BUZ1 1) /Subject. (30A, 50V, Ohm, N- Channel. Ordering Information

Lecture - 4 Diode Rectifier Circuits

Application Note AN-940

IRF840. 8A, 500V, Ohm, N-Channel Power MOSFET. Features. Ordering Information. Symbol. Packaging. Data Sheet January 2002

OptiMOS 3 Power-Transistor

IRF A, 100V, Ohm, N-Channel Power MOSFET. Features. Ordering Information. Symbol. Packaging. Data Sheet January 2002

Design And Application Guide For High Speed MOSFET Gate Drive Circuits

TSM2N7002K 60V N-Channel MOSFET

Features. T A=25 o C unless otherwise noted. Symbol Parameter Ratings Units. (Note 1b) 0.46

C Soldering Temperature, for 10 seconds 300 (1.6mm from case )

Introduction to VLSI design (EECS 467)

Sheet Resistance = R (L/W) = R N L

APPLICATION NOTES: Dimming InGaN LED

BIPOLAR JUNCTION TRANSISTORS

Transcription:

Lecture 9 MOSFET(II) MOSFET I-V CHARACTERISTICS(contd.) Outline 1. The saturation regime 2. Backgate characteristics Reading Assignment: Howe and Sodini, Chapter 4, Section 4.4 Announcements: 1. Quiz#1: March 14, 7:30-9:30PM, Walker; covers Lectures #1-9; open book; must have calculator No Recitation on Wednesday, March 14: instructors or TAs available in their offices during recitation times 6.012 Spring 2007 Lecture 9 1

1. The Saturation Regime Geometry of problem Key Assumption (thus far): V BS = 0 V GS = V GB Regimes of operation: Cut-off: V GS < V T No inversion layer anywhere underneath the gate I D = 0 Linear: V GS >V T and 0 < V DS < V GS -V T : Inversion layer everywhere under the gate I D = W L µ nc ox V GS V DS 2 V T V DS 6.012 Spring 2007 Lecture 9 2

The Saturation Regime (contd.) Saturation: V GS > V T, and V DS > V GS -V T : Inversion layer pinched-off at drain end of channel I D = W 2L µ nc ox [ V GS V T ] 2 Output characteristics: Last lecture: To derive the above equations for I D, we used for Q N (y), the charge-control relation at location y: Q N (y) = C ox [ V GS V(y) V T ] for V GS V(y) V T.. Note that we assumed that (a) V BS = 0 V GS = V GB, and (b) V T is independent of y. See discussion on body effect in Section 4.4 of text. 6.012 Spring 2007 Lecture 9 3

The Saturation Regime (contd..) Review of Q N, E y, and V in linear regime as V DS increases: Ohmic drop along channel de-biases inversion layer current saturation. 6.012 Spring 2007 Lecture 9 4

The Saturation Regime (contd.) What happens when V DS = V GS V T? Charge control relation at drain: Q N (L) = C ox [ V GS V DS V T ]= 0 No inversion layer at the drain end of channel???!!! Pinch-off. At pinch-off: Charge control equation inaccurate around V T ; Electron concentration small but not zero; Electrons move fast because electric field is very high; Dominant electrostatic feature Acceptor charge There is no barrier to electron flow (on the contrary!). 6.012 Spring 2007 Lecture 9 5

The Saturation Regime (contd ) Voltage at pinch-off point (V=0 at source): Drain current at pinch-off: lateral electric field V DSsat = V GS V T electron concentration V GS V T I [ V V ] 2 Dsat GS T Also, L E y : I Dsat 1 L 6.012 Spring 2007 Lecture 9 6

The Saturation Regime (contd.) What happens if V DS > V GS V T? Depletion region separating pinch-off and drain widens To first order, I D does not increase past pinch-off: I D = I Dsat W 2L µ C [ V V ] 2 n ox GS T To second order, electrical channel length affected: L I D : I D 1 L L 1 L 1 + L L 6.012 Spring 2007 Lecture 9 7

The Saturation Regime (contd.) Experimental finding: with L L = λv DS λ 1 L Typically, λ = 0.1 µm V 1 L For L = 1µm, increase of V DS of 1V past V DSsat results in increase in I D of 10%. Improved model for the drain current in saturation: I D = W 2L µ nc ox ( V GS V T ) 2 [ 1 + λv DS ] 6.012 Spring 2007 Lecture 9 8

2. Backgate Characteristics There is a fourth terminal in a MOSFET: the body. What does it do? Key Assumption (thus far): V BS = 0 V GS = V GB Body contact allows application of bias to body with respect to inversion layer, V BS. Only interested in V BS < 0 (pn diode in reverse bias). Interested in effect on inversion layer examine for V GS > V T (keep it constant). 6.012 Spring 2007 Lecture 9 9

Backgate Characteristics (Contd.) Application of V BS < 0 increases potential build-up across semiconductor: 2φ p 2φ p V BS Depletion region at the source must widen to produce required extra field: 6.012 Spring 2007 Lecture 9 10

Backgate Characteristics (Contd.) Consequences of application of V BS < 0: -2φ p -2φ p -V BS Q B x dmax Since V GS is constant, V ox unchanged E ox unchanged Q S = Q G unchanged Q S = Q N + Q B unchanged, but Q B Q N inversion layer charge is reduced! For the same applied gate-to-source voltage V GS, application of V BS < 0 reduces the density of electrons in the inversion layer, in other words V T 6.012 Spring 2007 Lecture 9 11

Backgate Characteristics (Contd.) How does V T change with V BS? In V T formula change 2φ p to 2φ p V BS : V T GB (VBS ) = V FB 2φ p V BS + 1 C ox 2ε s qn a ( 2φ p V BS ) In MOSFETs, interested in V T between gate and source: V GB = V GS V BS V T GB = VT GS VBS Then: And: V = V + V GS T GB T BS V T GS (VBS ) = V FB 2φ p + 1 C ox 2ε s qn a ( 2φ p V BS ) V T (V BS ) In the context of the MOSFET, V T is always defined in terms of gate-to-source voltage. 6.012 Spring 2007 Lecture 9 12

Backgate Characteristics (Contd.) V T (V BS ) = V FB 2φ p + 1 C ox 2ε s qn a ( 2φ p V BS ) Define backgate effect parameter [units: V -1/2 ]: And: Then: γ = 1 C ox 2ε s qn a V To = V T (V BS = 0) [ ] V T (V BS ) = V To + γ 2φ p V BS 2φ p 6.012 Spring 2007 Lecture 9 13

Backgate Characteristics (Contd.) Triode Region V DS ~ 0.1V 6.012 Spring 2007 Lecture 9 14

What did we learn today? Summary of Key Concepts MOSFET in saturation (V DS V DSsat ): pinch-off point at drain-end of channel Electron concentration small, but Electrons move very fast; Pinch-off point does not represent a barrier to electron flow I Dsat increases slightly in saturation regime due to channel length modulation Backbias affects V T of MOSFET 6.012 Spring 2007 Lecture 9 15