Faturs Low-voltag and Standard-voltag Opration 2.7 (V CC = 2.7V to 5.5V).8 (V CC =.8V to 3.6V) Intrnally Organizd 65,536 x 8 Two-wir Srial Intrfac Schmitt Triggrs, Filtrd Inputs for Nois Supprssion Bidirctional Data Transfr Protocol MHz (5V), 400 khz (2.7V) and 00 khz (.8V) Compatibility Writ Protct Pin for Hardwar and Softwar Data Protction 28-byt Pag Writ Mod (Partial Pag Writs Allowd) Slf-timd Writ Cycl (5 ms Max) High Rliability Enduranc: 00,000 Writ Cycls Data Rtntion: 40 Yars Automotiv Dvics Availabl 8-lad PDIP, 8-lad EIAJ SOIC, 8-lad JEDEC SOIC, 8-lad TSSOP, 8-lad LAP, 8-lad SAP and 8-ball dbga2 Packags Di Sals: Wafr Form, Waffl Pack and Bumpd Di Dscription Th AT24C52 provids 524,288 bits of srial lctrically rasabl and programmabl rad only mmory (EEPROM) organizd as 65,536 words of 8 bits ach. Th dvic s cascadabl fatur allows up to four dvics to shar a common two-wir bus. Th dvic is optimizd for us in many industrial and commrcial applications whr lowpowr and low-voltag opration ar ssntial. Th dvics ar availabl in spacsaving 8-pin PDIP, 8-lad EIAJ SOIC, 8-lad JEDEC SOIC, 8-lad TSSOP, 8-lad Ladlss Array (LAP), and 8-lad SAP packags. In addition, th ntir family is availabl in 2.7V (2.7V to 5.5V) and.8v (.8V to 3.6V) vrsions. Two-wir Srial EEPROM 52K (65,536 x 8) AT24C52 Not: Not rcommndd for nw dsign; plas rfr to AT24C52B datasht. Tabl. Pin Configurations Pin Nam Function A0 A Addrss Inputs SDA Srial Data SCL Srial Clock Input WP Writ Protct NC No Connct A0 A NC GND 8-lad TSSOP 2 3 4 8 7 6 5 VCC WP SCL SDA 8-lad SOIC A0 A NC GND 8-lad PDIP 2 3 4 8 7 6 5 VCC WP SCL SDA A0 A NC GND 2 3 4 8 7 6 5 VCC WP SCL SDA 8-ball dbga2 8-lad Ladlss Array 8-lad SAP VCC WP SCL SDA 8 7 6 5 2 3 4 A0 A NC GND VCC WP SCL SDA 8 7 6 5 2 3 4 A0 A NC GND VCC WP SCL SDA 8 7 6 5 2 3 4 A0 A NC GND Bottom Viw Bottom Viw Bottom Viw Rv.
Absolut Maximum Ratings* Oprating Tmpratur... 55 C to +25 C Storag Tmpratur... 65 C to +50 C Voltag on Any Pin with Rspct to Ground....0V to +7.0V Maximum Oprating Voltag... 6.25V *NOTICE: Strsss byond thos listd undr Absolut Maximum Ratings may caus prmannt damag to th dvic. This is a strss rating only and functional opration of th dvic at ths or any othr conditions byond thos indicatd in th oprational sctions of this spcification is not implid. Exposur to absolut maximum rating conditions for xtndd priods may affct dvic rliability. DC Output Currnt... 5.0 ma Figur. Block Diagram 2 AT24C52
AT24C52 Pin Dscription SERIAL CLOCK (SCL): Th SCL input is usd to positiv dg clock data into ach EEPROM dvic and ngativ dg clock data out of ach dvic. SERIAL DATA (SDA): Th SDA pin is bidirctional for srial data transfr. This pin is opn-drain drivn and may b wir-ord with any numbr of othr opn-drain or opn collctor dvics. DEVICE/ADDRESSES (A, A0): Th A and A0 pins ar dvic addrss inputs that ar hardwird or lft not connctd for hardwar compatibility with othr AT24Cxx dvics. Whn th pins ar hardwird, as many as four 52K dvics may b addrssd on a singl bus systm (dvic addrssing is discussd in dtail undr th Dvic Addrssing sction. If th pins ar lft floating, th A and A0 pins will b intrnally pulld down to GND if th capacitiv coupling to th circuit board V CC plan is <3 pf. If coupling is >3 pf, Atml rcommnds conncting th addrss pins to GND. WRITE PROTECT (WP): Th writ protct input, whn connctd to GND, allows normal writ oprations. Whn WP is connctd high to V CC, all writ oprations to th mmory ar inhibitd. If th pin is lft floating, th WP pin will b intrnally pulld down to GND if th capacitiv coupling to th circuit board V CC plan is <3 pf. If coupling is >3 pf, Atml rcommnds conncting th pin to GND. Switching WP to V CC prior to a writ opration crats a softwar writ protct function. Mmory Organization AT24C52, 52K SERIAL EEPROM: Th 52K is intrnally organizd as 52 pags of 28-byts ach. Random word addrssing rquirs a 6-bit data word addrss. 3
Tabl 2. Pin Capacitanc () Applicabl ovr rcommndd oprating rang from T A = 25 C, f =.0 MHz, V CC = +.8V Symbol Tst Condition Max Units Conditions C I/O Input/Output Capacitanc (SDA) 8 pf V I/O = 0V C IN Input Capacitanc (A 0, A, SCL) 6 pf V IN = 0V Not:. This paramtr is charactrizd and is not 00% tstd. Tabl 3. DC Charactristics Applicabl ovr rcommndd oprating rang from: T AI = 40 C to +85 C, V CC = +.8V to +5.5V, T AC = 0 C to +70 C, V CC = +.8V to +5.5V (unlss othrwis notd) Symbol Paramtr Tst Condition Min Typ Max Units V CC Supply Voltag.8 3.6 V V CC2 Supply Voltag 2.7 5.5 V V CC3 Supply Voltag 4.5 5.5 V I CC Supply Currnt V CC = 5.0V READ at 400 khz.0 2.0 ma I CC2 Supply Currnt V CC = 5.0V WRITE at 400 khz 2.0 3.0 ma I SB I SB2 Standby Currnt (.8V option) Standby Currnt (2.7V option) Not:. V IL min and V IH max ar rfrnc only and ar not tstd. V CC =.8V.0 µa V IN = V CC or V SS V CC = 3.6V 3.0 V CC = 2.7V 2.0 µa V IN = V CC or V SS V CC = 5.5V 6.0 I SB3 Standby Currnt (5.0V option) V CC = 4.5-5.5V V IN = V CC or V SS 6.0 µa I LI Input Lakag Currnt V IN = V CC or V SS 0.0 3.0 µa I LO Output Lakag Currnt V OUT = V CC or V SS 0.05 3.0 µa V IL Input Low Lvl () 0.6 V CC x 0.3 V V IH Input High Lvl () V CC x 0.7 V CC + 0.5 V V OL2 Output Low Lvl V CC = 3.0V I OL = 2. ma 0.4 V V OL Output Low Lvl V CC =.8V I OL = 0.5 ma 0.2 V 4 AT24C52
AT24C52 Tabl 4. AC Charactristics Applicabl ovr rcommndd oprating rang from T A = 40 C to +85 C, V CC = +.8V to +5.5V, C L = 00 pf (unlss othrwis notd) Tst conditions ar listd in Not 2. Symbol Paramtr.8 Volt 2.7 Volt 5.0 Volt Min Max Min Max Min Max f SCL Clock Frquncy, SCL 00 400 000 khz t LOW Clock Puls Width Low 4.7.3 0.4 µs t HIGH Clock Puls Width High 4.0.0 0.4 µs t AA Clock Low to Data Out Valid 0. 4.5 0.05 0.9 0.05 0.55 µs t BUF Tim th bus must b fr bfor a nw transmission can start () 4.7.3 0.5 µs t HD.STA Start Hold Tim 4.0 0.6 0.25 µs t SU.STA Start St-up Tim 4.7 0.6 0.25 µs t HD.DAT Data In Hold Tim 0 0 0 µs t SU.DAT Data In St-up Tim 200 00 00 ns t R Inputs Ris Tim ().0 0.3 0.3 µs t F Inputs Fall Tim () 300 300 00 ns t SU.STO Stop St-up Tim 4.7 0.6 0.25 µs t DH Data Out Hold Tim 00 50 50 ns t WR Writ Cycl Tim 20 or 5 (3) 0 or 5 (3) 0 or 5 (3) ms Enduranc () 5.0V, 25 C, Pag Mod 00K 00K 00K Writ Cycls Nots:. This paramtr is charactrizd and is not 00% tstd. 2. AC masurmnt conditions: R L (conncts to V CC ):.3 kω (2.7V, 5V), 0 kω (.8V) Input puls voltags: 0.3V CC to 0.7V CC Input ris and fall tims: 50 ns Input and output timing rfrnc voltags: 0.5V CC 3. Th Writ Cycl Tim of 5 ms only applis to th AT24C52 dvics baring th procss lttr A on th packag (th mark is locatd in th lowr right cornr on th top sid of th packag). Units 5
Dvic Opration CLOCK and DATA TRANSITIONS: Th SDA pin is normally pulld high with an xtrnal dvic. Data on th SDA pin may chang only during SCL low tim priods (s Figur 4 on pag 7). Data changs during SCL high priods will indicat a start or stop condition as dfind blow. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must prcd any othr command (s Figur 5 on pag 8). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. Aftr a rad squnc, th stop command will plac th EEPROM in a standby powr mod (s Figur 5 on pag 8). ACKNOWLEDGE: All addrsss and data words ar srially transmittd to and from th EEPROM in 8-bit words. Th EEPROM snds a zro during th ninth clock cycl to acknowldg that it has rcivd ach word. STANDBY MODE: Th AT24C52 faturs a low powr standby mod which is nabld: a) upon powr-up and b) aftr th rcipt of th STOP bit and th compltion of any intrnal oprations. MEMORY RESET: Aftr an intrruption in protocol, powr loss or systm rst, any twowir part can b rst by following ths stps: (a) Clock up to 9 cycls, (b) look for SDA high in ach cycl whil SCL is high and thn (c) crat a start condition as SDA is high. 6 AT24C52
AT24C52 Figur 2. Bus Timing (SCL: Srial Clock, SDA: Srial Data I/O) Figur 3. Writ Cycl Timing (SCL: Srial Clock, SDA: Srial Data I/O) SCL SDA 8th BIT ACK WORDn STOP CONDITION t wr () START CONDITION Not:. Th writ cycl tim t WR is th tim from a valid stop condition of a writ squnc to th nd of th intrnal clar/writ cycl. Figur 4. Data Validity 7
Figur 5. Start and Stop Dfinition Figur 6. Output Acknowldg 8 AT24C52
AT24C52 Dvic Addrssing Writ Oprations Th 52K EEPROM rquirs an 8-bit dvic addrss word following a start condition to nabl th chip for a rad or writ opration (s Figur 7 on pag 0). Th dvic addrss word consists of a mandatory, 0 squnc for th first fiv most significant bits as shown. This is common to all two-wir EEPROM dvics. Th 52K uss th two dvic addrss bits A, A0 to allow as many as four dvics on th sam bus. Ths bits must compar to thir corrsponding hardwird input pins. Th A and A0 pins us an intrnal propritary circuit that biass thm to a logic low condition if th pins ar allowd to float. Th ighth bit of th dvic addrss is th rad/writ opration slct bit. A rad opration is initiatd if this bit is high and a writ opration is initiatd if this bit is low. Upon a compar of th dvic addrss, th EEPROM will output a 0. If a compar is not mad, th dvic will rturn to a standby stat. DATA SECURITY: Th AT24C52 has a hardwar data protction schm that allows th usr to Writ Protct th whol mmory whn th WP pin is at V CC. BYTE WRITE: A writ opration rquirs two 8-bit data word addrsss following th dvic addrss word and acknowldgmnt. Upon rcipt of this addrss, th EEPROM will again rspond with a 0 and thn clock in th first 8-bit data word. Following rcipt of th 8-bit data word, th EEPROM will output a 0. Th addrssing dvic, such as a microcontrollr, thn must trminat th writ squnc with a stop condition. At this tim th EEPROM ntrs an intrnally-timd writ cycl, t WR, to th nonvolatil mmory. All inputs ar disabld during this writ cycl and th EEPROM will not rspond until th writ is complt (s Figur 8 on pag ). PAGE WRITE: Th 52K EEPROM is capabl of 28-byt pag writs. A pag writ is initiatd th sam way as a byt writ, but th microcontrollr dos not snd a stop condition aftr th first data word is clockd in. Instad, aftr th EEPROM acknowldgs rcipt of th first data word, th microcontrollr can transmit up to 27 mor data words. Th EEPROM will rspond with a 0 aftr ach data word rcivd. Th microcontrollr must trminat th pag writ squnc with a stop condition (s Figur 9 on pag ). Th data word addrss lowr 7 bits ar intrnally incrmntd following th rcipt of ach data word. Th highr data word addrss bits ar not incrmntd, rtaining th mmory pag row location. Whn th word addrss, intrnally gnratd, rachs th pag boundary, th following byt is placd at th bginning of th sam pag. If mor than 28 data words ar transmittd to th EEPROM, th data word addrss will roll ovr and prvious data will b ovrwrittn. Th addrss roll ovr during writ is from th last byt of th currnt pag to th first byt of th sam pag. ACKNOWLEDGE POLLING: Onc th intrnally-timd writ cycl has startd and th EEPROM inputs ar disabld, acknowldg polling can b initiatd. This involvs snding a start condition followd by th dvic addrss word. Th Rad/Writ bit is rprsntativ of th opration dsird. Only if th intrnal writ cycl has compltd will th EEPROM rspond with a 0, allowing th rad or writ squnc to continu. 9
Rad Oprations Rad oprations ar initiatd th sam way as writ oprations with th xcption that th Rad/Writ slct bit in th dvic addrss word is st to. Thr ar thr rad oprations: currnt addrss rad, random addrss rad and squntial rad. CURRENT ADDRESS READ: Th intrnal data word addrss countr maintains th last addrss accssd during th last rad or writ opration, incrmntd by. This addrss stays valid btwn oprations as long as th chip powr is maintaind. Th addrss roll ovr during rad is from th last byt of th last mmory pag, to th first byt of th first pag. Onc th dvic addrss with th Rad/Writ slct bit st to is clockd in and acknowldgd by th EEPROM, th currnt addrss data word is srially clockd out. Th microcontrollr dos not rspond with an input 0 but dos gnrat a following stop condition (s Figur 0 on pag ). RANDOM READ: A random rad rquirs a dummy byt writ squnc to load in th data word addrss. Onc th dvic addrss word and data word addrss ar clockd in and acknowldgd by th EEPROM, th microcontrollr must gnrat anothr start condition. Th microcontrollr now initiats a currnt addrss rad by snding a dvic addrss with th Rad/Writ slct bit high. Th EEPROM acknowldgs th dvic addrss and srially clocks out th data word. Th microcontrollr dos not rspond with a 0 but dos gnrat a following stop condition (s Figur on pag ). SEQUENTIAL READ: Squntial rads ar initiatd by ithr a currnt addrss rad or a random addrss rad. Aftr th microcontrollr rcivs a data word, it rsponds with an acknowldg. As long as th EEPROM rcivs an acknowldg, it will continu to incrmnt th data word addrss and srially clock out squntial data words. Whn th mmory addrss limit is rachd, th data word addrss will roll ovr and th squntial rad will continu. Th squntial rad opration is trminatd whn th microcontrollr dos not rspond with a 0 but dos gnrat a following stop condition (s Figur 2 on pag 2). Figur 7. Dvic Addrss 0 AT24C52
AT24C52 Figur 8. Byt Writ Figur 9. Pag Writ Figur 0. Currnt Addrss Rad Figur. Random Rad
Figur 2. Squntial Rad 2 AT24C52
AT24C52 Ordring Information () Ordring Cod Packag Opration Rang AT24C52C-0CU-2.7 (2) AT24C52C-0CU-.8 (2) AT24C52-0PU-2.7 (2) AT24C52-0PU-.8 (2) AT24C52W-0SU-2.7 (2) AT24C52W-0SU-.8 (2) AT24C52N-0SU-2.7 (2) AT24C52N-0SU-.8 (2) AT24C52-0TU-2.7 (2) AT24C52-0TU-.8 (2) AT24C52Y4-0YU-.8 (2) AT24C52U4-0UU-.8 (2) 8CN 8CN 8P3 8P3 8S2 8S2 8S 8S 8A2 8A2 8Y4 8U4- Lad-fr/Halogn-fr/ Industrial Tmpratur ( 40 C to 85 C) AT24C52-W.8- (3) Di Sal Industrial Tmpratur ( 40 C to 85 C) Nots:. For 2.7V dvics usd in th 4.5V to 5.5V rang, plas rfr to prformanc valus in th AC and DC charactristics tabls. 2. U dsignats Grn packag + RoHS compliant. 3. Availabl in waffl pack and wafr form; ordr as SL788 for inklss wafr form. Bumpd di availabl upon rqust. Plas contact Srial EEPROM markting. Packag Typ 8CN 8-lad, 0.300" Wid, Ladlss Array Packag (LAP) 8P3 8-lad, 0.300" Wid, Plastic Dual In-lin Packag (PDIP) 8S2 8-lad, 0.200 Wid, Plastic Gull Wing Small Outlin Packag (EIAJ SOIC) 8S 8-lad, 0.50 Wid, Plastic Gull Wing Small Outlin Packag (JEDEC SOIC) 8A2 8-lad, 4.4 mm Body, Plastic Thin Shrink Small Outlin Packag (TSSOP) 8Y4 8-lad, 6.00 mm x 4.90 mm Body, Dual Footprint, Non-ladd, Small Array Packag (SAP) 8U4-8-ball, di Ball Grid Array Packag (dbga2) Options 2.7 Low-voltag (2.7V to 5.5V).8 Low-voltag (.8V to 3.6V) 3
Packaging Information 8U4- dbga2 A BALL PAD CORNER D 5. b E TOP VIEW A BALL PAD CORNER A2 A A 2 SIDE VIEW A B C () D d (d) BOTTOM VIEW 8 SOLDER BALLS 5. Dimnsion 'b' is masurd at th maximum soldr ball diamtr. COMMON DIMENSIONS (Unit of Masur = mm) SYMBOL MIN NOM MAX NOTE A 0.8 0.9.00 A 0.5 0.20 0.25 A2 0.40 0.45 0.50 b 0.25 0.30 0.35 D 2.47 BSC E 4.07 BSC 0.75 BSC 0.74 REF d 0.75 BSC d 0.80 REF This drawing is for gnral information only. R 50 E. Chynn Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8U4-, 8-ball, 2.47 x 4.07 mm Body, 0.75 mm pitch, Small Di Ball Grid Array Packag (dbga2) /5/05 DRAWING NO. REV. PO8U4- A 4 AT24C52
AT24C52 8CN LAP Markd Pin Indntifir E D A A Top Viw Sid Viw 0.0 mm TYP 8 L Pin Cornr 7 2 COMMON DIMENSIONS (Unit of Masur = mm) SYMBOL MIN NOM MAX NOTE 6 3 b A 0.94.04.4 A 0.30 0.34 0.38 b 0.36 0.4 0.46 5 4 D 7.90 8.00 8.0 L E 4.90 5.00 5.0.27 BSC Bottom Viw 0.60 REF L 0.62.0.67 0.72 L 0.92 0.97.02 Not: R. Mtal Pad Dimnsions. 2. All xposd mtal ara shall hav th following finishd platings. Ni: 0.0005 to 0.05 mm Au: 0.0005 to 0.00 mm 50 E.Chynn Mtn Blvd. Colorado Springs, CO 80906 TITLE 8CN, 8-lad (8 x 5 x.04 mm Body), Lad Pitch.27 mm, Ladlss Array Packag (LAP) /8/04 DRAWING NO. REV. 8CN B 5
8P3 PDIP E E N Top Viw c A End Viw D D A2 A COMMON DIMENSIONS (Unit of Masur = inchs) SYMBOL MIN NOM MAX NOTE A 0.20 2 A2 0.5 0.30 0.95 b 0.04 0.08 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.00 0.04 b3 4 PLCS b2 b L D 0.355 0.365 0.400 3 D 0.005 3 E 0.300 0.30 0.325 4 E 0.240 0.250 0.280 3 Sid Viw 0.00 BSC A 0.300 BSC 4 L 0.5 0.30 0.50 2 Nots: R. This drawing is for gnral information only; rfr to JEDEC Drawing MS-00, Variation BA, for additional information. 2. Dimnsions A and L ar masurd with th packag satd in JEDEC sating plan Gaug GS-3. 3. D, D and E dimnsions do not includ mold Flash or protrusions. Mold Flash or protrusions shall not xcd 0.00 inch. 4. E and A masurd with th lads constraind to b prpndicular to datum. 5. Pointd or roundd lad tips ar prfrrd to as insrtion. 6. b2 and b3 maximum dimnsions do not includ Dambar protrusions. Dambar protrusions shall not xcd 0.00 (0.25 mm). 2325 Orchard Parkway San Jos, CA 953 TITLE 8P3, 8-lad, 0.300" Wid Body, Plastic Dual In-lin Packag (PDIP) DRAWING NO. 8P3 0/09/02 REV. B 6 AT24C52
AT24C52 8S2 EIAJ SOIC C E E N L Top Viw D Sid Viw b A A End Viw COMMON DIMENSIONS (Unit of Masur = mm) SYMBOL MIN NOM MAX NOTE A.70 2.6 A 0.05 0.25 b 0.35 0.48 5 C 0.5 0.35 5 D 5.3 5.35 E 5.8 5.40 2, 3 E 7.70 8.26 L 0.5 0.85 0 8.27 BSC 4 Nots:. This drawing is for gnral information only; rfr to EIAJ Drawing EDR-7320 for additional information. 2. Mismatch of th uppr and lowr dis and rsin burrs ar not includd. 3. It is rcommndd that uppr and lowr cavitis b qual. If thy ar diffrnt, th largr dimnsion shall b rgardd. 4. Dtrmins th tru gomtric position. 5. Valus b and C apply to pb/sn soldr platd trminal. Th standard thicknss of th soldr layr shall b 0.00 +0.00/ 0.005 mm. R 2325 Orchard Parkway San Jos, CA 953 TITLE 8S2, 8-lad, 0.209" Body, Plastic Small Outlin Packag (EIAJ) DRAWING NO. 8S2 0/7/03 REV. C 7
8S JEDEC SOIC C E E N L Top Viw End Viw B A COMMON DIMENSIONS (Unit of Masur = mm) D Sid Viw A SYMBOL MIN NOM MAX NOTE A.35.75 A 0.0 0.25 B 0.3 0.5 C 0.7 0.25 D 4.80 5.00 E 3.8 3.99 E 5.79 6.20.27 BSC L 0.40.27 0 8 Not: Ths drawings ar for gnral information only. Rfr to JEDEC Drawing MS-02, Variation AA for propr dimnsions, tolrancs, datums, tc. 0/7/03 R 50 E. Chynn Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8S, 8-lad (0.50" Wid Body), Plastic Gull Wing Small Outlin (JEDEC SOIC) DRAWING NO. 8S REV. B 8 AT24C52
AT24C52 8A2 TSSOP 3 2 Pin indicator this cornr E E L N Top Viw L End Viw b D Sid Viw A2 A COMMON DIMENSIONS (Unit of Masur = mm) SYMBOL MIN NOM MAX NOTE D 2.90 3.00 3.0 2, 5 E 6.40 BSC E 4.30 4.40 4.50 3, 5 A.20 A2 0.80.00.05 b 0.9 0.30 4 0.65 BSC L 0.45 0.60 0.75 L.00 REF Nots:. This drawing is for gnral information only. Rfr to JEDEC Drawing MO-53, Variation AA, for propr dimnsions, tolrancs, datums, tc. 2. Dimnsion D dos not includ mold Flash, protrusions or gat burrs. Mold Flash, protrusions and gat burrs shall not xcd 0.5 mm (0.006 in) pr sid. 3. Dimnsion E dos not includ intr-lad Flash or protrusions. Intr-lad Flash and protrusions shall not xcd 0.25 mm (0.00 in) pr sid. 4. Dimnsion b dos not includ Dambar protrusion. Allowabl Dambar protrusion shall b 0.08 mm total in xcss of th b dimnsion at maximum matrial condition. Dambar cannot b locatd on th lowr radius of th foot. Minimum spac btwn protrusion and adjacnt lad is 0.07 mm. 5. Dimnsion D and E to b dtrmind at Datum Plan H. 5/30/02 R 2325 Orchard Parkway San Jos, CA 953 TITLE 8A2, 8-lad, 4.4 mm Body, Plastic Thin Shrink Small Outlin Packag (TSSOP) DRAWING NO. 8A2 REV. B 9
8Y4 SAP PIN INDEX AREA A PIN ID D E D L E A A b COMMON DIMENSIONS (Unit of Masur = mm) SYMBOL MIN NOM MAX NOTE A 0.90 A 0.00 0.05 D 5.80 6.00 6.20 E 4.70 4.90 5.0 D 2.85 3.00 3.5 E 2.85 3.00 3.5 b 0.35 0.40 0.45.27 TYP 3.8 REF L 0.50 0.60 0.70 5/24/04 R 50 E. Chynn Mtn. Blvd. Colorado Springs, CO 8087 TITLE 8Y4, 8-lad (6.00 x 4.90 mm Body) SOIC Array Packag (SAP) Y4 DRAWING NO. 8Y4 REV. A 20 AT24C52
AT24C52 Rvision History Doc. Rv. Dat Commnts 6O /2007 Rvision history implmntd. Addd Not to Pag rcommnding nw dvic. 2
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